1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t wait; /* WAIT "prefix" present */
50 uint8_t lock; /* Lock prefix present */
51 uint8_t vex[3]; /* VEX prefix present */
52 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
53 uint8_t vex_m; /* VEX.M field */
55 uint8_t vex_lp; /* VEX.LP fields */
56 uint32_t rex; /* REX prefix present */
59 #define getu8(x) (*(uint8_t *)(x))
61 /* Littleendian CPU which can handle unaligned references */
62 #define getu16(x) (*(uint16_t *)(x))
63 #define getu32(x) (*(uint32_t *)(x))
64 #define getu64(x) (*(uint64_t *)(x))
66 static uint16_t getu16(uint8_t *data)
68 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
70 static uint32_t getu32(uint8_t *data)
72 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
74 static uint64_t getu64(uint8_t *data)
76 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
80 #define gets8(x) ((int8_t)getu8(x))
81 #define gets16(x) ((int16_t)getu16(x))
82 #define gets32(x) ((int32_t)getu32(x))
83 #define gets64(x) ((int64_t)getu64(x))
85 /* Important: regval must already have been adjusted for rex extensions */
86 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
88 if (!(regflags & (REGISTER|REGMEM)))
89 return 0; /* Registers not permissible?! */
93 if (!(REG_AL & ~regflags))
95 if (!(REG_AX & ~regflags))
97 if (!(REG_EAX & ~regflags))
99 if (!(REG_RAX & ~regflags))
101 if (!(REG_DL & ~regflags))
103 if (!(REG_DX & ~regflags))
105 if (!(REG_EDX & ~regflags))
107 if (!(REG_RDX & ~regflags))
109 if (!(REG_CL & ~regflags))
111 if (!(REG_CX & ~regflags))
113 if (!(REG_ECX & ~regflags))
115 if (!(REG_RCX & ~regflags))
117 if (!(FPU0 & ~regflags))
119 if (!(XMM0 & ~regflags))
121 if (!(YMM0 & ~regflags))
123 if (!(REG_CS & ~regflags))
124 return (regval == 1) ? R_CS : 0;
125 if (!(REG_DESS & ~regflags))
126 return (regval == 0 || regval == 2
127 || regval == 3 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_FSGS & ~regflags))
129 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
130 if (!(REG_SEG67 & ~regflags))
131 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
133 /* All the entries below look up regval in an 16-entry array */
134 if (regval < 0 || regval > 15)
137 if (!(REG8 & ~regflags)) {
138 if (rex & (REX_P|REX_NH))
139 return nasm_rd_reg8_rex[regval];
141 return nasm_rd_reg8[regval];
143 if (!(REG16 & ~regflags))
144 return nasm_rd_reg16[regval];
145 if (!(REG32 & ~regflags))
146 return nasm_rd_reg32[regval];
147 if (!(REG64 & ~regflags))
148 return nasm_rd_reg64[regval];
149 if (!(REG_SREG & ~regflags))
150 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
151 if (!(REG_CREG & ~regflags))
152 return nasm_rd_creg[regval];
153 if (!(REG_DREG & ~regflags))
154 return nasm_rd_dreg[regval];
155 if (!(REG_TREG & ~regflags)) {
157 return 0; /* TR registers are ill-defined with rex */
158 return nasm_rd_treg[regval];
160 if (!(FPUREG & ~regflags))
161 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
162 if (!(MMXREG & ~regflags))
163 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
164 if (!(XMMREG & ~regflags))
165 return nasm_rd_xmmreg[regval];
166 if (!(YMMREG & ~regflags))
167 return nasm_rd_ymmreg[regval];
173 * Process a DREX suffix
175 static uint8_t *do_drex(uint8_t *data, insn *ins)
177 uint8_t drex = *data++;
178 operand *dst = &ins->oprs[ins->drexdst];
180 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
181 return NULL; /* OC0 mismatch */
182 ins->rex = (ins->rex & ~7) | (drex & 7);
184 dst->segment = SEG_RMREG;
185 dst->basereg = drex >> 4;
191 * Process an effective address (ModRM) specification.
193 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
194 int segsize, operand * op, insn *ins)
196 int mod, rm, scale, index, base;
200 mod = (modrm >> 6) & 03;
203 if (mod != 3 && rm == 4 && asize != 16)
206 if (ins->rex & REX_D) {
207 data = do_drex(data, ins);
213 if (mod == 3) { /* pure register version */
214 op->basereg = rm+(rex & REX_B ? 8 : 0);
215 op->segment |= SEG_RMREG;
224 * <mod> specifies the displacement size (none, byte or
225 * word), and <rm> specifies the register combination.
226 * Exception: mod=0,rm=6 does not specify [BP] as one might
227 * expect, but instead specifies [disp16].
229 op->indexreg = op->basereg = -1;
230 op->scale = 1; /* always, in 16 bits */
261 if (rm == 6 && mod == 0) { /* special case */
265 mod = 2; /* fake disp16 */
269 op->segment |= SEG_NODISP;
272 op->segment |= SEG_DISP8;
273 op->offset = (int8_t)*data++;
276 op->segment |= SEG_DISP16;
277 op->offset = *data++;
278 op->offset |= ((unsigned)*data++) << 8;
284 * Once again, <mod> specifies displacement size (this time
285 * none, byte or *dword*), while <rm> specifies the base
286 * register. Again, [EBP] is missing, replaced by a pure
287 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
288 * and RIP-relative addressing in 64-bit mode.
291 * indicates not a single base register, but instead the
292 * presence of a SIB byte...
294 int a64 = asize == 64;
299 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
301 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
303 if (rm == 5 && mod == 0) {
305 op->eaflags |= EAF_REL;
306 op->segment |= SEG_RELATIVE;
307 mod = 2; /* fake disp32 */
311 op->disp_size = asize;
314 mod = 2; /* fake disp32 */
317 if (rm == 4) { /* process SIB */
318 scale = (sib >> 6) & 03;
319 index = (sib >> 3) & 07;
322 op->scale = 1 << scale;
324 if (index == 4 && !(rex & REX_X))
325 op->indexreg = -1; /* ESP/RSP cannot be an index */
327 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
329 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
331 if (base == 5 && mod == 0) {
333 mod = 2; /* Fake disp32 */
335 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
337 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
345 op->segment |= SEG_NODISP;
348 op->segment |= SEG_DISP8;
349 op->offset = gets8(data);
353 op->segment |= SEG_DISP32;
354 op->offset = gets32(data);
363 * Determine whether the instruction template in t corresponds to the data
364 * stream in data. Return the number of bytes matched if so.
366 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
368 static int matches(const struct itemplate *t, uint8_t *data,
369 const struct prefix_info *prefix, int segsize, insn *ins)
371 uint8_t *r = (uint8_t *)(t->code);
372 uint8_t *origdata = data;
373 bool a_used = false, o_used = false;
374 enum prefixes drep = 0;
375 enum prefixes dwait = 0;
376 uint8_t lock = prefix->lock;
377 int osize = prefix->osize;
378 int asize = prefix->asize;
381 struct operand *opx, *opy;
383 int s_field_for = -1; /* No 144/154 series code encountered */
385 int regmask = (segsize == 64) ? 15 : 7;
387 for (i = 0; i < MAX_OPERANDS; i++) {
388 ins->oprs[i].segment = ins->oprs[i].disp_size =
389 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
392 ins->rex = prefix->rex;
393 memset(ins->prefixes, 0, sizeof ins->prefixes);
395 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
398 if (prefix->rep == 0xF2)
400 else if (prefix->rep == 0xF3)
403 dwait = prefix->wait ? P_WAIT : 0;
405 while ((c = *r++) != 0) {
406 op1 = (c & 3) + ((opex & 1) << 2);
407 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
408 opx = &ins->oprs[op1];
409 opy = &ins->oprs[op2];
430 int t = *r++, d = *data++;
431 if (d < t || d > t + 7)
434 opx->basereg = (d-t)+
435 (ins->rex & REX_B ? 8 : 0);
436 opx->segment |= SEG_RMREG;
443 opx->offset = (int8_t)*data++;
444 opx->segment |= SEG_SIGNED;
448 opx->offset = *data++;
452 opx->offset = *data++;
456 opx->offset = getu16(data);
462 opx->offset = getu32(data);
465 opx->offset = getu16(data);
468 if (segsize != asize)
469 opx->disp_size = asize;
474 opx->offset = getu32(data);
481 opx->offset = getu16(data);
487 opx->offset = getu32(data);
493 opx->offset = getu64(data);
501 opx->offset = gets8(data++);
502 opx->segment |= SEG_RELATIVE;
506 opx->offset = getu64(data);
511 opx->offset = gets16(data);
513 opx->segment |= SEG_RELATIVE;
514 opx->segment &= ~SEG_32BIT;
518 opx->segment |= SEG_RELATIVE;
520 opx->offset = gets16(data);
522 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
523 } else if (osize == 32) {
524 opx->offset = gets32(data);
526 opx->segment &= ~SEG_64BIT;
527 opx->segment |= SEG_32BIT;
529 if (segsize != osize) {
531 (opx->type & ~SIZE_MASK)
532 | ((osize == 16) ? BITS16 : BITS32);
537 opx->offset = gets32(data);
539 opx->segment |= SEG_32BIT | SEG_RELATIVE;
548 opx->segment |= SEG_RMREG;
549 data = do_ea(data, modrm, asize, segsize, opy, ins);
552 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
557 if (s_field_for == op1) {
558 opx->offset = gets8(data);
561 opx->offset = getu16(data);
568 s_field_for = (*data & 0x02) ? op1 : -1;
569 if ((*data++ & ~0x02) != *r++)
574 if (s_field_for == op1) {
575 opx->offset = gets8(data);
578 opx->offset = getu32(data);
589 ins->rex |= REX_D|REX_OC;
594 data = do_drex(data, ins);
601 uint8_t ximm = *data++;
603 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
604 ins->oprs[c >> 3].segment |= SEG_RMREG;
605 ins->oprs[c & 7].offset = ximm & 15;
611 uint8_t ximm = *data++;
617 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
618 ins->oprs[c >> 4].segment |= SEG_RMREG;
624 uint8_t ximm = *data++;
627 ins->oprs[c].basereg = (ximm >> 4) & regmask;
628 ins->oprs[c].segment |= SEG_RMREG;
642 if (((modrm >> 3) & 07) != (c & 07))
643 return false; /* spare field doesn't match up */
644 data = do_ea(data, modrm, asize, segsize, opy, ins);
655 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
658 if ((vexm & 0x1f) != prefix->vex_m)
661 switch (vexwlp & 030) {
663 if (prefix->rex & REX_W)
667 if (!(prefix->rex & REX_W))
671 case 020: /* VEX.W is a don't care */
678 if ((vexwlp & 007) != prefix->vex_lp)
681 opx->segment |= SEG_RMREG;
682 opx->basereg = prefix->vex_v;
692 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
695 if ((vexm & 0x1f) != prefix->vex_m)
698 switch (vexwlp & 030) {
700 if (ins->rex & REX_W)
704 if (!(ins->rex & REX_W))
708 break; /* Need to do anything special here? */
711 if ((vexwlp & 007) != prefix->vex_lp)
714 if (prefix->vex_v != 0)
736 if (asize != segsize)
750 if (prefix->rex & REX_B)
755 if (prefix->rex & REX_X)
760 if (prefix->rex & REX_R)
765 if (prefix->rex & REX_W)
784 if (osize != (segsize == 16) ? 16 : 32)
791 ins->rex |= REX_W; /* 64-bit only instruction */
797 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
808 int t = *r++, d = *data++;
809 if (d < t || d > t + 15)
812 ins->condition = d - t;
822 if (prefix->rep != 0xF2)
828 if (prefix->rep != 0xF3)
853 if (prefix->wait != 0x9B)
859 ins->oprs[0].basereg = (*data++ >> 3) & 7;
863 if (prefix->osp || prefix->rep)
868 if (!prefix->osp || prefix->rep)
874 if (prefix->osp || prefix->rep != 0xf2)
880 if (prefix->osp || prefix->rep != 0xf3)
908 return false; /* Unknown code */
912 if (!vex_ok && (ins->rex & REX_V))
915 /* REX cannot be combined with DREX or VEX */
916 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
920 * Check for unused rep or a/o prefixes.
922 for (i = 0; i < t->operands; i++) {
923 if (ins->oprs[i].segment != SEG_RMREG)
928 if (ins->prefixes[PPS_LREP])
930 ins->prefixes[PPS_LREP] = P_LOCK;
933 if (ins->prefixes[PPS_LREP])
935 ins->prefixes[PPS_LREP] = drep;
937 ins->prefixes[PPS_WAIT] = dwait;
939 if (osize != ((segsize == 16) ? 16 : 32)) {
940 enum prefixes pfx = 0;
954 if (ins->prefixes[PPS_OSIZE])
956 ins->prefixes[PPS_OSIZE] = pfx;
959 if (!a_used && asize != segsize) {
960 if (ins->prefixes[PPS_ASIZE])
962 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
965 /* Fix: check for redundant REX prefixes */
967 return data - origdata;
970 /* Condition names for disassembly, sorted by x86 code */
971 static const char * const condition_name[16] = {
972 "o", "no", "c", "nc", "z", "nz", "na", "a",
973 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
976 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
977 int32_t offset, int autosync, uint32_t prefer)
979 const struct itemplate * const *p, * const *best_p;
980 const struct disasm_index *ix;
982 int length, best_length = 0;
984 int i, slen, colon, n;
988 uint32_t goodness, best;
990 struct prefix_info prefix;
993 memset(&ins, 0, sizeof ins);
998 memset(&prefix, 0, sizeof prefix);
999 prefix.asize = segsize;
1000 prefix.osize = (segsize == 64) ? 32 : segsize;
1007 while (!end_prefix) {
1011 prefix.rep = *data++;
1015 prefix.wait = *data++;
1019 prefix.lock = *data++;
1023 segover = "cs", prefix.seg = *data++;
1026 segover = "ss", prefix.seg = *data++;
1029 segover = "ds", prefix.seg = *data++;
1032 segover = "es", prefix.seg = *data++;
1035 segover = "fs", prefix.seg = *data++;
1038 segover = "gs", prefix.seg = *data++;
1042 prefix.osize = (segsize == 16) ? 32 : 16;
1043 prefix.osp = *data++;
1046 prefix.asize = (segsize == 32) ? 16 : 32;
1047 prefix.asp = *data++;
1052 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1053 prefix.vex[0] = *data++;
1054 prefix.vex[1] = *data++;
1057 prefix.vex_c = RV_VEX;
1059 if (prefix.vex[0] == 0xc4) {
1060 prefix.vex[2] = *data++;
1061 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1062 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1063 prefix.vex_m = prefix.vex[1] & 0x1f;
1064 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1065 prefix.vex_lp = prefix.vex[2] & 7;
1067 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1069 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1070 prefix.vex_lp = prefix.vex[1] & 7;
1073 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp];
1079 if ((data[1] & 030) != 0 &&
1080 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1081 prefix.vex[0] = *data++;
1082 prefix.vex[1] = *data++;
1083 prefix.vex[2] = *data++;
1086 prefix.vex_c = RV_XOP;
1088 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1089 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1090 prefix.vex_m = prefix.vex[1] & 0x1f;
1091 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1092 prefix.vex_lp = prefix.vex[2] & 7;
1094 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
1115 if (segsize == 64) {
1116 prefix.rex = *data++;
1117 if (prefix.rex & REX_W)
1129 best = -1; /* Worst possible */
1131 best_pref = INT_MAX;
1134 return 0; /* No instruction table at all... */
1138 while (ix->n == -1) {
1139 ix = (const struct disasm_index *)ix->p + *dp++;
1142 p = (const struct itemplate * const *)ix->p;
1143 for (n = ix->n; n; n--, p++) {
1144 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1147 * Final check to make sure the types of r/m match up.
1148 * XXX: Need to make sure this is actually correct.
1150 for (i = 0; i < (*p)->operands; i++) {
1151 if (!((*p)->opd[i] & SAME_AS) &&
1153 /* If it's a mem-only EA but we have a
1155 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1156 !(MEMORY & ~(*p)->opd[i])) ||
1157 /* If it's a reg-only EA but we have a memory
1159 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1160 !(REG_EA & ~(*p)->opd[i]) &&
1161 !((*p)->opd[i] & REG_SMASK)) ||
1162 /* Register type mismatch (eg FS vs REG_DESS):
1164 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1165 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1166 !whichreg((*p)->opd[i],
1167 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1175 * Note: we always prefer instructions which incorporate
1176 * prefixes in the instructions themselves. This is to allow
1177 * e.g. PAUSE to be preferred to REP NOP, and deal with
1178 * MMX/SSE instructions where prefixes are used to select
1179 * between MMX and SSE register sets or outright opcode
1184 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1186 for (i = 0; i < MAXPREFIX; i++)
1187 if (tmp_ins.prefixes[i])
1189 if (nprefix < best_pref ||
1190 (nprefix == best_pref && goodness < best)) {
1191 /* This is the best one found so far */
1194 best_pref = nprefix;
1195 best_length = length;
1203 return 0; /* no instruction was matched */
1205 /* Pick the best match */
1207 length = best_length;
1211 /* TODO: snprintf returns the value that the string would have if
1212 * the buffer were long enough, and not the actual length of
1213 * the returned string, so each instance of using the return
1214 * value of snprintf should actually be checked to assure that
1215 * the return value is "sane." Maybe a macro wrapper could
1216 * be used for that purpose.
1218 for (i = 0; i < MAXPREFIX; i++) {
1219 const char *prefix = prefix_name(ins.prefixes[i]);
1221 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1225 if (i >= FIRST_COND_OPCODE)
1226 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1227 nasm_insn_names[i], condition_name[ins.condition]);
1229 slen += snprintf(output + slen, outbufsize - slen, "%s",
1230 nasm_insn_names[i]);
1233 length += data - origdata; /* fix up for prefixes */
1234 for (i = 0; i < (*p)->operands; i++) {
1235 opflags_t t = (*p)->opd[i];
1236 const operand *o = &ins.oprs[i];
1240 o = &ins.oprs[t & ~SAME_AS];
1241 t = (*p)->opd[t & ~SAME_AS];
1244 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1247 if (o->segment & SEG_RELATIVE) {
1248 offs += offset + length;
1250 * sort out wraparound
1252 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1254 else if (segsize != 64)
1258 * add sync marker, if autosync is on
1269 if ((t & (REGISTER | FPUREG)) ||
1270 (o->segment & SEG_RMREG)) {
1272 reg = whichreg(t, o->basereg, ins.rex);
1274 slen += snprintf(output + slen, outbufsize - slen, "to ");
1275 slen += snprintf(output + slen, outbufsize - slen, "%s",
1276 nasm_reg_names[reg-EXPR_REG_START]);
1277 } else if (!(UNITY & ~t)) {
1278 output[slen++] = '1';
1279 } else if (t & IMMEDIATE) {
1282 snprintf(output + slen, outbufsize - slen, "byte ");
1283 if (o->segment & SEG_SIGNED) {
1286 output[slen++] = '-';
1288 output[slen++] = '+';
1290 } else if (t & BITS16) {
1292 snprintf(output + slen, outbufsize - slen, "word ");
1293 } else if (t & BITS32) {
1295 snprintf(output + slen, outbufsize - slen, "dword ");
1296 } else if (t & BITS64) {
1298 snprintf(output + slen, outbufsize - slen, "qword ");
1299 } else if (t & NEAR) {
1301 snprintf(output + slen, outbufsize - slen, "near ");
1302 } else if (t & SHORT) {
1304 snprintf(output + slen, outbufsize - slen, "short ");
1307 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1309 } else if (!(MEM_OFFS & ~t)) {
1311 snprintf(output + slen, outbufsize - slen,
1312 "[%s%s%s0x%"PRIx64"]",
1313 (segover ? segover : ""),
1314 (segover ? ":" : ""),
1315 (o->disp_size == 64 ? "qword " :
1316 o->disp_size == 32 ? "dword " :
1317 o->disp_size == 16 ? "word " : ""), offs);
1319 } else if (!(REGMEM & ~t)) {
1320 int started = false;
1323 snprintf(output + slen, outbufsize - slen, "byte ");
1326 snprintf(output + slen, outbufsize - slen, "word ");
1329 snprintf(output + slen, outbufsize - slen, "dword ");
1332 snprintf(output + slen, outbufsize - slen, "qword ");
1335 snprintf(output + slen, outbufsize - slen, "tword ");
1338 snprintf(output + slen, outbufsize - slen, "oword ");
1341 snprintf(output + slen, outbufsize - slen, "yword ");
1343 slen += snprintf(output + slen, outbufsize - slen, "far ");
1346 snprintf(output + slen, outbufsize - slen, "near ");
1347 output[slen++] = '[';
1349 slen += snprintf(output + slen, outbufsize - slen, "%s",
1350 (o->disp_size == 64 ? "qword " :
1351 o->disp_size == 32 ? "dword " :
1352 o->disp_size == 16 ? "word " :
1354 if (o->eaflags & EAF_REL)
1355 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1358 snprintf(output + slen, outbufsize - slen, "%s:",
1362 if (o->basereg != -1) {
1363 slen += snprintf(output + slen, outbufsize - slen, "%s",
1364 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1367 if (o->indexreg != -1) {
1369 output[slen++] = '+';
1370 slen += snprintf(output + slen, outbufsize - slen, "%s",
1371 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1374 snprintf(output + slen, outbufsize - slen, "*%d",
1380 if (o->segment & SEG_DISP8) {
1382 uint8_t offset = offs;
1383 if ((int8_t)offset < 0) {
1390 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1392 } else if (o->segment & SEG_DISP16) {
1394 uint16_t offset = offs;
1395 if ((int16_t)offset < 0 && started) {
1399 prefix = started ? "+" : "";
1402 snprintf(output + slen, outbufsize - slen,
1403 "%s0x%"PRIx16"", prefix, offset);
1404 } else if (o->segment & SEG_DISP32) {
1405 if (prefix.asize == 64) {
1407 uint64_t offset = (int64_t)(int32_t)offs;
1408 if ((int32_t)offs < 0 && started) {
1412 prefix = started ? "+" : "";
1415 snprintf(output + slen, outbufsize - slen,
1416 "%s0x%"PRIx64"", prefix, offset);
1419 uint32_t offset = offs;
1420 if ((int32_t) offset < 0 && started) {
1424 prefix = started ? "+" : "";
1427 snprintf(output + slen, outbufsize - slen,
1428 "%s0x%"PRIx32"", prefix, offset);
1431 output[slen++] = ']';
1434 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1438 output[slen] = '\0';
1439 if (segover) { /* unused segment override */
1441 int count = slen + 1;
1443 p[count + 3] = p[count];
1444 strncpy(output, segover, 2);
1451 * This is called when we don't have a complete instruction. If it
1452 * is a standalone *single-byte* prefix show it as such, otherwise
1453 * print it as a literal.
1455 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1457 uint8_t byte = *data;
1458 const char *str = NULL;
1492 str = (segsize == 16) ? "o32" : "o16";
1495 str = (segsize == 32) ? "a16" : "a32";
1513 if (segsize == 64) {
1514 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1515 (byte == REX_P) ? "" : ".",
1516 (byte & REX_W) ? "w" : "",
1517 (byte & REX_R) ? "r" : "",
1518 (byte & REX_X) ? "x" : "",
1519 (byte & REX_B) ? "b" : "");
1522 /* else fall through */
1524 snprintf(output, outbufsize, "db 0x%02x", byte);
1529 strcpy(output, str);