1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
57 #define getu8(x) (*(uint8_t *)(x))
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
64 static uint16_t getu16(uint8_t *data)
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
68 static uint32_t getu32(uint8_t *data)
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
72 static uint64_t getu64(uint8_t *data)
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
91 if (!(REG_AL & ~regflags))
93 if (!(REG_AX & ~regflags))
95 if (!(REG_EAX & ~regflags))
97 if (!(REG_RAX & ~regflags))
99 if (!(REG_DL & ~regflags))
101 if (!(REG_DX & ~regflags))
103 if (!(REG_EDX & ~regflags))
105 if (!(REG_RDX & ~regflags))
107 if (!(REG_CL & ~regflags))
109 if (!(REG_CX & ~regflags))
111 if (!(REG_ECX & ~regflags))
113 if (!(REG_RCX & ~regflags))
115 if (!(FPU0 & ~regflags))
117 if (!(XMM0 & ~regflags))
119 if (!(YMM0 & ~regflags))
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
135 if (!(REG8 & ~regflags)) {
137 return nasm_rd_reg8_rex[regval];
139 return nasm_rd_reg8[regval];
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
171 * Process a DREX suffix
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
189 * Process an effective address (ModRM) specification.
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
194 int mod, rm, scale, index, base;
198 mod = (modrm >> 6) & 03;
201 if (mod != 3 && rm == 4 && asize != 16)
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
259 if (rm == 6 && mod == 0) { /* special case */
263 mod = 2; /* fake disp16 */
267 op->segment |= SEG_NODISP;
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
292 int a64 = asize == 64;
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
301 if (rm == 5 && mod == 0) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
309 op->disp_size = asize;
312 mod = 2; /* fake disp32 */
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
320 op->scale = 1 << scale;
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
329 if (base == 5 && mod == 0) {
331 mod = 2; /* Fake disp32 */
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
343 op->segment |= SEG_NODISP;
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
380 int s_field_for = -1; /* No 144/154 series code encountered */
382 int regmask = (segsize == 64) ? 15 : 7;
384 for (i = 0; i < MAX_OPERANDS; i++) {
385 ins->oprs[i].segment = ins->oprs[i].disp_size =
386 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
389 ins->rex = prefix->rex;
390 memset(ins->prefixes, 0, sizeof ins->prefixes);
392 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
395 if (prefix->rep == 0xF2)
397 else if (prefix->rep == 0xF3)
400 while ((c = *r++) != 0) {
401 op1 = (c & 3) + ((opex & 1) << 2);
402 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
403 opx = &ins->oprs[op1];
424 int t = *r++, d = *data++;
425 if (d < t || d > t + 7)
428 opx->basereg = (d-t)+
429 (ins->rex & REX_B ? 8 : 0);
430 opx->segment |= SEG_RMREG;
437 opx->offset = (int8_t)*data++;
438 opx->segment |= SEG_SIGNED;
442 opx->offset = *data++;
446 opx->offset = *data++;
450 opx->offset = getu16(data);
456 opx->offset = getu32(data);
459 opx->offset = getu16(data);
462 if (segsize != asize)
463 opx->disp_size = asize;
468 opx->offset = getu32(data);
475 opx->offset = getu16(data);
481 opx->offset = getu32(data);
487 opx->offset = getu64(data);
495 opx->offset = gets8(data++);
496 opx->segment |= SEG_RELATIVE;
500 opx->offset = getu64(data);
505 opx->offset = gets16(data);
507 opx->segment |= SEG_RELATIVE;
508 opx->segment &= ~SEG_32BIT;
512 opx->segment |= SEG_RELATIVE;
514 opx->offset = gets16(data);
516 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
517 } else if (osize == 32) {
518 opx->offset = gets32(data);
520 opx->segment &= ~SEG_64BIT;
521 opx->segment |= SEG_32BIT;
523 if (segsize != osize) {
525 (opx->type & ~SIZE_MASK)
526 | ((osize == 16) ? BITS16 : BITS32);
531 opx->offset = gets32(data);
533 opx->segment |= SEG_32BIT | SEG_RELATIVE;
542 opx->segment |= SEG_RMREG;
543 data = do_ea(data, modrm, asize, segsize, &ins->oprs[op2], ins);
546 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
551 if (s_field_for == op1) {
552 opx->offset = gets8(data);
555 opx->offset = getu16(data);
562 s_field_for = (*data & 0x02) ? op1 : -1;
563 if ((*data++ & ~0x02) != *r++)
568 if (s_field_for == op1) {
569 opx->offset = gets8(data);
572 opx->offset = getu32(data);
583 ins->rex |= REX_D|REX_OC;
588 data = do_drex(data, ins);
595 uint8_t ximm = *data++;
597 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
598 ins->oprs[c >> 3].segment |= SEG_RMREG;
599 ins->oprs[c & 7].offset = ximm & 15;
605 uint8_t ximm = *data++;
611 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
612 ins->oprs[c >> 4].segment |= SEG_RMREG;
618 uint8_t ximm = *data++;
621 ins->oprs[c].basereg = (ximm >> 4) & regmask;
622 ins->oprs[c].segment |= SEG_RMREG;
636 if (((modrm >> 3) & 07) != (c & 07))
637 return false; /* spare field doesn't match up */
638 data = do_ea(data, modrm, asize, segsize, &ins->oprs[op2], ins);
649 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
652 if ((vexm & 0x1f) != prefix->vex_m)
655 switch (vexwlp & 030) {
657 if (prefix->rex & REX_W)
661 if (!(prefix->rex & REX_W))
665 case 020: /* VEX.W is a don't care */
672 if ((vexwlp & 007) != prefix->vex_lp)
675 opx->segment |= SEG_RMREG;
676 opx->basereg = prefix->vex_v;
686 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
689 if ((vexm & 0x1f) != prefix->vex_m)
692 switch (vexwlp & 030) {
694 if (ins->rex & REX_W)
698 if (!(ins->rex & REX_W))
702 break; /* Need to do anything special here? */
705 if ((vexwlp & 007) != prefix->vex_lp)
708 if (prefix->vex_v != 0)
730 if (asize != segsize)
744 if (prefix->rex & REX_B)
749 if (prefix->rex & REX_X)
754 if (prefix->rex & REX_R)
759 if (prefix->rex & REX_W)
778 if (osize != (segsize == 16) ? 16 : 32)
785 ins->rex |= REX_W; /* 64-bit only instruction */
791 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
798 int t = *r++, d = *data++;
799 if (d < t || d > t + 15)
802 ins->condition = d - t;
812 if (prefix->rep != 0xF2)
818 if (prefix->rep != 0xF3)
843 ins->oprs[0].basereg = (*data++ >> 3) & 7;
847 if (prefix->osp || prefix->rep)
852 if (!prefix->osp || prefix->rep)
858 if (prefix->osp || prefix->rep != 0xf2)
864 if (prefix->osp || prefix->rep != 0xf3)
892 return false; /* Unknown code */
896 if (!vex_ok && (ins->rex & REX_V))
899 /* REX cannot be combined with DREX or VEX */
900 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
904 * Check for unused rep or a/o prefixes.
906 for (i = 0; i < t->operands; i++) {
907 if (ins->oprs[i].segment != SEG_RMREG)
912 if (ins->prefixes[PPS_LREP])
914 ins->prefixes[PPS_LREP] = P_LOCK;
917 if (ins->prefixes[PPS_LREP])
919 ins->prefixes[PPS_LREP] = drep;
922 if (osize != ((segsize == 16) ? 16 : 32)) {
923 enum prefixes pfx = 0;
937 if (ins->prefixes[PPS_OSIZE])
939 ins->prefixes[PPS_OSIZE] = pfx;
942 if (!a_used && asize != segsize) {
943 if (ins->prefixes[PPS_ASIZE])
945 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
948 /* Fix: check for redundant REX prefixes */
950 return data - origdata;
953 /* Condition names for disassembly, sorted by x86 code */
954 static const char * const condition_name[16] = {
955 "o", "no", "c", "nc", "z", "nz", "na", "a",
956 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
959 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
960 int32_t offset, int autosync, uint32_t prefer)
962 const struct itemplate * const *p, * const *best_p;
963 const struct disasm_index *ix;
965 int length, best_length = 0;
967 int i, slen, colon, n;
971 uint32_t goodness, best;
973 struct prefix_info prefix;
976 memset(&ins, 0, sizeof ins);
981 memset(&prefix, 0, sizeof prefix);
982 prefix.asize = segsize;
983 prefix.osize = (segsize == 64) ? 32 : segsize;
990 while (!end_prefix) {
994 prefix.rep = *data++;
998 prefix.lock = *data++;
1002 segover = "cs", prefix.seg = *data++;
1005 segover = "ss", prefix.seg = *data++;
1008 segover = "ds", prefix.seg = *data++;
1011 segover = "es", prefix.seg = *data++;
1014 segover = "fs", prefix.seg = *data++;
1017 segover = "gs", prefix.seg = *data++;
1021 prefix.osize = (segsize == 16) ? 32 : 16;
1022 prefix.osp = *data++;
1025 prefix.asize = (segsize == 32) ? 16 : 32;
1026 prefix.asp = *data++;
1031 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1032 prefix.vex[0] = *data++;
1033 prefix.vex[1] = *data++;
1037 if (prefix.vex[0] == 0xc4) {
1038 prefix.vex[2] = *data++;
1039 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1040 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1041 prefix.vex_m = prefix.vex[1] & 0x1f;
1042 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1043 prefix.vex_lp = prefix.vex[2] & 7;
1045 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1047 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1048 prefix.vex_lp = prefix.vex[1] & 7;
1051 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1072 if (segsize == 64) {
1073 prefix.rex = *data++;
1074 if (prefix.rex & REX_W)
1086 best = -1; /* Worst possible */
1088 best_pref = INT_MAX;
1091 return 0; /* No instruction table at all... */
1095 while (ix->n == -1) {
1096 ix = (const struct disasm_index *)ix->p + *dp++;
1099 p = (const struct itemplate * const *)ix->p;
1100 for (n = ix->n; n; n--, p++) {
1101 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1104 * Final check to make sure the types of r/m match up.
1105 * XXX: Need to make sure this is actually correct.
1107 for (i = 0; i < (*p)->operands; i++) {
1108 if (!((*p)->opd[i] & SAME_AS) &&
1110 /* If it's a mem-only EA but we have a
1112 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1113 !(MEMORY & ~(*p)->opd[i])) ||
1114 /* If it's a reg-only EA but we have a memory
1116 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1117 !(REG_EA & ~(*p)->opd[i]) &&
1118 !((*p)->opd[i] & REG_SMASK)) ||
1119 /* Register type mismatch (eg FS vs REG_DESS):
1121 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1122 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1123 !whichreg((*p)->opd[i],
1124 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1132 * Note: we always prefer instructions which incorporate
1133 * prefixes in the instructions themselves. This is to allow
1134 * e.g. PAUSE to be preferred to REP NOP, and deal with
1135 * MMX/SSE instructions where prefixes are used to select
1136 * between MMX and SSE register sets or outright opcode
1141 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1143 for (i = 0; i < MAXPREFIX; i++)
1144 if (tmp_ins.prefixes[i])
1146 if (nprefix < best_pref ||
1147 (nprefix == best_pref && goodness < best)) {
1148 /* This is the best one found so far */
1151 best_pref = nprefix;
1152 best_length = length;
1160 return 0; /* no instruction was matched */
1162 /* Pick the best match */
1164 length = best_length;
1168 /* TODO: snprintf returns the value that the string would have if
1169 * the buffer were long enough, and not the actual length of
1170 * the returned string, so each instance of using the return
1171 * value of snprintf should actually be checked to assure that
1172 * the return value is "sane." Maybe a macro wrapper could
1173 * be used for that purpose.
1175 for (i = 0; i < MAXPREFIX; i++)
1176 switch (ins.prefixes[i]) {
1178 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1181 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1184 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1187 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1190 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1193 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1196 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1199 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1202 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1205 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1212 if (i >= FIRST_COND_OPCODE)
1213 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1214 nasm_insn_names[i], condition_name[ins.condition]);
1216 slen += snprintf(output + slen, outbufsize - slen, "%s",
1217 nasm_insn_names[i]);
1220 length += data - origdata; /* fix up for prefixes */
1221 for (i = 0; i < (*p)->operands; i++) {
1222 opflags_t t = (*p)->opd[i];
1223 const operand *o = &ins.oprs[i];
1227 o = &ins.oprs[t & ~SAME_AS];
1228 t = (*p)->opd[t & ~SAME_AS];
1231 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1234 if (o->segment & SEG_RELATIVE) {
1235 offs += offset + length;
1237 * sort out wraparound
1239 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1241 else if (segsize != 64)
1245 * add sync marker, if autosync is on
1256 if ((t & (REGISTER | FPUREG)) ||
1257 (o->segment & SEG_RMREG)) {
1259 reg = whichreg(t, o->basereg, ins.rex);
1261 slen += snprintf(output + slen, outbufsize - slen, "to ");
1262 slen += snprintf(output + slen, outbufsize - slen, "%s",
1263 nasm_reg_names[reg-EXPR_REG_START]);
1264 } else if (!(UNITY & ~t)) {
1265 output[slen++] = '1';
1266 } else if (t & IMMEDIATE) {
1269 snprintf(output + slen, outbufsize - slen, "byte ");
1270 if (o->segment & SEG_SIGNED) {
1273 output[slen++] = '-';
1275 output[slen++] = '+';
1277 } else if (t & BITS16) {
1279 snprintf(output + slen, outbufsize - slen, "word ");
1280 } else if (t & BITS32) {
1282 snprintf(output + slen, outbufsize - slen, "dword ");
1283 } else if (t & BITS64) {
1285 snprintf(output + slen, outbufsize - slen, "qword ");
1286 } else if (t & NEAR) {
1288 snprintf(output + slen, outbufsize - slen, "near ");
1289 } else if (t & SHORT) {
1291 snprintf(output + slen, outbufsize - slen, "short ");
1294 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1296 } else if (!(MEM_OFFS & ~t)) {
1298 snprintf(output + slen, outbufsize - slen,
1299 "[%s%s%s0x%"PRIx64"]",
1300 (segover ? segover : ""),
1301 (segover ? ":" : ""),
1302 (o->disp_size == 64 ? "qword " :
1303 o->disp_size == 32 ? "dword " :
1304 o->disp_size == 16 ? "word " : ""), offs);
1306 } else if (!(REGMEM & ~t)) {
1307 int started = false;
1310 snprintf(output + slen, outbufsize - slen, "byte ");
1313 snprintf(output + slen, outbufsize - slen, "word ");
1316 snprintf(output + slen, outbufsize - slen, "dword ");
1319 snprintf(output + slen, outbufsize - slen, "qword ");
1322 snprintf(output + slen, outbufsize - slen, "tword ");
1325 snprintf(output + slen, outbufsize - slen, "oword ");
1328 snprintf(output + slen, outbufsize - slen, "yword ");
1330 slen += snprintf(output + slen, outbufsize - slen, "far ");
1333 snprintf(output + slen, outbufsize - slen, "near ");
1334 output[slen++] = '[';
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 (o->disp_size == 64 ? "qword " :
1338 o->disp_size == 32 ? "dword " :
1339 o->disp_size == 16 ? "word " :
1341 if (o->eaflags & EAF_REL)
1342 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1345 snprintf(output + slen, outbufsize - slen, "%s:",
1349 if (o->basereg != -1) {
1350 slen += snprintf(output + slen, outbufsize - slen, "%s",
1351 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1354 if (o->indexreg != -1) {
1356 output[slen++] = '+';
1357 slen += snprintf(output + slen, outbufsize - slen, "%s",
1358 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1361 snprintf(output + slen, outbufsize - slen, "*%d",
1367 if (o->segment & SEG_DISP8) {
1369 uint8_t offset = offs;
1370 if ((int8_t)offset < 0) {
1377 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1379 } else if (o->segment & SEG_DISP16) {
1381 uint16_t offset = offs;
1382 if ((int16_t)offset < 0 && started) {
1386 prefix = started ? "+" : "";
1389 snprintf(output + slen, outbufsize - slen,
1390 "%s0x%"PRIx16"", prefix, offset);
1391 } else if (o->segment & SEG_DISP32) {
1392 if (prefix.asize == 64) {
1394 uint64_t offset = (int64_t)(int32_t)offs;
1395 if ((int32_t)offs < 0 && started) {
1399 prefix = started ? "+" : "";
1402 snprintf(output + slen, outbufsize - slen,
1403 "%s0x%"PRIx64"", prefix, offset);
1406 uint32_t offset = offs;
1407 if ((int32_t) offset < 0 && started) {
1411 prefix = started ? "+" : "";
1414 snprintf(output + slen, outbufsize - slen,
1415 "%s0x%"PRIx32"", prefix, offset);
1418 output[slen++] = ']';
1421 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1425 output[slen] = '\0';
1426 if (segover) { /* unused segment override */
1428 int count = slen + 1;
1430 p[count + 3] = p[count];
1431 strncpy(output, segover, 2);
1437 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1439 snprintf(output, outbufsize, "db 0x%02X", *data);