1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
53 * Flags that go into the `segment' field of `insn' structures
56 #define SEG_RELATIVE 1
63 #define SEG_SIGNED 128
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
86 #define getu8(x) (*(uint8_t *)(x))
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
93 static uint16_t getu16(uint8_t *data)
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 static uint32_t getu32(uint8_t *data)
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 static uint64_t getu64(uint8_t *data)
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
118 regflags |= REGISTER;
120 if (!(REG_AL & ~regflags))
122 if (!(REG_AX & ~regflags))
124 if (!(REG_EAX & ~regflags))
126 if (!(REG_RAX & ~regflags))
128 if (!(REG_DL & ~regflags))
130 if (!(REG_DX & ~regflags))
132 if (!(REG_EDX & ~regflags))
134 if (!(REG_RDX & ~regflags))
136 if (!(REG_CL & ~regflags))
138 if (!(REG_CX & ~regflags))
140 if (!(REG_ECX & ~regflags))
142 if (!(REG_RCX & ~regflags))
144 if (!(FPU0 & ~regflags))
146 if (!(XMM0 & ~regflags))
148 if (!(YMM0 & ~regflags))
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
168 return nasm_rd_reg8[regval];
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
200 * Process an effective address (ModRM) specification.
202 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
203 int segsize, enum ea_type type,
204 operand *op, insn *ins)
206 int mod, rm, scale, index, base;
210 mod = (modrm >> 6) & 03;
213 if (mod != 3 && asize != 16 && rm == 4)
218 if (mod == 3) { /* pure register version */
219 op->basereg = rm+(rex & REX_B ? 8 : 0);
220 op->segment |= SEG_RMREG;
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
235 if (type != EA_SCALAR)
238 op->indexreg = op->basereg = -1;
239 op->scale = 1; /* always, in 16 bits */
270 if (rm == 6 && mod == 0) { /* special case */
274 mod = 2; /* fake disp16 */
278 op->segment |= SEG_NODISP;
281 op->segment |= SEG_DISP8;
282 op->offset = (int8_t)*data++;
285 op->segment |= SEG_DISP16;
286 op->offset = *data++;
287 op->offset |= ((unsigned)*data++) << 8;
293 * Once again, <mod> specifies displacement size (this time
294 * none, byte or *dword*), while <rm> specifies the base
295 * register. Again, [EBP] is missing, replaced by a pure
296 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
297 * and RIP-relative addressing in 64-bit mode.
300 * indicates not a single base register, but instead the
301 * presence of a SIB byte...
303 int a64 = asize == 64;
308 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
310 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
312 if (rm == 5 && mod == 0) {
314 op->eaflags |= EAF_REL;
315 op->segment |= SEG_RELATIVE;
316 mod = 2; /* fake disp32 */
320 op->disp_size = asize;
323 mod = 2; /* fake disp32 */
327 if (rm == 4) { /* process SIB */
328 scale = (sib >> 6) & 03;
329 index = (sib >> 3) & 07;
332 op->scale = 1 << scale;
334 if (type == EA_XMMVSIB)
335 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
336 else if (type == EA_YMMVSIB)
337 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
338 else if (index == 4 && !(rex & REX_X))
339 op->indexreg = -1; /* ESP/RSP cannot be an index */
341 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
343 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
345 if (base == 5 && mod == 0) {
347 mod = 2; /* Fake disp32 */
349 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
351 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
355 } else if (type != EA_SCALAR) {
356 /* Can't have VSIB without SIB */
362 op->segment |= SEG_NODISP;
365 op->segment |= SEG_DISP8;
366 op->offset = gets8(data);
370 op->segment |= SEG_DISP32;
371 op->offset = gets32(data);
380 * Determine whether the instruction template in t corresponds to the data
381 * stream in data. Return the number of bytes matched if so.
383 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
385 static int matches(const struct itemplate *t, uint8_t *data,
386 const struct prefix_info *prefix, int segsize, insn *ins)
388 uint8_t *r = (uint8_t *)(t->code);
389 uint8_t *origdata = data;
390 bool a_used = false, o_used = false;
391 enum prefixes drep = 0;
392 enum prefixes dwait = 0;
393 uint8_t lock = prefix->lock;
394 int osize = prefix->osize;
395 int asize = prefix->asize;
398 struct operand *opx, *opy;
400 int s_field_for = -1; /* No 144/154 series code encountered */
402 int regmask = (segsize == 64) ? 15 : 7;
403 enum ea_type eat = EA_SCALAR;
405 for (i = 0; i < MAX_OPERANDS; i++) {
406 ins->oprs[i].segment = ins->oprs[i].disp_size =
407 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
410 ins->rex = prefix->rex;
411 memset(ins->prefixes, 0, sizeof ins->prefixes);
413 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
416 if (prefix->rep == 0xF2)
418 else if (prefix->rep == 0xF3)
421 dwait = prefix->wait ? P_WAIT : 0;
423 while ((c = *r++) != 0) {
424 op1 = (c & 3) + ((opex & 1) << 2);
425 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
426 opx = &ins->oprs[op1];
427 opy = &ins->oprs[op2];
448 int t = *r++, d = *data++;
449 if (d < t || d > t + 7)
452 opx->basereg = (d-t)+
453 (ins->rex & REX_B ? 8 : 0);
454 opx->segment |= SEG_RMREG;
461 opx->offset = (int8_t)*data++;
462 opx->segment |= SEG_SIGNED;
466 opx->offset = *data++;
470 opx->offset = *data++;
474 opx->offset = getu16(data);
480 opx->offset = getu32(data);
483 opx->offset = getu16(data);
486 if (segsize != asize)
487 opx->disp_size = asize;
492 opx->offset = getu32(data);
499 opx->offset = getu16(data);
505 opx->offset = getu32(data);
511 opx->offset = getu64(data);
519 opx->offset = gets8(data++);
520 opx->segment |= SEG_RELATIVE;
524 opx->offset = getu64(data);
529 opx->offset = gets16(data);
531 opx->segment |= SEG_RELATIVE;
532 opx->segment &= ~SEG_32BIT;
536 opx->segment |= SEG_RELATIVE;
538 opx->offset = gets16(data);
540 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
541 } else if (osize == 32) {
542 opx->offset = gets32(data);
544 opx->segment &= ~SEG_64BIT;
545 opx->segment |= SEG_32BIT;
547 if (segsize != osize) {
549 (opx->type & ~SIZE_MASK)
550 | ((osize == 16) ? BITS16 : BITS32);
555 opx->offset = gets32(data);
557 opx->segment |= SEG_32BIT | SEG_RELATIVE;
566 opx->segment |= SEG_RMREG;
567 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
570 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
575 if (s_field_for == op1) {
576 opx->offset = gets8(data);
579 opx->offset = getu16(data);
586 s_field_for = (*data & 0x02) ? op1 : -1;
587 if ((*data++ & ~0x02) != *r++)
592 if (s_field_for == op1) {
593 opx->offset = gets8(data);
596 opx->offset = getu32(data);
603 uint8_t ximm = *data++;
605 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
606 ins->oprs[c >> 3].segment |= SEG_RMREG;
607 ins->oprs[c & 7].offset = ximm & 15;
613 uint8_t ximm = *data++;
619 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
620 ins->oprs[c >> 4].segment |= SEG_RMREG;
626 uint8_t ximm = *data++;
628 opx->basereg = (ximm >> 4) & regmask;
629 opx->segment |= SEG_RMREG;
643 if (((modrm >> 3) & 07) != (c & 07))
644 return false; /* spare field doesn't match up */
645 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
652 if (s_field_for == op1) {
653 opx->offset = gets8(data);
656 opx->offset = gets32(data);
668 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
671 if ((vexm & 0x1f) != prefix->vex_m)
674 switch (vexwlp & 060) {
676 if (prefix->rex & REX_W)
680 if (!(prefix->rex & REX_W))
684 case 040: /* VEX.W is a don't care */
691 /* The 010 bit of vexwlp is set if VEX.L is ignored */
692 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
696 if (prefix->vex_v != 0)
699 opx->segment |= SEG_RMREG;
700 opx->basereg = prefix->vex_v;
710 if (prefix->rep == 0xF3)
715 if (prefix->rep == 0xF2)
717 else if (prefix->rep == 0xF3)
722 if (prefix->lock == 0xF0) {
723 if (prefix->rep == 0xF2)
725 else if (prefix->rep == 0xF3)
745 if (asize != segsize)
759 if (prefix->rex & REX_B)
764 if (prefix->rex & REX_X)
769 if (prefix->rex & REX_R)
774 if (prefix->rex & REX_W)
793 if (osize != (segsize == 16) ? 16 : 32)
800 ins->rex |= REX_W; /* 64-bit only instruction */
817 int t = *r++, d = *data++;
818 if (d < t || d > t + 15)
821 ins->condition = d - t;
831 if (prefix->rep != 0xF2)
837 if (prefix->rep != 0xF3)
862 if (prefix->wait != 0x9B)
868 ins->oprs[0].basereg = (*data++ >> 3) & 7;
872 if (prefix->osp || prefix->rep)
877 if (!prefix->osp || prefix->rep)
883 if (prefix->osp || prefix->rep != 0xf2)
889 if (prefix->osp || prefix->rep != 0xf3)
925 return false; /* Unknown code */
929 if (!vex_ok && (ins->rex & REX_V))
932 /* REX cannot be combined with VEX */
933 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
937 * Check for unused rep or a/o prefixes.
939 for (i = 0; i < t->operands; i++) {
940 if (ins->oprs[i].segment != SEG_RMREG)
945 if (ins->prefixes[PPS_LOCK])
947 ins->prefixes[PPS_LOCK] = P_LOCK;
950 if (ins->prefixes[PPS_REP])
952 ins->prefixes[PPS_REP] = drep;
954 ins->prefixes[PPS_WAIT] = dwait;
956 if (osize != ((segsize == 16) ? 16 : 32)) {
957 enum prefixes pfx = 0;
971 if (ins->prefixes[PPS_OSIZE])
973 ins->prefixes[PPS_OSIZE] = pfx;
976 if (!a_used && asize != segsize) {
977 if (ins->prefixes[PPS_ASIZE])
979 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
982 /* Fix: check for redundant REX prefixes */
984 return data - origdata;
987 /* Condition names for disassembly, sorted by x86 code */
988 static const char * const condition_name[16] = {
989 "o", "no", "c", "nc", "z", "nz", "na", "a",
990 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
993 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
994 int32_t offset, int autosync, uint32_t prefer)
996 const struct itemplate * const *p, * const *best_p;
997 const struct disasm_index *ix;
999 int length, best_length = 0;
1001 int i, slen, colon, n;
1005 uint32_t goodness, best;
1007 struct prefix_info prefix;
1010 memset(&ins, 0, sizeof ins);
1013 * Scan for prefixes.
1015 memset(&prefix, 0, sizeof prefix);
1016 prefix.asize = segsize;
1017 prefix.osize = (segsize == 64) ? 32 : segsize;
1024 while (!end_prefix) {
1028 prefix.rep = *data++;
1032 prefix.wait = *data++;
1036 prefix.lock = *data++;
1040 segover = "cs", prefix.seg = *data++;
1043 segover = "ss", prefix.seg = *data++;
1046 segover = "ds", prefix.seg = *data++;
1049 segover = "es", prefix.seg = *data++;
1052 segover = "fs", prefix.seg = *data++;
1055 segover = "gs", prefix.seg = *data++;
1059 prefix.osize = (segsize == 16) ? 32 : 16;
1060 prefix.osp = *data++;
1063 prefix.asize = (segsize == 32) ? 16 : 32;
1064 prefix.asp = *data++;
1069 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1070 prefix.vex[0] = *data++;
1071 prefix.vex[1] = *data++;
1074 prefix.vex_c = RV_VEX;
1076 if (prefix.vex[0] == 0xc4) {
1077 prefix.vex[2] = *data++;
1078 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1079 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1080 prefix.vex_m = prefix.vex[1] & 0x1f;
1081 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1082 prefix.vex_lp = prefix.vex[2] & 7;
1084 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1086 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1087 prefix.vex_lp = prefix.vex[1] & 7;
1090 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1096 if ((data[1] & 030) != 0 &&
1097 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1098 prefix.vex[0] = *data++;
1099 prefix.vex[1] = *data++;
1100 prefix.vex[2] = *data++;
1103 prefix.vex_c = RV_XOP;
1105 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1106 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1107 prefix.vex_m = prefix.vex[1] & 0x1f;
1108 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1109 prefix.vex_lp = prefix.vex[2] & 7;
1111 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1132 if (segsize == 64) {
1133 prefix.rex = *data++;
1134 if (prefix.rex & REX_W)
1146 best = -1; /* Worst possible */
1148 best_pref = INT_MAX;
1151 return 0; /* No instruction table at all... */
1155 while (ix->n == -1) {
1156 ix = (const struct disasm_index *)ix->p + *dp++;
1159 p = (const struct itemplate * const *)ix->p;
1160 for (n = ix->n; n; n--, p++) {
1161 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1164 * Final check to make sure the types of r/m match up.
1165 * XXX: Need to make sure this is actually correct.
1167 for (i = 0; i < (*p)->operands; i++) {
1168 if (!((*p)->opd[i] & SAME_AS) &&
1170 /* If it's a mem-only EA but we have a
1172 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1173 is_class(MEMORY, (*p)->opd[i])) ||
1174 /* If it's a reg-only EA but we have a memory
1176 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1177 !(REG_EA & ~(*p)->opd[i]) &&
1178 !((*p)->opd[i] & REG_SMASK)) ||
1179 /* Register type mismatch (eg FS vs REG_DESS):
1181 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1182 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1183 !whichreg((*p)->opd[i],
1184 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1192 * Note: we always prefer instructions which incorporate
1193 * prefixes in the instructions themselves. This is to allow
1194 * e.g. PAUSE to be preferred to REP NOP, and deal with
1195 * MMX/SSE instructions where prefixes are used to select
1196 * between MMX and SSE register sets or outright opcode
1201 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1203 for (i = 0; i < MAXPREFIX; i++)
1204 if (tmp_ins.prefixes[i])
1206 if (nprefix < best_pref ||
1207 (nprefix == best_pref && goodness < best)) {
1208 /* This is the best one found so far */
1211 best_pref = nprefix;
1212 best_length = length;
1220 return 0; /* no instruction was matched */
1222 /* Pick the best match */
1224 length = best_length;
1228 /* TODO: snprintf returns the value that the string would have if
1229 * the buffer were long enough, and not the actual length of
1230 * the returned string, so each instance of using the return
1231 * value of snprintf should actually be checked to assure that
1232 * the return value is "sane." Maybe a macro wrapper could
1233 * be used for that purpose.
1235 for (i = 0; i < MAXPREFIX; i++) {
1236 const char *prefix = prefix_name(ins.prefixes[i]);
1238 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1242 if (i >= FIRST_COND_OPCODE)
1243 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1244 nasm_insn_names[i], condition_name[ins.condition]);
1246 slen += snprintf(output + slen, outbufsize - slen, "%s",
1247 nasm_insn_names[i]);
1250 length += data - origdata; /* fix up for prefixes */
1251 for (i = 0; i < (*p)->operands; i++) {
1252 opflags_t t = (*p)->opd[i];
1253 const operand *o = &ins.oprs[i];
1257 o = &ins.oprs[t & ~SAME_AS];
1258 t = (*p)->opd[t & ~SAME_AS];
1261 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1264 if (o->segment & SEG_RELATIVE) {
1265 offs += offset + length;
1267 * sort out wraparound
1269 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1271 else if (segsize != 64)
1275 * add sync marker, if autosync is on
1286 if ((t & (REGISTER | FPUREG)) ||
1287 (o->segment & SEG_RMREG)) {
1289 reg = whichreg(t, o->basereg, ins.rex);
1291 slen += snprintf(output + slen, outbufsize - slen, "to ");
1292 slen += snprintf(output + slen, outbufsize - slen, "%s",
1293 nasm_reg_names[reg-EXPR_REG_START]);
1294 } else if (!(UNITY & ~t)) {
1295 output[slen++] = '1';
1296 } else if (t & IMMEDIATE) {
1299 snprintf(output + slen, outbufsize - slen, "byte ");
1300 if (o->segment & SEG_SIGNED) {
1303 output[slen++] = '-';
1305 output[slen++] = '+';
1307 } else if (t & BITS16) {
1309 snprintf(output + slen, outbufsize - slen, "word ");
1310 } else if (t & BITS32) {
1312 snprintf(output + slen, outbufsize - slen, "dword ");
1313 } else if (t & BITS64) {
1315 snprintf(output + slen, outbufsize - slen, "qword ");
1316 } else if (t & NEAR) {
1318 snprintf(output + slen, outbufsize - slen, "near ");
1319 } else if (t & SHORT) {
1321 snprintf(output + slen, outbufsize - slen, "short ");
1324 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1326 } else if (!(MEM_OFFS & ~t)) {
1328 snprintf(output + slen, outbufsize - slen,
1329 "[%s%s%s0x%"PRIx64"]",
1330 (segover ? segover : ""),
1331 (segover ? ":" : ""),
1332 (o->disp_size == 64 ? "qword " :
1333 o->disp_size == 32 ? "dword " :
1334 o->disp_size == 16 ? "word " : ""), offs);
1336 } else if (is_class(REGMEM, t)) {
1337 int started = false;
1340 snprintf(output + slen, outbufsize - slen, "byte ");
1343 snprintf(output + slen, outbufsize - slen, "word ");
1346 snprintf(output + slen, outbufsize - slen, "dword ");
1349 snprintf(output + slen, outbufsize - slen, "qword ");
1352 snprintf(output + slen, outbufsize - slen, "tword ");
1355 snprintf(output + slen, outbufsize - slen, "oword ");
1358 snprintf(output + slen, outbufsize - slen, "yword ");
1360 slen += snprintf(output + slen, outbufsize - slen, "far ");
1363 snprintf(output + slen, outbufsize - slen, "near ");
1364 output[slen++] = '[';
1366 slen += snprintf(output + slen, outbufsize - slen, "%s",
1367 (o->disp_size == 64 ? "qword " :
1368 o->disp_size == 32 ? "dword " :
1369 o->disp_size == 16 ? "word " :
1371 if (o->eaflags & EAF_REL)
1372 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1375 snprintf(output + slen, outbufsize - slen, "%s:",
1379 if (o->basereg != -1) {
1380 slen += snprintf(output + slen, outbufsize - slen, "%s",
1381 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1384 if (o->indexreg != -1) {
1386 output[slen++] = '+';
1387 slen += snprintf(output + slen, outbufsize - slen, "%s",
1388 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1391 snprintf(output + slen, outbufsize - slen, "*%d",
1397 if (o->segment & SEG_DISP8) {
1399 uint8_t offset = offs;
1400 if ((int8_t)offset < 0) {
1407 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1409 } else if (o->segment & SEG_DISP16) {
1411 uint16_t offset = offs;
1412 if ((int16_t)offset < 0 && started) {
1416 prefix = started ? "+" : "";
1419 snprintf(output + slen, outbufsize - slen,
1420 "%s0x%"PRIx16"", prefix, offset);
1421 } else if (o->segment & SEG_DISP32) {
1422 if (prefix.asize == 64) {
1424 uint64_t offset = (int64_t)(int32_t)offs;
1425 if ((int32_t)offs < 0 && started) {
1429 prefix = started ? "+" : "";
1432 snprintf(output + slen, outbufsize - slen,
1433 "%s0x%"PRIx64"", prefix, offset);
1436 uint32_t offset = offs;
1437 if ((int32_t) offset < 0 && started) {
1441 prefix = started ? "+" : "";
1444 snprintf(output + slen, outbufsize - slen,
1445 "%s0x%"PRIx32"", prefix, offset);
1448 output[slen++] = ']';
1451 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1455 output[slen] = '\0';
1456 if (segover) { /* unused segment override */
1458 int count = slen + 1;
1460 p[count + 3] = p[count];
1461 strncpy(output, segover, 2);
1468 * This is called when we don't have a complete instruction. If it
1469 * is a standalone *single-byte* prefix show it as such, otherwise
1470 * print it as a literal.
1472 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1474 uint8_t byte = *data;
1475 const char *str = NULL;
1509 str = (segsize == 16) ? "o32" : "o16";
1512 str = (segsize == 32) ? "a16" : "a32";
1530 if (segsize == 64) {
1531 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1532 (byte == REX_P) ? "" : ".",
1533 (byte & REX_W) ? "w" : "",
1534 (byte & REX_R) ? "r" : "",
1535 (byte & REX_X) ? "x" : "",
1536 (byte & REX_B) ? "b" : "");
1539 /* else fall through */
1541 snprintf(output, outbufsize, "db 0x%02x", byte);
1546 snprintf(output, outbufsize, "%s", str);