1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
53 * Flags that go into the `segment' field of `insn' structures
56 #define SEG_RELATIVE 1
63 #define SEG_SIGNED 128
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
86 #define getu8(x) (*(uint8_t *)(x))
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
93 static uint16_t getu16(uint8_t *data)
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 static uint32_t getu32(uint8_t *data)
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 static uint64_t getu64(uint8_t *data)
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
118 regflags |= REGISTER;
120 if (!(REG_AL & ~regflags))
122 if (!(REG_AX & ~regflags))
124 if (!(REG_EAX & ~regflags))
126 if (!(REG_RAX & ~regflags))
128 if (!(REG_DL & ~regflags))
130 if (!(REG_DX & ~regflags))
132 if (!(REG_EDX & ~regflags))
134 if (!(REG_RDX & ~regflags))
136 if (!(REG_CL & ~regflags))
138 if (!(REG_CX & ~regflags))
140 if (!(REG_ECX & ~regflags))
142 if (!(REG_RCX & ~regflags))
144 if (!(FPU0 & ~regflags))
146 if (!(XMM0 & ~regflags))
148 if (!(YMM0 & ~regflags))
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
168 return nasm_rd_reg8[regval];
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
200 * Process a DREX suffix
202 static uint8_t *do_drex(uint8_t *data, insn *ins)
204 uint8_t drex = *data++;
205 operand *dst = &ins->oprs[ins->drexdst];
207 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
208 return NULL; /* OC0 mismatch */
209 ins->rex = (ins->rex & ~7) | (drex & 7);
211 dst->segment = SEG_RMREG;
212 dst->basereg = drex >> 4;
218 * Process an effective address (ModRM) specification.
220 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
221 int segsize, enum ea_type type,
222 operand *op, insn *ins)
224 int mod, rm, scale, index, base;
228 mod = (modrm >> 6) & 03;
231 if (mod != 3 && asize != 16 && rm == 4)
234 if (ins->rex & REX_D) {
235 data = do_drex(data, ins);
241 if (mod == 3) { /* pure register version */
242 op->basereg = rm+(rex & REX_B ? 8 : 0);
243 op->segment |= SEG_RMREG;
252 * <mod> specifies the displacement size (none, byte or
253 * word), and <rm> specifies the register combination.
254 * Exception: mod=0,rm=6 does not specify [BP] as one might
255 * expect, but instead specifies [disp16].
258 if (type != EA_SCALAR)
261 op->indexreg = op->basereg = -1;
262 op->scale = 1; /* always, in 16 bits */
293 if (rm == 6 && mod == 0) { /* special case */
297 mod = 2; /* fake disp16 */
301 op->segment |= SEG_NODISP;
304 op->segment |= SEG_DISP8;
305 op->offset = (int8_t)*data++;
308 op->segment |= SEG_DISP16;
309 op->offset = *data++;
310 op->offset |= ((unsigned)*data++) << 8;
316 * Once again, <mod> specifies displacement size (this time
317 * none, byte or *dword*), while <rm> specifies the base
318 * register. Again, [EBP] is missing, replaced by a pure
319 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
320 * and RIP-relative addressing in 64-bit mode.
323 * indicates not a single base register, but instead the
324 * presence of a SIB byte...
326 int a64 = asize == 64;
331 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
333 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
335 if (rm == 5 && mod == 0) {
337 op->eaflags |= EAF_REL;
338 op->segment |= SEG_RELATIVE;
339 mod = 2; /* fake disp32 */
343 op->disp_size = asize;
346 mod = 2; /* fake disp32 */
350 if (rm == 4) { /* process SIB */
351 scale = (sib >> 6) & 03;
352 index = (sib >> 3) & 07;
355 op->scale = 1 << scale;
357 if (index == 4 && !(rex & REX_X))
358 op->indexreg = -1; /* ESP/RSP cannot be an index */
359 else if (type == EA_XMMVSIB)
360 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
361 else if (type == EA_YMMVSIB)
362 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
364 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
366 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
368 if (base == 5 && mod == 0) {
370 mod = 2; /* Fake disp32 */
372 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
374 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
378 } else if (type != EA_SCALAR) {
379 /* Can't have VSIB without SIB */
385 op->segment |= SEG_NODISP;
388 op->segment |= SEG_DISP8;
389 op->offset = gets8(data);
393 op->segment |= SEG_DISP32;
394 op->offset = gets32(data);
403 * Determine whether the instruction template in t corresponds to the data
404 * stream in data. Return the number of bytes matched if so.
406 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
408 static int matches(const struct itemplate *t, uint8_t *data,
409 const struct prefix_info *prefix, int segsize, insn *ins)
411 uint8_t *r = (uint8_t *)(t->code);
412 uint8_t *origdata = data;
413 bool a_used = false, o_used = false;
414 enum prefixes drep = 0;
415 enum prefixes dwait = 0;
416 uint8_t lock = prefix->lock;
417 int osize = prefix->osize;
418 int asize = prefix->asize;
421 struct operand *opx, *opy;
423 int s_field_for = -1; /* No 144/154 series code encountered */
425 int regmask = (segsize == 64) ? 15 : 7;
426 enum ea_type eat = EA_SCALAR;
428 for (i = 0; i < MAX_OPERANDS; i++) {
429 ins->oprs[i].segment = ins->oprs[i].disp_size =
430 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
433 ins->rex = prefix->rex;
434 memset(ins->prefixes, 0, sizeof ins->prefixes);
436 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
439 if (prefix->rep == 0xF2)
441 else if (prefix->rep == 0xF3)
444 dwait = prefix->wait ? P_WAIT : 0;
446 while ((c = *r++) != 0) {
447 op1 = (c & 3) + ((opex & 1) << 2);
448 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
449 opx = &ins->oprs[op1];
450 opy = &ins->oprs[op2];
471 int t = *r++, d = *data++;
472 if (d < t || d > t + 7)
475 opx->basereg = (d-t)+
476 (ins->rex & REX_B ? 8 : 0);
477 opx->segment |= SEG_RMREG;
484 opx->offset = (int8_t)*data++;
485 opx->segment |= SEG_SIGNED;
489 opx->offset = *data++;
493 opx->offset = *data++;
497 opx->offset = getu16(data);
503 opx->offset = getu32(data);
506 opx->offset = getu16(data);
509 if (segsize != asize)
510 opx->disp_size = asize;
515 opx->offset = getu32(data);
522 opx->offset = getu16(data);
528 opx->offset = getu32(data);
534 opx->offset = getu64(data);
542 opx->offset = gets8(data++);
543 opx->segment |= SEG_RELATIVE;
547 opx->offset = getu64(data);
552 opx->offset = gets16(data);
554 opx->segment |= SEG_RELATIVE;
555 opx->segment &= ~SEG_32BIT;
559 opx->segment |= SEG_RELATIVE;
561 opx->offset = gets16(data);
563 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
564 } else if (osize == 32) {
565 opx->offset = gets32(data);
567 opx->segment &= ~SEG_64BIT;
568 opx->segment |= SEG_32BIT;
570 if (segsize != osize) {
572 (opx->type & ~SIZE_MASK)
573 | ((osize == 16) ? BITS16 : BITS32);
578 opx->offset = gets32(data);
580 opx->segment |= SEG_32BIT | SEG_RELATIVE;
589 opx->segment |= SEG_RMREG;
590 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
593 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
598 if (s_field_for == op1) {
599 opx->offset = gets8(data);
602 opx->offset = getu16(data);
609 s_field_for = (*data & 0x02) ? op1 : -1;
610 if ((*data++ & ~0x02) != *r++)
615 if (s_field_for == op1) {
616 opx->offset = gets8(data);
619 opx->offset = getu32(data);
630 ins->rex |= REX_D|REX_OC;
635 data = do_drex(data, ins);
642 uint8_t ximm = *data++;
644 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
645 ins->oprs[c >> 3].segment |= SEG_RMREG;
646 ins->oprs[c & 7].offset = ximm & 15;
652 uint8_t ximm = *data++;
658 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
659 ins->oprs[c >> 4].segment |= SEG_RMREG;
665 uint8_t ximm = *data++;
668 ins->oprs[c].basereg = (ximm >> 4) & regmask;
669 ins->oprs[c].segment |= SEG_RMREG;
683 if (((modrm >> 3) & 07) != (c & 07))
684 return false; /* spare field doesn't match up */
685 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
692 if (s_field_for == op1) {
693 opx->offset = gets8(data);
696 opx->offset = gets32(data);
708 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
711 if ((vexm & 0x1f) != prefix->vex_m)
714 switch (vexwlp & 060) {
716 if (prefix->rex & REX_W)
720 if (!(prefix->rex & REX_W))
724 case 040: /* VEX.W is a don't care */
731 /* The 010 bit of vexwlp is set if VEX.L is ignored */
732 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
736 if (prefix->vex_v != 0)
739 opx->segment |= SEG_RMREG;
740 opx->basereg = prefix->vex_v;
761 if (asize != segsize)
775 if (prefix->rex & REX_B)
780 if (prefix->rex & REX_X)
785 if (prefix->rex & REX_R)
790 if (prefix->rex & REX_W)
809 if (osize != (segsize == 16) ? 16 : 32)
816 ins->rex |= REX_W; /* 64-bit only instruction */
833 int t = *r++, d = *data++;
834 if (d < t || d > t + 15)
837 ins->condition = d - t;
847 if (prefix->rep != 0xF2)
853 if (prefix->rep != 0xF3)
878 if (prefix->wait != 0x9B)
884 ins->oprs[0].basereg = (*data++ >> 3) & 7;
888 if (prefix->osp || prefix->rep)
893 if (!prefix->osp || prefix->rep)
899 if (prefix->osp || prefix->rep != 0xf2)
905 if (prefix->osp || prefix->rep != 0xf3)
941 return false; /* Unknown code */
945 if (!vex_ok && (ins->rex & REX_V))
948 /* REX cannot be combined with DREX or VEX */
949 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
953 * Check for unused rep or a/o prefixes.
955 for (i = 0; i < t->operands; i++) {
956 if (ins->oprs[i].segment != SEG_RMREG)
961 if (ins->prefixes[PPS_LREP])
963 ins->prefixes[PPS_LREP] = P_LOCK;
966 if (ins->prefixes[PPS_LREP])
968 ins->prefixes[PPS_LREP] = drep;
970 ins->prefixes[PPS_WAIT] = dwait;
972 if (osize != ((segsize == 16) ? 16 : 32)) {
973 enum prefixes pfx = 0;
987 if (ins->prefixes[PPS_OSIZE])
989 ins->prefixes[PPS_OSIZE] = pfx;
992 if (!a_used && asize != segsize) {
993 if (ins->prefixes[PPS_ASIZE])
995 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
998 /* Fix: check for redundant REX prefixes */
1000 return data - origdata;
1003 /* Condition names for disassembly, sorted by x86 code */
1004 static const char * const condition_name[16] = {
1005 "o", "no", "c", "nc", "z", "nz", "na", "a",
1006 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1009 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1010 int32_t offset, int autosync, uint32_t prefer)
1012 const struct itemplate * const *p, * const *best_p;
1013 const struct disasm_index *ix;
1015 int length, best_length = 0;
1017 int i, slen, colon, n;
1021 uint32_t goodness, best;
1023 struct prefix_info prefix;
1026 memset(&ins, 0, sizeof ins);
1029 * Scan for prefixes.
1031 memset(&prefix, 0, sizeof prefix);
1032 prefix.asize = segsize;
1033 prefix.osize = (segsize == 64) ? 32 : segsize;
1040 while (!end_prefix) {
1044 prefix.rep = *data++;
1048 prefix.wait = *data++;
1052 prefix.lock = *data++;
1056 segover = "cs", prefix.seg = *data++;
1059 segover = "ss", prefix.seg = *data++;
1062 segover = "ds", prefix.seg = *data++;
1065 segover = "es", prefix.seg = *data++;
1068 segover = "fs", prefix.seg = *data++;
1071 segover = "gs", prefix.seg = *data++;
1075 prefix.osize = (segsize == 16) ? 32 : 16;
1076 prefix.osp = *data++;
1079 prefix.asize = (segsize == 32) ? 16 : 32;
1080 prefix.asp = *data++;
1085 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1086 prefix.vex[0] = *data++;
1087 prefix.vex[1] = *data++;
1090 prefix.vex_c = RV_VEX;
1092 if (prefix.vex[0] == 0xc4) {
1093 prefix.vex[2] = *data++;
1094 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1095 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1096 prefix.vex_m = prefix.vex[1] & 0x1f;
1097 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1098 prefix.vex_lp = prefix.vex[2] & 7;
1100 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1102 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1103 prefix.vex_lp = prefix.vex[1] & 7;
1106 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1112 if ((data[1] & 030) != 0 &&
1113 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1114 prefix.vex[0] = *data++;
1115 prefix.vex[1] = *data++;
1116 prefix.vex[2] = *data++;
1119 prefix.vex_c = RV_XOP;
1121 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1122 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1123 prefix.vex_m = prefix.vex[1] & 0x1f;
1124 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1125 prefix.vex_lp = prefix.vex[2] & 7;
1127 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1148 if (segsize == 64) {
1149 prefix.rex = *data++;
1150 if (prefix.rex & REX_W)
1162 best = -1; /* Worst possible */
1164 best_pref = INT_MAX;
1167 return 0; /* No instruction table at all... */
1171 while (ix->n == -1) {
1172 ix = (const struct disasm_index *)ix->p + *dp++;
1175 p = (const struct itemplate * const *)ix->p;
1176 for (n = ix->n; n; n--, p++) {
1177 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1180 * Final check to make sure the types of r/m match up.
1181 * XXX: Need to make sure this is actually correct.
1183 for (i = 0; i < (*p)->operands; i++) {
1184 if (!((*p)->opd[i] & SAME_AS) &&
1186 /* If it's a mem-only EA but we have a
1188 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1189 is_class(MEMORY, (*p)->opd[i])) ||
1190 /* If it's a reg-only EA but we have a memory
1192 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1193 !(REG_EA & ~(*p)->opd[i]) &&
1194 !((*p)->opd[i] & REG_SMASK)) ||
1195 /* Register type mismatch (eg FS vs REG_DESS):
1197 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1198 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1199 !whichreg((*p)->opd[i],
1200 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1208 * Note: we always prefer instructions which incorporate
1209 * prefixes in the instructions themselves. This is to allow
1210 * e.g. PAUSE to be preferred to REP NOP, and deal with
1211 * MMX/SSE instructions where prefixes are used to select
1212 * between MMX and SSE register sets or outright opcode
1217 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1219 for (i = 0; i < MAXPREFIX; i++)
1220 if (tmp_ins.prefixes[i])
1222 if (nprefix < best_pref ||
1223 (nprefix == best_pref && goodness < best)) {
1224 /* This is the best one found so far */
1227 best_pref = nprefix;
1228 best_length = length;
1236 return 0; /* no instruction was matched */
1238 /* Pick the best match */
1240 length = best_length;
1244 /* TODO: snprintf returns the value that the string would have if
1245 * the buffer were long enough, and not the actual length of
1246 * the returned string, so each instance of using the return
1247 * value of snprintf should actually be checked to assure that
1248 * the return value is "sane." Maybe a macro wrapper could
1249 * be used for that purpose.
1251 for (i = 0; i < MAXPREFIX; i++) {
1252 const char *prefix = prefix_name(ins.prefixes[i]);
1254 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1258 if (i >= FIRST_COND_OPCODE)
1259 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1260 nasm_insn_names[i], condition_name[ins.condition]);
1262 slen += snprintf(output + slen, outbufsize - slen, "%s",
1263 nasm_insn_names[i]);
1266 length += data - origdata; /* fix up for prefixes */
1267 for (i = 0; i < (*p)->operands; i++) {
1268 opflags_t t = (*p)->opd[i];
1269 const operand *o = &ins.oprs[i];
1273 o = &ins.oprs[t & ~SAME_AS];
1274 t = (*p)->opd[t & ~SAME_AS];
1277 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1280 if (o->segment & SEG_RELATIVE) {
1281 offs += offset + length;
1283 * sort out wraparound
1285 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1287 else if (segsize != 64)
1291 * add sync marker, if autosync is on
1302 if ((t & (REGISTER | FPUREG)) ||
1303 (o->segment & SEG_RMREG)) {
1305 reg = whichreg(t, o->basereg, ins.rex);
1307 slen += snprintf(output + slen, outbufsize - slen, "to ");
1308 slen += snprintf(output + slen, outbufsize - slen, "%s",
1309 nasm_reg_names[reg-EXPR_REG_START]);
1310 } else if (!(UNITY & ~t)) {
1311 output[slen++] = '1';
1312 } else if (t & IMMEDIATE) {
1315 snprintf(output + slen, outbufsize - slen, "byte ");
1316 if (o->segment & SEG_SIGNED) {
1319 output[slen++] = '-';
1321 output[slen++] = '+';
1323 } else if (t & BITS16) {
1325 snprintf(output + slen, outbufsize - slen, "word ");
1326 } else if (t & BITS32) {
1328 snprintf(output + slen, outbufsize - slen, "dword ");
1329 } else if (t & BITS64) {
1331 snprintf(output + slen, outbufsize - slen, "qword ");
1332 } else if (t & NEAR) {
1334 snprintf(output + slen, outbufsize - slen, "near ");
1335 } else if (t & SHORT) {
1337 snprintf(output + slen, outbufsize - slen, "short ");
1340 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1342 } else if (!(MEM_OFFS & ~t)) {
1344 snprintf(output + slen, outbufsize - slen,
1345 "[%s%s%s0x%"PRIx64"]",
1346 (segover ? segover : ""),
1347 (segover ? ":" : ""),
1348 (o->disp_size == 64 ? "qword " :
1349 o->disp_size == 32 ? "dword " :
1350 o->disp_size == 16 ? "word " : ""), offs);
1352 } else if (is_class(REGMEM, t)) {
1353 int started = false;
1356 snprintf(output + slen, outbufsize - slen, "byte ");
1359 snprintf(output + slen, outbufsize - slen, "word ");
1362 snprintf(output + slen, outbufsize - slen, "dword ");
1365 snprintf(output + slen, outbufsize - slen, "qword ");
1368 snprintf(output + slen, outbufsize - slen, "tword ");
1371 snprintf(output + slen, outbufsize - slen, "oword ");
1374 snprintf(output + slen, outbufsize - slen, "yword ");
1376 slen += snprintf(output + slen, outbufsize - slen, "far ");
1379 snprintf(output + slen, outbufsize - slen, "near ");
1380 output[slen++] = '[';
1382 slen += snprintf(output + slen, outbufsize - slen, "%s",
1383 (o->disp_size == 64 ? "qword " :
1384 o->disp_size == 32 ? "dword " :
1385 o->disp_size == 16 ? "word " :
1387 if (o->eaflags & EAF_REL)
1388 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1391 snprintf(output + slen, outbufsize - slen, "%s:",
1395 if (o->basereg != -1) {
1396 slen += snprintf(output + slen, outbufsize - slen, "%s",
1397 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1400 if (o->indexreg != -1) {
1402 output[slen++] = '+';
1403 slen += snprintf(output + slen, outbufsize - slen, "%s",
1404 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1407 snprintf(output + slen, outbufsize - slen, "*%d",
1413 if (o->segment & SEG_DISP8) {
1415 uint8_t offset = offs;
1416 if ((int8_t)offset < 0) {
1423 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1425 } else if (o->segment & SEG_DISP16) {
1427 uint16_t offset = offs;
1428 if ((int16_t)offset < 0 && started) {
1432 prefix = started ? "+" : "";
1435 snprintf(output + slen, outbufsize - slen,
1436 "%s0x%"PRIx16"", prefix, offset);
1437 } else if (o->segment & SEG_DISP32) {
1438 if (prefix.asize == 64) {
1440 uint64_t offset = (int64_t)(int32_t)offs;
1441 if ((int32_t)offs < 0 && started) {
1445 prefix = started ? "+" : "";
1448 snprintf(output + slen, outbufsize - slen,
1449 "%s0x%"PRIx64"", prefix, offset);
1452 uint32_t offset = offs;
1453 if ((int32_t) offset < 0 && started) {
1457 prefix = started ? "+" : "";
1460 snprintf(output + slen, outbufsize - slen,
1461 "%s0x%"PRIx32"", prefix, offset);
1464 output[slen++] = ']';
1467 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1471 output[slen] = '\0';
1472 if (segover) { /* unused segment override */
1474 int count = slen + 1;
1476 p[count + 3] = p[count];
1477 strncpy(output, segover, 2);
1484 * This is called when we don't have a complete instruction. If it
1485 * is a standalone *single-byte* prefix show it as such, otherwise
1486 * print it as a literal.
1488 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1490 uint8_t byte = *data;
1491 const char *str = NULL;
1525 str = (segsize == 16) ? "o32" : "o16";
1528 str = (segsize == 32) ? "a16" : "a32";
1546 if (segsize == 64) {
1547 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1548 (byte == REX_P) ? "" : ".",
1549 (byte & REX_W) ? "w" : "",
1550 (byte & REX_R) ? "r" : "",
1551 (byte & REX_X) ? "x" : "",
1552 (byte & REX_B) ? "b" : "");
1555 /* else fall through */
1557 snprintf(output, outbufsize, "db 0x%02x", byte);
1562 snprintf(output, outbufsize, "%s", str);