1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
57 #define getu8(x) (*(uint8_t *)(x))
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
64 static uint16_t getu16(uint8_t *data)
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
68 static uint32_t getu32(uint8_t *data)
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
72 static uint64_t getu64(uint8_t *data)
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
91 if (!(REG_AL & ~regflags))
93 if (!(REG_AX & ~regflags))
95 if (!(REG_EAX & ~regflags))
97 if (!(REG_RAX & ~regflags))
99 if (!(REG_DL & ~regflags))
101 if (!(REG_DX & ~regflags))
103 if (!(REG_EDX & ~regflags))
105 if (!(REG_RDX & ~regflags))
107 if (!(REG_CL & ~regflags))
109 if (!(REG_CX & ~regflags))
111 if (!(REG_ECX & ~regflags))
113 if (!(REG_RCX & ~regflags))
115 if (!(FPU0 & ~regflags))
117 if (!(XMM0 & ~regflags))
119 if (!(YMM0 & ~regflags))
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
135 if (!(REG8 & ~regflags)) {
137 return nasm_rd_reg8_rex[regval];
139 return nasm_rd_reg8[regval];
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
171 * Process a DREX suffix
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
189 * Process an effective address (ModRM) specification.
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
194 int mod, rm, scale, index, base;
198 mod = (modrm >> 6) & 03;
201 if (mod != 3 && rm == 4 && asize != 16)
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
259 if (rm == 6 && mod == 0) { /* special case */
263 mod = 2; /* fake disp16 */
267 op->segment |= SEG_NODISP;
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
292 int a64 = asize == 64;
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
301 if (rm == 5 && mod == 0) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
309 op->disp_size = asize;
312 mod = 2; /* fake disp32 */
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
320 op->scale = 1 << scale;
323 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
329 if (base == 5 && mod == 0) {
331 mod = 2; /* Fake disp32 */
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
343 op->segment |= SEG_NODISP;
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
378 int s_field_for = -1; /* No 144/154 series code encountered */
381 for (i = 0; i < MAX_OPERANDS; i++) {
382 ins->oprs[i].segment = ins->oprs[i].disp_size =
383 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
386 ins->rex = prefix->rex;
387 memset(ins->prefixes, 0, sizeof ins->prefixes);
389 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
392 if (prefix->rep == 0xF2)
394 else if (prefix->rep == 0xF3)
397 while ((c = *r++) != 0) {
398 opx = &ins->oprs[c & 3];
412 ins->oprs[0].basereg = 0;
415 ins->oprs[0].basereg = 2;
418 ins->oprs[0].basereg = 3;
428 ins->oprs[0].basereg = 4;
431 ins->oprs[0].basereg = 5;
441 ins->oprs[0].basereg = 0;
444 ins->oprs[0].basereg = 1;
447 ins->oprs[0].basereg = 2;
450 ins->oprs[0].basereg = 3;
460 ins->oprs[0].basereg = 4;
463 ins->oprs[0].basereg = 5;
472 int t = *r++, d = *data++;
473 if (d < t || d > t + 7)
476 opx->basereg = (d-t)+
477 (ins->rex & REX_B ? 8 : 0);
478 opx->segment |= SEG_RMREG;
484 opx->offset = (int8_t)*data++;
485 opx->segment |= SEG_SIGNED;
489 opx->offset = *data++;
493 opx->offset = *data++;
497 opx->offset = getu16(data);
503 opx->offset = getu32(data);
506 opx->offset = getu16(data);
509 if (segsize != asize)
510 opx->disp_size = asize;
514 opx->offset = getu32(data);
521 opx->offset = getu16(data);
527 opx->offset = getu32(data);
533 opx->offset = getu64(data);
541 opx->offset = gets8(data++);
542 opx->segment |= SEG_RELATIVE;
546 opx->offset = getu64(data);
551 opx->offset = gets16(data);
553 opx->segment |= SEG_RELATIVE;
554 opx->segment &= ~SEG_32BIT;
558 opx->segment |= SEG_RELATIVE;
560 opx->offset = gets16(data);
562 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
563 } else if (osize == 32) {
564 opx->offset = gets32(data);
566 opx->segment &= ~SEG_64BIT;
567 opx->segment |= SEG_32BIT;
569 if (segsize != osize) {
571 (opx->type & ~SIZE_MASK)
572 | ((osize == 16) ? BITS16 : BITS32);
577 opx->offset = gets32(data);
579 opx->segment |= SEG_32BIT | SEG_RELATIVE;
588 opx->segment |= SEG_RMREG;
589 data = do_ea(data, modrm, asize, segsize,
590 &ins->oprs[(c >> 3) & 3], ins);
593 opx->basereg = ((modrm >> 3)&7)+
594 (ins->rex & REX_R ? 8 : 0);
599 if (s_field_for == (c & 3)) {
600 opx->offset = gets8(data);
603 opx->offset = getu16(data);
610 s_field_for = (*data & 0x02) ? c & 3 : -1;
611 if ((*data++ & ~0x02) != *r++)
616 if (s_field_for == (c & 3)) {
617 opx->offset = gets8(data);
620 opx->offset = getu32(data);
627 ins->drexdst = c & 3;
631 ins->rex |= REX_D|REX_OC;
632 ins->drexdst = c & 3;
636 data = do_drex(data, ins);
643 uint8_t ximm = *data++;
645 ins->oprs[c >> 3].basereg = ximm >> 4;
646 ins->oprs[c >> 3].segment |= SEG_RMREG;
647 ins->oprs[c & 7].offset = ximm & 15;
653 uint8_t ximm = *data++;
659 ins->oprs[c >> 4].basereg = ximm >> 4;
660 ins->oprs[c >> 4].segment |= SEG_RMREG;
666 uint8_t ximm = *data++;
669 ins->oprs[c].basereg = ximm >> 4;
670 ins->oprs[c].segment |= SEG_RMREG;
684 if (((modrm >> 3) & 07) != (c & 07))
685 return false; /* spare field doesn't match up */
686 data = do_ea(data, modrm, asize, segsize,
687 &ins->oprs[(c >> 3) & 07], ins);
698 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
701 if ((vexm & 0x1f) != prefix->vex_m)
704 switch (vexwlp & 030) {
706 if (prefix->rex & REX_W)
710 if (!(prefix->rex & REX_W))
714 break; /* XXX: Need to do anything special here? */
717 if ((vexwlp & 007) != prefix->vex_lp)
720 opx->segment |= SEG_RMREG;
721 opx->basereg = prefix->vex_v;
731 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
734 if ((vexm & 0x1f) != prefix->vex_m)
737 switch (vexwlp & 030) {
739 if (ins->rex & REX_W)
743 if (!(ins->rex & REX_W))
747 break; /* Need to do anything special here? */
750 if ((vexwlp & 007) != prefix->vex_lp)
753 if (prefix->vex_v != 0)
775 if (asize != segsize)
789 if (prefix->rex & REX_B)
794 if (prefix->rex & REX_X)
799 if (prefix->rex & REX_R)
804 if (prefix->rex & REX_W)
823 if (osize != (segsize == 16) ? 16 : 32)
830 ins->rex |= REX_W; /* 64-bit only instruction */
836 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
843 int t = *r++, d = *data++;
844 if (d < t || d > t + 15)
847 ins->condition = d - t;
857 if (prefix->rep != 0xF2)
863 if (prefix->rep != 0xF3)
884 if (prefix->osp || prefix->rep)
889 if (!prefix->osp || prefix->rep)
895 if (prefix->osp || prefix->rep != 0xf2)
901 if (prefix->osp || prefix->rep != 0xf3)
929 return false; /* Unknown code */
933 if (!vex_ok && (ins->rex & REX_V))
936 /* REX cannot be combined with DREX or VEX */
937 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
941 * Check for unused rep or a/o prefixes.
943 for (i = 0; i < t->operands; i++) {
944 if (ins->oprs[i].segment != SEG_RMREG)
949 if (ins->prefixes[PPS_LREP])
951 ins->prefixes[PPS_LREP] = P_LOCK;
954 if (ins->prefixes[PPS_LREP])
956 ins->prefixes[PPS_LREP] = drep;
959 if (osize != ((segsize == 16) ? 16 : 32)) {
960 enum prefixes pfx = 0;
974 if (ins->prefixes[PPS_OSIZE])
976 ins->prefixes[PPS_OSIZE] = pfx;
979 if (!a_used && asize != segsize) {
980 if (ins->prefixes[PPS_ASIZE])
982 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
985 /* Fix: check for redundant REX prefixes */
987 return data - origdata;
990 /* Condition names for disassembly, sorted by x86 code */
991 static const char * const condition_name[16] = {
992 "o", "no", "c", "nc", "z", "nz", "na", "a",
993 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
996 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
997 int32_t offset, int autosync, uint32_t prefer)
999 const struct itemplate * const *p, * const *best_p;
1000 const struct disasm_index *ix;
1002 int length, best_length = 0;
1004 int i, slen, colon, n;
1008 uint32_t goodness, best;
1010 struct prefix_info prefix;
1013 memset(&ins, 0, sizeof ins);
1016 * Scan for prefixes.
1018 memset(&prefix, 0, sizeof prefix);
1019 prefix.asize = segsize;
1020 prefix.osize = (segsize == 64) ? 32 : segsize;
1027 while (!end_prefix) {
1031 prefix.rep = *data++;
1035 prefix.lock = *data++;
1039 segover = "cs", prefix.seg = *data++;
1042 segover = "ss", prefix.seg = *data++;
1045 segover = "ds", prefix.seg = *data++;
1048 segover = "es", prefix.seg = *data++;
1051 segover = "fs", prefix.seg = *data++;
1054 segover = "gs", prefix.seg = *data++;
1058 prefix.osize = (segsize == 16) ? 32 : 16;
1059 prefix.osp = *data++;
1062 prefix.asize = (segsize == 32) ? 16 : 32;
1063 prefix.asp = *data++;
1068 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1069 prefix.vex[0] = *data++;
1070 prefix.vex[1] = *data++;
1071 if (prefix.vex[0] == 0xc4)
1072 prefix.vex[2] = *data++;
1075 if (prefix.vex[0] == 0xc4) {
1076 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1077 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1078 prefix.vex_m = prefix.vex[1] & 0x1f;
1079 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1080 prefix.vex_lp = prefix.vex[2] & 7;
1082 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1084 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1085 prefix.vex_lp = prefix.vex[1] & 7;
1088 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1108 if (segsize == 64) {
1109 prefix.rex = *data++;
1110 if (prefix.rex & REX_W)
1122 best = -1; /* Worst possible */
1124 best_pref = INT_MAX;
1127 return 0; /* No instruction table at all... */
1131 while (ix->n == -1) {
1132 ix = (const struct disasm_index *)ix->p + *dp++;
1135 p = (const struct itemplate * const *)ix->p;
1136 for (n = ix->n; n; n--, p++) {
1137 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1140 * Final check to make sure the types of r/m match up.
1141 * XXX: Need to make sure this is actually correct.
1143 for (i = 0; i < (*p)->operands; i++) {
1144 if (!((*p)->opd[i] & SAME_AS) &&
1146 /* If it's a mem-only EA but we have a
1148 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1149 !(MEMORY & ~(*p)->opd[i])) ||
1150 /* If it's a reg-only EA but we have a memory
1152 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1153 !(REG_EA & ~(*p)->opd[i]) &&
1154 !((*p)->opd[i] & REG_SMASK)) ||
1155 /* Register type mismatch (eg FS vs REG_DESS):
1157 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1158 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1159 !whichreg((*p)->opd[i],
1160 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1168 * Note: we always prefer instructions which incorporate
1169 * prefixes in the instructions themselves. This is to allow
1170 * e.g. PAUSE to be preferred to REP NOP, and deal with
1171 * MMX/SSE instructions where prefixes are used to select
1172 * between MMX and SSE register sets or outright opcode
1177 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1179 for (i = 0; i < MAXPREFIX; i++)
1180 if (tmp_ins.prefixes[i])
1182 if (nprefix < best_pref ||
1183 (nprefix == best_pref && goodness < best)) {
1184 /* This is the best one found so far */
1187 best_pref = nprefix;
1188 best_length = length;
1196 return 0; /* no instruction was matched */
1198 /* Pick the best match */
1200 length = best_length;
1204 /* TODO: snprintf returns the value that the string would have if
1205 * the buffer were long enough, and not the actual length of
1206 * the returned string, so each instance of using the return
1207 * value of snprintf should actually be checked to assure that
1208 * the return value is "sane." Maybe a macro wrapper could
1209 * be used for that purpose.
1211 for (i = 0; i < MAXPREFIX; i++)
1212 switch (ins.prefixes[i]) {
1214 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1217 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1220 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1223 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1226 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1229 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1232 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1235 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1238 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1241 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1248 if (i >= FIRST_COND_OPCODE) {
1249 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1250 nasm_cond_insn_names[i-FIRST_COND_OPCODE],
1251 condition_name[ins.condition]);
1253 slen += snprintf(output + slen, outbufsize - slen, "%s",
1254 nasm_insn_names[i]);
1257 length += data - origdata; /* fix up for prefixes */
1258 for (i = 0; i < (*p)->operands; i++) {
1259 opflags_t t = (*p)->opd[i];
1260 const operand *o = &ins.oprs[i];
1264 o = &ins.oprs[t & ~SAME_AS];
1265 t = (*p)->opd[t & ~SAME_AS];
1268 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1271 if (o->segment & SEG_RELATIVE) {
1272 offs += offset + length;
1274 * sort out wraparound
1276 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1278 else if (segsize != 64)
1282 * add sync marker, if autosync is on
1293 if ((t & (REGISTER | FPUREG)) ||
1294 (o->segment & SEG_RMREG)) {
1296 reg = whichreg(t, o->basereg, ins.rex);
1298 slen += snprintf(output + slen, outbufsize - slen, "to ");
1299 slen += snprintf(output + slen, outbufsize - slen, "%s",
1300 nasm_reg_names[reg-EXPR_REG_START]);
1301 } else if (!(UNITY & ~t)) {
1302 output[slen++] = '1';
1303 } else if (t & IMMEDIATE) {
1306 snprintf(output + slen, outbufsize - slen, "byte ");
1307 if (o->segment & SEG_SIGNED) {
1310 output[slen++] = '-';
1312 output[slen++] = '+';
1314 } else if (t & BITS16) {
1316 snprintf(output + slen, outbufsize - slen, "word ");
1317 } else if (t & BITS32) {
1319 snprintf(output + slen, outbufsize - slen, "dword ");
1320 } else if (t & BITS64) {
1322 snprintf(output + slen, outbufsize - slen, "qword ");
1323 } else if (t & NEAR) {
1325 snprintf(output + slen, outbufsize - slen, "near ");
1326 } else if (t & SHORT) {
1328 snprintf(output + slen, outbufsize - slen, "short ");
1331 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1333 } else if (!(MEM_OFFS & ~t)) {
1335 snprintf(output + slen, outbufsize - slen,
1336 "[%s%s%s0x%"PRIx64"]",
1337 (segover ? segover : ""),
1338 (segover ? ":" : ""),
1339 (o->disp_size == 64 ? "qword " :
1340 o->disp_size == 32 ? "dword " :
1341 o->disp_size == 16 ? "word " : ""), offs);
1343 } else if (!(REGMEM & ~t)) {
1344 int started = false;
1347 snprintf(output + slen, outbufsize - slen, "byte ");
1350 snprintf(output + slen, outbufsize - slen, "word ");
1353 snprintf(output + slen, outbufsize - slen, "dword ");
1356 snprintf(output + slen, outbufsize - slen, "qword ");
1359 snprintf(output + slen, outbufsize - slen, "tword ");
1362 snprintf(output + slen, outbufsize - slen, "oword ");
1365 snprintf(output + slen, outbufsize - slen, "yword ");
1367 slen += snprintf(output + slen, outbufsize - slen, "far ");
1370 snprintf(output + slen, outbufsize - slen, "near ");
1371 output[slen++] = '[';
1373 slen += snprintf(output + slen, outbufsize - slen, "%s",
1374 (o->disp_size == 64 ? "qword " :
1375 o->disp_size == 32 ? "dword " :
1376 o->disp_size == 16 ? "word " :
1378 if (o->eaflags & EAF_REL)
1379 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1382 snprintf(output + slen, outbufsize - slen, "%s:",
1386 if (o->basereg != -1) {
1387 slen += snprintf(output + slen, outbufsize - slen, "%s",
1388 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1391 if (o->indexreg != -1) {
1393 output[slen++] = '+';
1394 slen += snprintf(output + slen, outbufsize - slen, "%s",
1395 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1398 snprintf(output + slen, outbufsize - slen, "*%d",
1404 if (o->segment & SEG_DISP8) {
1406 uint8_t offset = offs;
1407 if ((int8_t)offset < 0) {
1414 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1416 } else if (o->segment & SEG_DISP16) {
1418 uint16_t offset = offs;
1419 if ((int16_t)offset < 0 && started) {
1423 prefix = started ? "+" : "";
1426 snprintf(output + slen, outbufsize - slen,
1427 "%s0x%"PRIx16"", prefix, offset);
1428 } else if (o->segment & SEG_DISP32) {
1429 if (prefix.asize == 64) {
1431 uint64_t offset = (int64_t)(int32_t)offs;
1432 if ((int32_t)offs < 0 && started) {
1436 prefix = started ? "+" : "";
1439 snprintf(output + slen, outbufsize - slen,
1440 "%s0x%"PRIx64"", prefix, offset);
1443 uint32_t offset = offs;
1444 if ((int32_t) offset < 0 && started) {
1448 prefix = started ? "+" : "";
1451 snprintf(output + slen, outbufsize - slen,
1452 "%s0x%"PRIx32"", prefix, offset);
1455 output[slen++] = ']';
1458 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1462 output[slen] = '\0';
1463 if (segover) { /* unused segment override */
1465 int count = slen + 1;
1467 p[count + 3] = p[count];
1468 strncpy(output, segover, 2);
1474 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1476 snprintf(output, outbufsize, "db 0x%02X", *data);