1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
26 * Flags that go into the `segment' field of `insn' structures
29 #define SEG_RELATIVE 1
36 #define SEG_SIGNED 128
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
57 #define getu8(x) (*(uint8_t *)(x))
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
64 static uint16_t getu16(uint8_t *data)
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
68 static uint32_t getu32(uint8_t *data)
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
72 static uint64_t getu64(uint8_t *data)
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
91 if (!(REG_AL & ~regflags))
93 if (!(REG_AX & ~regflags))
95 if (!(REG_EAX & ~regflags))
97 if (!(REG_RAX & ~regflags))
99 if (!(REG_DL & ~regflags))
101 if (!(REG_DX & ~regflags))
103 if (!(REG_EDX & ~regflags))
105 if (!(REG_RDX & ~regflags))
107 if (!(REG_CL & ~regflags))
109 if (!(REG_CX & ~regflags))
111 if (!(REG_ECX & ~regflags))
113 if (!(REG_RCX & ~regflags))
115 if (!(FPU0 & ~regflags))
117 if (!(REG_CS & ~regflags))
118 return (regval == 1) ? R_CS : 0;
119 if (!(REG_DESS & ~regflags))
120 return (regval == 0 || regval == 2
121 || regval == 3 ? nasm_rd_sreg[regval] : 0);
122 if (!(REG_FSGS & ~regflags))
123 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
124 if (!(REG_SEG67 & ~regflags))
125 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
127 /* All the entries below look up regval in an 16-entry array */
128 if (regval < 0 || regval > 15)
131 if (!(REG8 & ~regflags)) {
133 return nasm_rd_reg8_rex[regval];
135 return nasm_rd_reg8[regval];
137 if (!(REG16 & ~regflags))
138 return nasm_rd_reg16[regval];
139 if (!(REG32 & ~regflags))
140 return nasm_rd_reg32[regval];
141 if (!(REG64 & ~regflags))
142 return nasm_rd_reg64[regval];
143 if (!(REG_SREG & ~regflags))
144 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
145 if (!(REG_CREG & ~regflags))
146 return nasm_rd_creg[regval];
147 if (!(REG_DREG & ~regflags))
148 return nasm_rd_dreg[regval];
149 if (!(REG_TREG & ~regflags)) {
151 return 0; /* TR registers are ill-defined with rex */
152 return nasm_rd_treg[regval];
154 if (!(FPUREG & ~regflags))
155 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
156 if (!(MMXREG & ~regflags))
157 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
158 if (!(XMMREG & ~regflags))
159 return nasm_rd_xmmreg[regval];
160 if (!(YMMREG & ~regflags))
161 return nasm_rd_ymmreg[regval];
167 * Process a DREX suffix
169 static uint8_t *do_drex(uint8_t *data, insn *ins)
171 uint8_t drex = *data++;
172 operand *dst = &ins->oprs[ins->drexdst];
174 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
175 return NULL; /* OC0 mismatch */
176 ins->rex = (ins->rex & ~7) | (drex & 7);
178 dst->segment = SEG_RMREG;
179 dst->basereg = drex >> 4;
185 * Process an effective address (ModRM) specification.
187 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
188 int segsize, operand * op, insn *ins)
190 int mod, rm, scale, index, base;
194 mod = (modrm >> 6) & 03;
197 if (mod != 3 && rm == 4 && asize != 16)
200 if (ins->rex & REX_D) {
201 data = do_drex(data, ins);
207 if (mod == 3) { /* pure register version */
208 op->basereg = rm+(rex & REX_B ? 8 : 0);
209 op->segment |= SEG_RMREG;
218 * <mod> specifies the displacement size (none, byte or
219 * word), and <rm> specifies the register combination.
220 * Exception: mod=0,rm=6 does not specify [BP] as one might
221 * expect, but instead specifies [disp16].
223 op->indexreg = op->basereg = -1;
224 op->scale = 1; /* always, in 16 bits */
255 if (rm == 6 && mod == 0) { /* special case */
259 mod = 2; /* fake disp16 */
263 op->segment |= SEG_NODISP;
266 op->segment |= SEG_DISP8;
267 op->offset = (int8_t)*data++;
270 op->segment |= SEG_DISP16;
271 op->offset = *data++;
272 op->offset |= ((unsigned)*data++) << 8;
278 * Once again, <mod> specifies displacement size (this time
279 * none, byte or *dword*), while <rm> specifies the base
280 * register. Again, [EBP] is missing, replaced by a pure
281 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
282 * and RIP-relative addressing in 64-bit mode.
285 * indicates not a single base register, but instead the
286 * presence of a SIB byte...
288 int a64 = asize == 64;
293 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
295 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
297 if (rm == 5 && mod == 0) {
299 op->eaflags |= EAF_REL;
300 op->segment |= SEG_RELATIVE;
301 mod = 2; /* fake disp32 */
305 op->disp_size = asize;
308 mod = 2; /* fake disp32 */
311 if (rm == 4) { /* process SIB */
312 scale = (sib >> 6) & 03;
313 index = (sib >> 3) & 07;
316 op->scale = 1 << scale;
319 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
321 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
323 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
325 if (base == 5 && mod == 0) {
327 mod = 2; /* Fake disp32 */
329 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
331 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
339 op->segment |= SEG_NODISP;
342 op->segment |= SEG_DISP8;
343 op->offset = gets8(data);
347 op->segment |= SEG_DISP32;
348 op->offset = gets32(data);
357 * Determine whether the instruction template in t corresponds to the data
358 * stream in data. Return the number of bytes matched if so.
360 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
362 static int matches(const struct itemplate *t, uint8_t *data,
363 const struct prefix_info *prefix, int segsize, insn *ins)
365 uint8_t *r = (uint8_t *)(t->code);
366 uint8_t *origdata = data;
367 bool a_used = false, o_used = false;
368 enum prefixes drep = 0;
369 uint8_t lock = prefix->lock;
370 int osize = prefix->osize;
371 int asize = prefix->asize;
374 int s_field_for = -1; /* No 144/154 series code encountered */
377 for (i = 0; i < MAX_OPERANDS; i++) {
378 ins->oprs[i].segment = ins->oprs[i].disp_size =
379 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
382 ins->rex = prefix->rex;
383 memset(ins->prefixes, 0, sizeof ins->prefixes);
385 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
388 if (prefix->rep == 0xF2)
390 else if (prefix->rep == 0xF3)
393 while ((c = *r++) != 0) {
394 opx = &ins->oprs[c & 3];
408 ins->oprs[0].basereg = 0;
411 ins->oprs[0].basereg = 2;
414 ins->oprs[0].basereg = 3;
424 ins->oprs[0].basereg = 4;
427 ins->oprs[0].basereg = 5;
437 ins->oprs[0].basereg = 0;
440 ins->oprs[0].basereg = 1;
443 ins->oprs[0].basereg = 2;
446 ins->oprs[0].basereg = 3;
456 ins->oprs[0].basereg = 4;
459 ins->oprs[0].basereg = 5;
468 int t = *r++, d = *data++;
469 if (d < t || d > t + 7)
472 opx->basereg = (d-t)+
473 (ins->rex & REX_B ? 8 : 0);
474 opx->segment |= SEG_RMREG;
480 opx->offset = (int8_t)*data++;
481 opx->segment |= SEG_SIGNED;
485 opx->offset = *data++;
489 opx->offset = *data++;
493 opx->offset = getu16(data);
499 opx->offset = getu32(data);
502 opx->offset = getu16(data);
505 if (segsize != asize)
506 opx->disp_size = asize;
510 opx->offset = getu32(data);
517 opx->offset = getu16(data);
523 opx->offset = getu32(data);
529 opx->offset = getu64(data);
537 opx->offset = gets8(data++);
538 opx->segment |= SEG_RELATIVE;
542 opx->offset = getu64(data);
547 opx->offset = gets16(data);
549 opx->segment |= SEG_RELATIVE;
550 opx->segment &= ~SEG_32BIT;
554 opx->segment |= SEG_RELATIVE;
556 opx->offset = gets16(data);
558 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
559 } else if (osize == 32) {
560 opx->offset = gets32(data);
562 opx->segment &= ~SEG_64BIT;
563 opx->segment |= SEG_32BIT;
565 if (segsize != osize) {
567 (opx->type & ~SIZE_MASK)
568 | ((osize == 16) ? BITS16 : BITS32);
573 opx->offset = gets32(data);
575 opx->segment |= SEG_32BIT | SEG_RELATIVE;
584 opx->segment |= SEG_RMREG;
585 data = do_ea(data, modrm, asize, segsize,
586 &ins->oprs[(c >> 3) & 3], ins);
589 opx->basereg = ((modrm >> 3)&7)+
590 (ins->rex & REX_R ? 8 : 0);
595 if (s_field_for == (c & 3)) {
596 opx->offset = gets8(data);
599 opx->offset = getu16(data);
606 s_field_for = (*data & 0x02) ? c & 3 : -1;
607 if ((*data++ & ~0x02) != *r++)
612 if (s_field_for == (c & 3)) {
613 opx->offset = gets8(data);
616 opx->offset = getu32(data);
623 ins->drexdst = c & 3;
627 ins->rex |= REX_D|REX_OC;
628 ins->drexdst = c & 3;
632 data = do_drex(data, ins);
639 uint8_t ximm = *data++;
641 ins->oprs[c >> 3].basereg = ximm >> 4;
642 ins->oprs[c >> 3].segment |= SEG_RMREG;
643 ins->oprs[c & 7].offset = ximm & 15;
649 uint8_t ximm = *data++;
655 ins->oprs[c >> 4].basereg = ximm >> 4;
656 ins->oprs[c >> 4].segment |= SEG_RMREG;
662 uint8_t ximm = *data++;
665 ins->oprs[c].basereg = ximm >> 4;
666 ins->oprs[c].segment |= SEG_RMREG;
680 if (((modrm >> 3) & 07) != (c & 07))
681 return false; /* spare field doesn't match up */
682 data = do_ea(data, modrm, asize, segsize,
683 &ins->oprs[(c >> 3) & 07], ins);
694 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
697 if ((vexm & 0x1f) != prefix->vex_m)
700 switch (vexwlp & 030) {
702 if (prefix->rex & REX_W)
706 if (!(prefix->rex & REX_W))
710 break; /* XXX: Need to do anything special here? */
713 if ((vexwlp & 007) != prefix->vex_lp)
716 opx->segment |= SEG_RMREG;
717 opx->basereg = prefix->vex_v;
727 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
730 if ((vexm & 0x1f) != prefix->vex_m)
733 switch (vexwlp & 030) {
735 if (ins->rex & REX_W)
739 if (!(ins->rex & REX_W))
743 break; /* Need to do anything special here? */
746 if ((vexwlp & 007) != prefix->vex_lp)
749 if (prefix->vex_v != 0)
771 if (asize != segsize)
785 if (prefix->rex & REX_B)
790 if (prefix->rex & REX_X)
795 if (prefix->rex & REX_R)
800 if (prefix->rex & REX_W)
819 if (osize != (segsize == 16) ? 16 : 32)
826 ins->rex |= REX_W; /* 64-bit only instruction */
832 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
839 int t = *r++, d = *data++;
840 if (d < t || d > t + 15)
843 ins->condition = d - t;
853 if (prefix->rep != 0xF2)
859 if (prefix->rep != 0xF3)
880 if (prefix->osp || prefix->rep)
885 if (!prefix->osp || prefix->rep)
890 if (prefix->osp || prefix->rep != 0xf2)
895 if (prefix->osp || prefix->rep != 0xf3)
922 return false; /* Unknown code */
926 if (!vex_ok && (ins->rex & REX_V))
929 /* REX cannot be combined with DREX or VEX */
930 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
934 * Check for unused rep or a/o prefixes.
936 for (i = 0; i < t->operands; i++) {
937 if (ins->oprs[i].segment != SEG_RMREG)
942 if (ins->prefixes[PPS_LREP])
944 ins->prefixes[PPS_LREP] = P_LOCK;
947 if (ins->prefixes[PPS_LREP])
949 ins->prefixes[PPS_LREP] = drep;
952 if (osize != ((segsize == 16) ? 16 : 32)) {
953 enum prefixes pfx = 0;
967 if (ins->prefixes[PPS_OSIZE])
969 ins->prefixes[PPS_OSIZE] = pfx;
972 if (!a_used && asize != segsize) {
973 if (ins->prefixes[PPS_ASIZE])
975 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
978 /* Fix: check for redundant REX prefixes */
980 return data - origdata;
983 /* Condition names for disassembly, sorted by x86 code */
984 static const char * const condition_name[16] = {
985 "o", "no", "c", "nc", "z", "nz", "na", "a",
986 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
989 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
990 int32_t offset, int autosync, uint32_t prefer)
992 const struct itemplate * const *p, * const *best_p;
993 const struct disasm_index *ix;
995 int length, best_length = 0;
997 int i, slen, colon, n;
1001 uint32_t goodness, best;
1003 struct prefix_info prefix;
1006 memset(&ins, 0, sizeof ins);
1009 * Scan for prefixes.
1011 memset(&prefix, 0, sizeof prefix);
1012 prefix.asize = segsize;
1013 prefix.osize = (segsize == 64) ? 32 : segsize;
1018 while (!end_prefix) {
1022 prefix.rep = *data++;
1025 prefix.lock = *data++;
1028 segover = "cs", prefix.seg = *data++;
1031 segover = "ss", prefix.seg = *data++;
1034 segover = "ds", prefix.seg = *data++;
1037 segover = "es", prefix.seg = *data++;
1040 segover = "fs", prefix.seg = *data++;
1043 segover = "gs", prefix.seg = *data++;
1046 prefix.osize = (segsize == 16) ? 32 : 16;
1047 prefix.osp = *data++;
1050 prefix.asize = (segsize == 32) ? 16 : 32;
1051 prefix.asp = *data++;
1055 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1056 prefix.vex[0] = *data++;
1057 prefix.vex[1] = *data++;
1058 if (prefix.vex[0] == 0xc4)
1059 prefix.vex[2] = *data++;
1062 if (prefix.vex[0] == 0xc4) {
1063 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1064 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1065 prefix.vex_m = prefix.vex[1] & 0x1f;
1066 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1067 prefix.vex_lp = prefix.vex[2] & 7;
1069 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1071 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1072 prefix.vex_lp = prefix.vex[1] & 7;
1092 if (segsize == 64) {
1093 prefix.rex = *data++;
1094 if (prefix.rex & REX_W)
1105 best = -1; /* Worst possible */
1107 best_pref = INT_MAX;
1110 ix = itable + *dp++;
1111 while (ix->n == -1) {
1112 ix = (const struct disasm_index *)ix->p + *dp++;
1115 p = (const struct itemplate * const *)ix->p;
1116 for (n = ix->n; n; n--, p++) {
1117 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1120 * Final check to make sure the types of r/m match up.
1121 * XXX: Need to make sure this is actually correct.
1123 for (i = 0; i < (*p)->operands; i++) {
1124 if (!((*p)->opd[i] & SAME_AS) &&
1126 /* If it's a mem-only EA but we have a
1128 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1129 !(MEMORY & ~(*p)->opd[i])) ||
1130 /* If it's a reg-only EA but we have a memory
1132 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1133 !(REG_EA & ~(*p)->opd[i]) &&
1134 !((*p)->opd[i] & REG_SMASK)) ||
1135 /* Register type mismatch (eg FS vs REG_DESS):
1137 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1138 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1139 !whichreg((*p)->opd[i],
1140 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1148 * Note: we always prefer instructions which incorporate
1149 * prefixes in the instructions themselves. This is to allow
1150 * e.g. PAUSE to be preferred to REP NOP, and deal with
1151 * MMX/SSE instructions where prefixes are used to select
1152 * between MMX and SSE register sets or outright opcode
1157 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1159 for (i = 0; i < MAXPREFIX; i++)
1160 if (tmp_ins.prefixes[i])
1162 if (nprefix < best_pref ||
1163 (nprefix == best_pref && goodness < best)) {
1164 /* This is the best one found so far */
1167 best_pref = nprefix;
1168 best_length = length;
1176 return 0; /* no instruction was matched */
1178 /* Pick the best match */
1180 length = best_length;
1184 /* TODO: snprintf returns the value that the string would have if
1185 * the buffer were long enough, and not the actual length of
1186 * the returned string, so each instance of using the return
1187 * value of snprintf should actually be checked to assure that
1188 * the return value is "sane." Maybe a macro wrapper could
1189 * be used for that purpose.
1191 for (i = 0; i < MAXPREFIX; i++)
1192 switch (ins.prefixes[i]) {
1194 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1197 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1200 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1203 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1206 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1209 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1212 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1215 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1218 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1221 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1228 if (i >= FIRST_COND_OPCODE) {
1229 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1230 nasm_cond_insn_names[i-FIRST_COND_OPCODE],
1231 condition_name[ins.condition]);
1233 slen += snprintf(output + slen, outbufsize - slen, "%s",
1234 nasm_insn_names[i]);
1237 length += data - origdata; /* fix up for prefixes */
1238 for (i = 0; i < (*p)->operands; i++) {
1239 opflags_t t = (*p)->opd[i];
1240 const operand *o = &ins.oprs[i];
1244 o = &ins.oprs[t & ~SAME_AS];
1245 t = (*p)->opd[t & ~SAME_AS];
1248 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1251 if (o->segment & SEG_RELATIVE) {
1252 offs += offset + length;
1254 * sort out wraparound
1256 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1258 else if (segsize != 64)
1262 * add sync marker, if autosync is on
1273 if ((t & (REGISTER | FPUREG)) ||
1274 (o->segment & SEG_RMREG)) {
1276 reg = whichreg(t, o->basereg, ins.rex);
1278 slen += snprintf(output + slen, outbufsize - slen, "to ");
1279 slen += snprintf(output + slen, outbufsize - slen, "%s",
1280 nasm_reg_names[reg-EXPR_REG_START]);
1281 } else if (!(UNITY & ~t)) {
1282 output[slen++] = '1';
1283 } else if (t & IMMEDIATE) {
1286 snprintf(output + slen, outbufsize - slen, "byte ");
1287 if (o->segment & SEG_SIGNED) {
1290 output[slen++] = '-';
1292 output[slen++] = '+';
1294 } else if (t & BITS16) {
1296 snprintf(output + slen, outbufsize - slen, "word ");
1297 } else if (t & BITS32) {
1299 snprintf(output + slen, outbufsize - slen, "dword ");
1300 } else if (t & BITS64) {
1302 snprintf(output + slen, outbufsize - slen, "qword ");
1303 } else if (t & NEAR) {
1305 snprintf(output + slen, outbufsize - slen, "near ");
1306 } else if (t & SHORT) {
1308 snprintf(output + slen, outbufsize - slen, "short ");
1311 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1313 } else if (!(MEM_OFFS & ~t)) {
1315 snprintf(output + slen, outbufsize - slen,
1316 "[%s%s%s0x%"PRIx64"]",
1317 (segover ? segover : ""),
1318 (segover ? ":" : ""),
1319 (o->disp_size == 64 ? "qword " :
1320 o->disp_size == 32 ? "dword " :
1321 o->disp_size == 16 ? "word " : ""), offs);
1323 } else if (!(REGMEM & ~t)) {
1324 int started = false;
1327 snprintf(output + slen, outbufsize - slen, "byte ");
1330 snprintf(output + slen, outbufsize - slen, "word ");
1333 snprintf(output + slen, outbufsize - slen, "dword ");
1336 snprintf(output + slen, outbufsize - slen, "qword ");
1339 snprintf(output + slen, outbufsize - slen, "tword ");
1342 snprintf(output + slen, outbufsize - slen, "oword ");
1345 snprintf(output + slen, outbufsize - slen, "yword ");
1347 slen += snprintf(output + slen, outbufsize - slen, "far ");
1350 snprintf(output + slen, outbufsize - slen, "near ");
1351 output[slen++] = '[';
1353 slen += snprintf(output + slen, outbufsize - slen, "%s",
1354 (o->disp_size == 64 ? "qword " :
1355 o->disp_size == 32 ? "dword " :
1356 o->disp_size == 16 ? "word " :
1358 if (o->eaflags & EAF_REL)
1359 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1362 snprintf(output + slen, outbufsize - slen, "%s:",
1366 if (o->basereg != -1) {
1367 slen += snprintf(output + slen, outbufsize - slen, "%s",
1368 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1371 if (o->indexreg != -1) {
1373 output[slen++] = '+';
1374 slen += snprintf(output + slen, outbufsize - slen, "%s",
1375 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1378 snprintf(output + slen, outbufsize - slen, "*%d",
1384 if (o->segment & SEG_DISP8) {
1386 uint8_t offset = offs;
1387 if ((int8_t)offset < 0) {
1394 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1396 } else if (o->segment & SEG_DISP16) {
1398 uint16_t offset = offs;
1399 if ((int16_t)offset < 0 && started) {
1403 prefix = started ? "+" : "";
1406 snprintf(output + slen, outbufsize - slen,
1407 "%s0x%"PRIx16"", prefix, offset);
1408 } else if (o->segment & SEG_DISP32) {
1409 if (prefix.asize == 64) {
1411 uint64_t offset = (int64_t)(int32_t)offs;
1412 if ((int32_t)offs < 0 && started) {
1416 prefix = started ? "+" : "";
1419 snprintf(output + slen, outbufsize - slen,
1420 "%s0x%"PRIx64"", prefix, offset);
1423 uint32_t offset = offs;
1424 if ((int32_t) offset < 0 && started) {
1428 prefix = started ? "+" : "";
1431 snprintf(output + slen, outbufsize - slen,
1432 "%s0x%"PRIx32"", prefix, offset);
1435 output[slen++] = ']';
1438 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1442 output[slen] = '\0';
1443 if (segover) { /* unused segment override */
1445 int count = slen + 1;
1447 p[count + 3] = p[count];
1448 strncpy(output, segover, 2);
1454 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1456 snprintf(output, outbufsize, "db 0x%02X", *data);