1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
53 * Flags that go into the `segment' field of `insn' structures
56 #define SEG_RELATIVE 1
63 #define SEG_SIGNED 128
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
86 #define getu8(x) (*(uint8_t *)(x))
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
93 static uint16_t getu16(uint8_t *data)
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 static uint32_t getu32(uint8_t *data)
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 static uint64_t getu64(uint8_t *data)
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
117 static const struct {
120 } specific_registers[] = {
144 if (!(regflags & (REGISTER|REGMEM)))
145 return 0; /* Registers not permissible?! */
147 regflags |= REGISTER;
149 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
150 if (!(specific_registers[i].flags & ~regflags))
151 return specific_registers[i].reg;
153 /* All the entries below look up regval in an 16-entry array */
154 if (regval < 0 || regval > 15)
157 if (!(REG8 & ~regflags)) {
158 if (rex & (REX_P|REX_NH))
159 return nasm_rd_reg8_rex[regval];
161 return nasm_rd_reg8[regval];
163 if (!(REG16 & ~regflags))
164 return nasm_rd_reg16[regval];
165 if (!(REG32 & ~regflags))
166 return nasm_rd_reg32[regval];
167 if (!(REG64 & ~regflags))
168 return nasm_rd_reg64[regval];
169 if (!(REG_SREG & ~regflags))
170 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
171 if (!(REG_CREG & ~regflags))
172 return nasm_rd_creg[regval];
173 if (!(REG_DREG & ~regflags))
174 return nasm_rd_dreg[regval];
175 if (!(REG_TREG & ~regflags)) {
177 return 0; /* TR registers are ill-defined with rex */
178 return nasm_rd_treg[regval];
180 if (!(FPUREG & ~regflags))
181 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
182 if (!(MMXREG & ~regflags))
183 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
184 if (!(XMMREG & ~regflags))
185 return nasm_rd_xmmreg[regval];
186 if (!(YMMREG & ~regflags))
187 return nasm_rd_ymmreg[regval];
193 * Process an effective address (ModRM) specification.
195 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
196 int segsize, enum ea_type type,
197 operand *op, insn *ins)
199 int mod, rm, scale, index, base;
203 mod = (modrm >> 6) & 03;
206 if (mod != 3 && asize != 16 && rm == 4)
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
228 if (type != EA_SCALAR)
231 op->indexreg = op->basereg = -1;
232 op->scale = 1; /* always, in 16 bits */
263 if (rm == 6 && mod == 0) { /* special case */
267 mod = 2; /* fake disp16 */
271 op->segment |= SEG_NODISP;
274 op->segment |= SEG_DISP8;
275 op->offset = (int8_t)*data++;
278 op->segment |= SEG_DISP16;
279 op->offset = *data++;
280 op->offset |= ((unsigned)*data++) << 8;
286 * Once again, <mod> specifies displacement size (this time
287 * none, byte or *dword*), while <rm> specifies the base
288 * register. Again, [EBP] is missing, replaced by a pure
289 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
290 * and RIP-relative addressing in 64-bit mode.
293 * indicates not a single base register, but instead the
294 * presence of a SIB byte...
296 int a64 = asize == 64;
301 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
303 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
305 if (rm == 5 && mod == 0) {
307 op->eaflags |= EAF_REL;
308 op->segment |= SEG_RELATIVE;
309 mod = 2; /* fake disp32 */
313 op->disp_size = asize;
316 mod = 2; /* fake disp32 */
320 if (rm == 4) { /* process SIB */
321 scale = (sib >> 6) & 03;
322 index = (sib >> 3) & 07;
325 op->scale = 1 << scale;
327 if (type == EA_XMMVSIB)
328 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
329 else if (type == EA_YMMVSIB)
330 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
331 else if (type == EA_ZMMVSIB)
332 op->indexreg = nasm_rd_zmmreg[index | ((rex & REX_X) ? 8 : 0)];
333 else if (index == 4 && !(rex & REX_X))
334 op->indexreg = -1; /* ESP/RSP cannot be an index */
336 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
338 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
340 if (base == 5 && mod == 0) {
342 mod = 2; /* Fake disp32 */
344 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
346 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
350 } else if (type != EA_SCALAR) {
351 /* Can't have VSIB without SIB */
357 op->segment |= SEG_NODISP;
360 op->segment |= SEG_DISP8;
361 op->offset = gets8(data);
365 op->segment |= SEG_DISP32;
366 op->offset = gets32(data);
375 * Determine whether the instruction template in t corresponds to the data
376 * stream in data. Return the number of bytes matched if so.
378 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
380 static int matches(const struct itemplate *t, uint8_t *data,
381 const struct prefix_info *prefix, int segsize, insn *ins)
383 uint8_t *r = (uint8_t *)(t->code);
384 uint8_t *origdata = data;
385 bool a_used = false, o_used = false;
386 enum prefixes drep = 0;
387 enum prefixes dwait = 0;
388 uint8_t lock = prefix->lock;
389 int osize = prefix->osize;
390 int asize = prefix->asize;
393 struct operand *opx, *opy;
396 int regmask = (segsize == 64) ? 15 : 7;
397 enum ea_type eat = EA_SCALAR;
399 for (i = 0; i < MAX_OPERANDS; i++) {
400 ins->oprs[i].segment = ins->oprs[i].disp_size =
401 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
404 ins->rex = prefix->rex;
405 memset(ins->prefixes, 0, sizeof ins->prefixes);
407 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
410 if (prefix->rep == 0xF2)
412 else if (prefix->rep == 0xF3)
415 dwait = prefix->wait ? P_WAIT : 0;
417 while ((c = *r++) != 0) {
418 op1 = (c & 3) + ((opex & 1) << 2);
419 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
420 opx = &ins->oprs[op1];
421 opy = &ins->oprs[op2];
442 int t = *r++, d = *data++;
443 if (d < t || d > t + 7)
446 opx->basereg = (d-t)+
447 (ins->rex & REX_B ? 8 : 0);
448 opx->segment |= SEG_RMREG;
454 opx->offset = (int8_t)*data++;
455 opx->segment |= SEG_SIGNED;
459 opx->offset = *data++;
463 opx->offset = *data++;
467 opx->offset = getu16(data);
473 opx->offset = getu32(data);
476 opx->offset = getu16(data);
479 if (segsize != asize)
480 opx->disp_size = asize;
484 opx->offset = getu32(data);
489 opx->offset = gets32(data);
496 opx->offset = getu16(data);
502 opx->offset = getu32(data);
508 opx->offset = getu64(data);
516 opx->offset = gets8(data++);
517 opx->segment |= SEG_RELATIVE;
521 opx->offset = getu64(data);
526 opx->offset = gets16(data);
528 opx->segment |= SEG_RELATIVE;
529 opx->segment &= ~SEG_32BIT;
532 case4(064): /* rel */
533 opx->segment |= SEG_RELATIVE;
534 /* In long mode rel is always 32 bits, sign extended. */
535 if (segsize == 64 || osize == 32) {
536 opx->offset = gets32(data);
539 opx->segment |= SEG_32BIT;
540 opx->type = (opx->type & ~SIZE_MASK)
541 | (segsize == 64 ? BITS64 : BITS32);
543 opx->offset = gets16(data);
545 opx->segment &= ~SEG_32BIT;
546 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
551 opx->offset = gets32(data);
553 opx->segment |= SEG_32BIT | SEG_RELATIVE;
562 opx->segment |= SEG_RMREG;
563 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
566 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
572 uint8_t ximm = *data++;
574 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
575 ins->oprs[c >> 3].segment |= SEG_RMREG;
576 ins->oprs[c & 7].offset = ximm & 15;
582 uint8_t ximm = *data++;
588 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
589 ins->oprs[c >> 4].segment |= SEG_RMREG;
595 uint8_t ximm = *data++;
597 opx->basereg = (ximm >> 4) & regmask;
598 opx->segment |= SEG_RMREG;
612 if (((modrm >> 3) & 07) != (c & 07))
613 return false; /* spare field doesn't match up */
614 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
627 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
630 if ((vexm & 0x1f) != prefix->vex_m)
633 switch (vexwlp & 060) {
635 if (prefix->rex & REX_W)
639 if (!(prefix->rex & REX_W))
643 case 040: /* VEX.W is a don't care */
650 /* The 010 bit of vexwlp is set if VEX.L is ignored */
651 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
655 if (prefix->vex_v != 0)
658 opx->segment |= SEG_RMREG;
659 opx->basereg = prefix->vex_v;
666 if (prefix->rep == 0xF3)
671 if (prefix->rep == 0xF2)
673 else if (prefix->rep == 0xF3)
678 if (prefix->lock == 0xF0) {
679 if (prefix->rep == 0xF2)
681 else if (prefix->rep == 0xF3)
701 if (asize != segsize)
715 if (prefix->rex & REX_B)
720 if (prefix->rex & REX_X)
725 if (prefix->rex & REX_R)
730 if (prefix->rex & REX_W)
749 if (osize != (segsize == 16) ? 16 : 32)
756 ins->rex |= REX_W; /* 64-bit only instruction */
773 int t = *r++, d = *data++;
774 if (d < t || d > t + 15)
777 ins->condition = d - t;
782 if (prefix->rep == 0xF3)
792 if (prefix->rep != 0xF2)
798 if (prefix->rep != 0xF3)
823 if (prefix->wait != 0x9B)
829 if (prefix->osp || prefix->rep)
834 if (!prefix->osp || prefix->rep)
866 if (prefix->rep == 0xF2)
883 return false; /* Unknown code */
887 if (!vex_ok && (ins->rex & REX_V))
890 /* REX cannot be combined with VEX */
891 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
895 * Check for unused rep or a/o prefixes.
897 for (i = 0; i < t->operands; i++) {
898 if (ins->oprs[i].segment != SEG_RMREG)
903 if (ins->prefixes[PPS_LOCK])
905 ins->prefixes[PPS_LOCK] = P_LOCK;
908 if (ins->prefixes[PPS_REP])
910 ins->prefixes[PPS_REP] = drep;
912 ins->prefixes[PPS_WAIT] = dwait;
914 if (osize != ((segsize == 16) ? 16 : 32)) {
915 enum prefixes pfx = 0;
929 if (ins->prefixes[PPS_OSIZE])
931 ins->prefixes[PPS_OSIZE] = pfx;
934 if (!a_used && asize != segsize) {
935 if (ins->prefixes[PPS_ASIZE])
937 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
940 /* Fix: check for redundant REX prefixes */
942 return data - origdata;
945 /* Condition names for disassembly, sorted by x86 code */
946 static const char * const condition_name[16] = {
947 "o", "no", "c", "nc", "z", "nz", "na", "a",
948 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
951 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
952 int32_t offset, int autosync, iflags_t prefer)
954 const struct itemplate * const *p, * const *best_p;
955 const struct disasm_index *ix;
957 int length, best_length = 0;
959 int i, slen, colon, n;
963 iflags_t goodness, best, flags;
965 struct prefix_info prefix;
968 memset(&ins, 0, sizeof ins);
973 memset(&prefix, 0, sizeof prefix);
974 prefix.asize = segsize;
975 prefix.osize = (segsize == 64) ? 32 : segsize;
982 while (!end_prefix) {
986 prefix.rep = *data++;
990 prefix.wait = *data++;
994 prefix.lock = *data++;
998 segover = "cs", prefix.seg = *data++;
1001 segover = "ss", prefix.seg = *data++;
1004 segover = "ds", prefix.seg = *data++;
1007 segover = "es", prefix.seg = *data++;
1010 segover = "fs", prefix.seg = *data++;
1013 segover = "gs", prefix.seg = *data++;
1017 prefix.osize = (segsize == 16) ? 32 : 16;
1018 prefix.osp = *data++;
1021 prefix.asize = (segsize == 32) ? 16 : 32;
1022 prefix.asp = *data++;
1027 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1028 prefix.vex[0] = *data++;
1029 prefix.vex[1] = *data++;
1032 prefix.vex_c = RV_VEX;
1034 if (prefix.vex[0] == 0xc4) {
1035 prefix.vex[2] = *data++;
1036 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1037 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1038 prefix.vex_m = prefix.vex[1] & 0x1f;
1039 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1040 prefix.vex_lp = prefix.vex[2] & 7;
1042 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1044 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1045 prefix.vex_lp = prefix.vex[1] & 7;
1048 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1054 if ((data[1] & 030) != 0 &&
1055 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1056 prefix.vex[0] = *data++;
1057 prefix.vex[1] = *data++;
1058 prefix.vex[2] = *data++;
1061 prefix.vex_c = RV_XOP;
1063 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1064 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1065 prefix.vex_m = prefix.vex[1] & 0x1f;
1066 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1067 prefix.vex_lp = prefix.vex[2] & 7;
1069 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1090 if (segsize == 64) {
1091 prefix.rex = *data++;
1092 if (prefix.rex & REX_W)
1104 best = -1; /* Worst possible */
1106 best_pref = INT_MAX;
1109 return 0; /* No instruction table at all... */
1113 while (ix->n == -1) {
1114 ix = (const struct disasm_index *)ix->p + *dp++;
1117 p = (const struct itemplate * const *)ix->p;
1118 for (n = ix->n; n; n--, p++) {
1119 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1122 * Final check to make sure the types of r/m match up.
1123 * XXX: Need to make sure this is actually correct.
1125 for (i = 0; i < (*p)->operands; i++) {
1127 /* If it's a mem-only EA but we have a
1129 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1130 is_class(MEMORY, (*p)->opd[i])) ||
1131 /* If it's a reg-only EA but we have a memory
1133 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1134 !(REG_EA & ~(*p)->opd[i]) &&
1135 !((*p)->opd[i] & REG_SMASK)) ||
1136 /* Register type mismatch (eg FS vs REG_DESS):
1138 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1139 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1140 !whichreg((*p)->opd[i],
1141 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1149 * Note: we always prefer instructions which incorporate
1150 * prefixes in the instructions themselves. This is to allow
1151 * e.g. PAUSE to be preferred to REP NOP, and deal with
1152 * MMX/SSE instructions where prefixes are used to select
1153 * between MMX and SSE register sets or outright opcode
1158 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1160 for (i = 0; i < MAXPREFIX; i++)
1161 if (tmp_ins.prefixes[i])
1163 if (nprefix < best_pref ||
1164 (nprefix == best_pref && goodness < best)) {
1165 /* This is the best one found so far */
1168 best_pref = nprefix;
1169 best_length = length;
1177 return 0; /* no instruction was matched */
1179 /* Pick the best match */
1181 length = best_length;
1182 flags = (*p)->flags;
1186 /* TODO: snprintf returns the value that the string would have if
1187 * the buffer were long enough, and not the actual length of
1188 * the returned string, so each instance of using the return
1189 * value of snprintf should actually be checked to assure that
1190 * the return value is "sane." Maybe a macro wrapper could
1191 * be used for that purpose.
1193 for (i = 0; i < MAXPREFIX; i++) {
1194 const char *prefix = prefix_name(ins.prefixes[i]);
1196 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1200 if (i >= FIRST_COND_OPCODE)
1201 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1202 nasm_insn_names[i], condition_name[ins.condition]);
1204 slen += snprintf(output + slen, outbufsize - slen, "%s",
1205 nasm_insn_names[i]);
1208 length += data - origdata; /* fix up for prefixes */
1209 for (i = 0; i < (*p)->operands; i++) {
1210 opflags_t t = (*p)->opd[i];
1211 const operand *o = &ins.oprs[i];
1214 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1217 if (o->segment & SEG_RELATIVE) {
1218 offs += offset + length;
1220 * sort out wraparound
1222 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1224 else if (segsize != 64)
1228 * add sync marker, if autosync is on
1239 if ((t & (REGISTER | FPUREG)) ||
1240 (o->segment & SEG_RMREG)) {
1242 reg = whichreg(t, o->basereg, ins.rex);
1244 slen += snprintf(output + slen, outbufsize - slen, "to ");
1245 slen += snprintf(output + slen, outbufsize - slen, "%s",
1246 nasm_reg_names[reg-EXPR_REG_START]);
1247 } else if (!(UNITY & ~t)) {
1248 output[slen++] = '1';
1249 } else if (t & IMMEDIATE) {
1252 snprintf(output + slen, outbufsize - slen, "byte ");
1253 if (o->segment & SEG_SIGNED) {
1256 output[slen++] = '-';
1258 output[slen++] = '+';
1260 } else if (t & BITS16) {
1262 snprintf(output + slen, outbufsize - slen, "word ");
1263 } else if (t & BITS32) {
1265 snprintf(output + slen, outbufsize - slen, "dword ");
1266 } else if (t & BITS64) {
1268 snprintf(output + slen, outbufsize - slen, "qword ");
1269 } else if (t & NEAR) {
1271 snprintf(output + slen, outbufsize - slen, "near ");
1272 } else if (t & SHORT) {
1274 snprintf(output + slen, outbufsize - slen, "short ");
1277 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1279 } else if (!(MEM_OFFS & ~t)) {
1281 snprintf(output + slen, outbufsize - slen,
1282 "[%s%s%s0x%"PRIx64"]",
1283 (segover ? segover : ""),
1284 (segover ? ":" : ""),
1285 (o->disp_size == 64 ? "qword " :
1286 o->disp_size == 32 ? "dword " :
1287 o->disp_size == 16 ? "word " : ""), offs);
1289 } else if (is_class(REGMEM, t)) {
1290 int started = false;
1293 snprintf(output + slen, outbufsize - slen, "byte ");
1296 snprintf(output + slen, outbufsize - slen, "word ");
1299 snprintf(output + slen, outbufsize - slen, "dword ");
1302 snprintf(output + slen, outbufsize - slen, "qword ");
1305 snprintf(output + slen, outbufsize - slen, "tword ");
1308 snprintf(output + slen, outbufsize - slen, "oword ");
1311 snprintf(output + slen, outbufsize - slen, "yword ");
1314 snprintf(output + slen, outbufsize - slen, "zword ");
1316 slen += snprintf(output + slen, outbufsize - slen, "far ");
1319 snprintf(output + slen, outbufsize - slen, "near ");
1320 output[slen++] = '[';
1322 slen += snprintf(output + slen, outbufsize - slen, "%s",
1323 (o->disp_size == 64 ? "qword " :
1324 o->disp_size == 32 ? "dword " :
1325 o->disp_size == 16 ? "word " :
1327 if (o->eaflags & EAF_REL)
1328 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1331 snprintf(output + slen, outbufsize - slen, "%s:",
1335 if (o->basereg != -1) {
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1340 if (o->indexreg != -1 && !(flags & IF_MIB)) {
1342 output[slen++] = '+';
1343 slen += snprintf(output + slen, outbufsize - slen, "%s",
1344 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1347 snprintf(output + slen, outbufsize - slen, "*%d",
1353 if (o->segment & SEG_DISP8) {
1355 uint8_t offset = offs;
1356 if ((int8_t)offset < 0) {
1363 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1365 } else if (o->segment & SEG_DISP16) {
1367 uint16_t offset = offs;
1368 if ((int16_t)offset < 0 && started) {
1372 prefix = started ? "+" : "";
1375 snprintf(output + slen, outbufsize - slen,
1376 "%s0x%"PRIx16"", prefix, offset);
1377 } else if (o->segment & SEG_DISP32) {
1378 if (prefix.asize == 64) {
1380 uint64_t offset = (int64_t)(int32_t)offs;
1381 if ((int32_t)offs < 0 && started) {
1385 prefix = started ? "+" : "";
1388 snprintf(output + slen, outbufsize - slen,
1389 "%s0x%"PRIx64"", prefix, offset);
1392 uint32_t offset = offs;
1393 if ((int32_t) offset < 0 && started) {
1397 prefix = started ? "+" : "";
1400 snprintf(output + slen, outbufsize - slen,
1401 "%s0x%"PRIx32"", prefix, offset);
1405 if (o->indexreg != -1 && (flags & IF_MIB)) {
1406 output[slen++] = ',';
1407 slen += snprintf(output + slen, outbufsize - slen, "%s",
1408 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1411 snprintf(output + slen, outbufsize - slen, "*%d",
1416 output[slen++] = ']';
1419 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1423 output[slen] = '\0';
1424 if (segover) { /* unused segment override */
1426 int count = slen + 1;
1428 p[count + 3] = p[count];
1429 strncpy(output, segover, 2);
1436 * This is called when we don't have a complete instruction. If it
1437 * is a standalone *single-byte* prefix show it as such, otherwise
1438 * print it as a literal.
1440 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1442 uint8_t byte = *data;
1443 const char *str = NULL;
1477 str = (segsize == 16) ? "o32" : "o16";
1480 str = (segsize == 32) ? "a16" : "a32";
1498 if (segsize == 64) {
1499 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1500 (byte == REX_P) ? "" : ".",
1501 (byte & REX_W) ? "w" : "",
1502 (byte & REX_R) ? "r" : "",
1503 (byte & REX_X) ? "x" : "",
1504 (byte & REX_B) ? "b" : "");
1507 /* else fall through */
1509 snprintf(output, outbufsize, "db 0x%02x", byte);
1514 snprintf(output, outbufsize, "%s", str);