1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
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16 // be used to endorse or promote products derived from this software without
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_X87_ASSEMBLER_X87_H_
38 #define V8_X87_ASSEMBLER_X87_H_
42 #include "src/assembler.h"
43 #include "src/compiler.h"
44 #include "src/isolate.h"
51 // 1) We would prefer to use an enum, but enum values are assignment-
52 // compatible with int, which has caused code-generation bugs.
54 // 2) We would prefer to use a class instead of a struct but we don't like
55 // the register initialization to depend on the particular initialization
56 // order (which appears to be different on OS X, Linux, and Windows for the
57 // installed versions of C++ we tried). Using a struct permits C-style
58 // "initialization". Also, the Register objects cannot be const as this
59 // forces initialization stubs in MSVC, making us dependent on initialization
62 // 3) By not using an enum, we are possibly preventing the compiler from
63 // doing certain constant folds, which may significantly reduce the
64 // code generated for some assembly instructions (because they boil down
65 // to a few constants). If this is a problem, we could change the code
66 // such that we use an enum in optimized mode, and the struct in debug
67 // mode. This way we get the compile-time error checking in debug mode
68 // and best performance in optimized code.
71 static const int kMaxNumAllocatableRegisters = 6;
72 static int NumAllocatableRegisters() {
73 return kMaxNumAllocatableRegisters;
75 static const int kNumRegisters = 8;
77 static inline const char* AllocationIndexToString(int index);
79 static inline int ToAllocationIndex(Register reg);
81 static inline Register FromAllocationIndex(int index);
83 static Register from_code(int code) {
85 DCHECK(code < kNumRegisters);
86 Register r = { code };
89 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
90 bool is(Register reg) const { return code_ == reg.code_; }
91 // eax, ebx, ecx and edx are byte registers, the rest are not.
92 bool is_byte_register() const { return code_ <= 3; }
102 // Unfortunately we can't make this private in a struct.
106 const int kRegister_eax_Code = 0;
107 const int kRegister_ecx_Code = 1;
108 const int kRegister_edx_Code = 2;
109 const int kRegister_ebx_Code = 3;
110 const int kRegister_esp_Code = 4;
111 const int kRegister_ebp_Code = 5;
112 const int kRegister_esi_Code = 6;
113 const int kRegister_edi_Code = 7;
114 const int kRegister_no_reg_Code = -1;
116 const Register eax = { kRegister_eax_Code };
117 const Register ecx = { kRegister_ecx_Code };
118 const Register edx = { kRegister_edx_Code };
119 const Register ebx = { kRegister_ebx_Code };
120 const Register esp = { kRegister_esp_Code };
121 const Register ebp = { kRegister_ebp_Code };
122 const Register esi = { kRegister_esi_Code };
123 const Register edi = { kRegister_edi_Code };
124 const Register no_reg = { kRegister_no_reg_Code };
127 inline const char* Register::AllocationIndexToString(int index) {
128 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
129 // This is the mapping of allocation indices to registers.
130 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
131 return kNames[index];
135 inline int Register::ToAllocationIndex(Register reg) {
136 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
137 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
141 inline Register Register::FromAllocationIndex(int index) {
142 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
143 return (index >= 4) ? from_code(index + 2) : from_code(index);
148 static const int kMaxNumAllocatableRegisters = 6;
149 static const int kMaxNumRegisters = 8;
150 static int NumAllocatableRegisters() {
151 return kMaxNumAllocatableRegisters;
155 // TODO(turbofan): Proper support for float32.
156 static int NumAllocatableAliasedRegisters() {
157 return NumAllocatableRegisters();
161 static int ToAllocationIndex(X87Register reg) {
165 static const char* AllocationIndexToString(int index) {
166 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
167 const char* const names[] = {
168 "stX_0", "stX_1", "stX_2", "stX_3", "stX_4",
169 "stX_5", "stX_6", "stX_7"
174 static X87Register FromAllocationIndex(int index) {
175 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
177 result.code_ = index;
181 bool is_valid() const {
182 return 0 <= code_ && code_ < kMaxNumRegisters;
190 bool is(X87Register reg) const {
191 return code_ == reg.code_;
198 typedef X87Register DoubleRegister;
201 const X87Register stX_0 = { 0 };
202 const X87Register stX_1 = { 1 };
203 const X87Register stX_2 = { 2 };
204 const X87Register stX_3 = { 3 };
205 const X87Register stX_4 = { 4 };
206 const X87Register stX_5 = { 5 };
207 const X87Register stX_6 = { 6 };
208 const X87Register stX_7 = { 7 };
212 // any value < 0 is considered no_condition
234 not_carry = above_equal,
236 not_zero = not_equal,
242 // Returns the equivalent of !cc.
243 // Negation of the default no_condition (-1) results in a non-default
244 // no_condition value (-2). As long as tests for no_condition check
245 // for condition < 0, this will work as expected.
246 inline Condition NegateCondition(Condition cc) {
247 return static_cast<Condition>(cc ^ 1);
251 // Commute a condition such that {a cond b == b cond' a}.
252 inline Condition CommuteCondition(Condition cc) {
269 return greater_equal;
276 // -----------------------------------------------------------------------------
277 // Machine instruction Immediates
279 class Immediate BASE_EMBEDDED {
281 inline explicit Immediate(int x);
282 inline explicit Immediate(const ExternalReference& ext);
283 inline explicit Immediate(Handle<Object> handle);
284 inline explicit Immediate(Smi* value);
285 inline explicit Immediate(Address addr);
287 static Immediate CodeRelativeOffset(Label* label) {
288 return Immediate(label);
291 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
292 bool is_int8() const {
293 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
295 bool is_int16() const {
296 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
300 inline explicit Immediate(Label* value);
303 RelocInfo::Mode rmode_;
305 friend class Operand;
306 friend class Assembler;
307 friend class MacroAssembler;
311 // -----------------------------------------------------------------------------
312 // Machine instruction Operands
319 times_int_size = times_4,
320 times_half_pointer_size = times_2,
321 times_pointer_size = times_4,
322 times_twice_pointer_size = times_8
326 class Operand BASE_EMBEDDED {
329 INLINE(explicit Operand(Register reg));
332 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
335 INLINE(explicit Operand(Immediate imm));
338 explicit Operand(Register base, int32_t disp,
339 RelocInfo::Mode rmode = RelocInfo::NONE32);
341 // [base + index*scale + disp/r]
342 explicit Operand(Register base,
346 RelocInfo::Mode rmode = RelocInfo::NONE32);
348 // [index*scale + disp/r]
349 explicit Operand(Register index,
352 RelocInfo::Mode rmode = RelocInfo::NONE32);
354 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) {
355 return Operand(index, scale, reinterpret_cast<int32_t>(table),
356 RelocInfo::INTERNAL_REFERENCE);
359 static Operand StaticVariable(const ExternalReference& ext) {
360 return Operand(reinterpret_cast<int32_t>(ext.address()),
361 RelocInfo::EXTERNAL_REFERENCE);
364 static Operand StaticArray(Register index,
366 const ExternalReference& arr) {
367 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
368 RelocInfo::EXTERNAL_REFERENCE);
371 static Operand ForCell(Handle<Cell> cell) {
372 AllowDeferredHandleDereference embedding_raw_address;
373 return Operand(reinterpret_cast<int32_t>(cell.location()),
377 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
378 return Operand(base, imm.x_, imm.rmode_);
381 // Returns true if this Operand is a wrapper for the specified register.
382 bool is_reg(Register reg) const;
384 // Returns true if this Operand is a wrapper for one register.
385 bool is_reg_only() const;
387 // Asserts that this Operand is a wrapper for one register and returns the
389 Register reg() const;
392 // Set the ModRM byte without an encoded 'reg' register. The
393 // register is encoded later as part of the emit_operand operation.
394 inline void set_modrm(int mod, Register rm);
396 inline void set_sib(ScaleFactor scale, Register index, Register base);
397 inline void set_disp8(int8_t disp);
398 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
401 // The number of bytes in buf_.
403 // Only valid if len_ > 4.
404 RelocInfo::Mode rmode_;
406 friend class Assembler;
407 friend class MacroAssembler;
411 // -----------------------------------------------------------------------------
412 // A Displacement describes the 32bit immediate field of an instruction which
413 // may be used together with a Label in order to refer to a yet unknown code
414 // position. Displacements stored in the instruction stream are used to describe
415 // the instruction and to chain a list of instructions using the same Label.
416 // A Displacement contains 2 different fields:
418 // next field: position of next displacement in the chain (0 = end of list)
419 // type field: instruction type
421 // A next value of null (0) indicates the end of a chain (note that there can
422 // be no displacement at position zero, because there is always at least one
423 // instruction byte before the displacement).
425 // Displacement _data field layout
427 // |31.....2|1......0|
430 class Displacement BASE_EMBEDDED {
432 enum Type { UNCONDITIONAL_JUMP, CODE_RELATIVE, OTHER, CODE_ABSOLUTE };
434 int data() const { return data_; }
435 Type type() const { return TypeField::decode(data_); }
436 void next(Label* L) const {
437 int n = NextField::decode(data_);
438 n > 0 ? L->link_to(n) : L->Unuse();
440 void link_to(Label* L) { init(L, type()); }
442 explicit Displacement(int data) { data_ = data; }
444 Displacement(Label* L, Type type) { init(L, type); }
447 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
448 NextField::decode(data_));
454 class TypeField: public BitField<Type, 0, 2> {};
455 class NextField: public BitField<int, 2, 32-2> {};
457 void init(Label* L, Type type);
461 class Assembler : public AssemblerBase {
463 // We check before assembling an instruction that there is sufficient
464 // space to write an instruction and its relocation information.
465 // The relocation writer's position must be kGap bytes above the end of
466 // the generated instructions. This leaves enough space for the
467 // longest possible ia32 instruction, 15 bytes, and the longest possible
468 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
469 // (There is a 15 byte limit on ia32 instruction length that rules out some
470 // otherwise valid instructions.)
471 // This allows for a single, fast space check per instruction.
472 static const int kGap = 32;
475 // Create an assembler. Instructions and relocation information are emitted
476 // into a buffer, with the instructions starting from the beginning and the
477 // relocation information starting from the end of the buffer. See CodeDesc
478 // for a detailed comment on the layout (globals.h).
480 // If the provided buffer is NULL, the assembler allocates and grows its own
481 // buffer, and buffer_size determines the initial buffer size. The buffer is
482 // owned by the assembler and deallocated upon destruction of the assembler.
484 // If the provided buffer is not NULL, the assembler uses the provided buffer
485 // for code generation and assumes its size to be buffer_size. If the buffer
486 // is too small, a fatal error occurs. No deallocation of the buffer is done
487 // upon destruction of the assembler.
488 // TODO(vitalyr): the assembler does not need an isolate.
489 Assembler(Isolate* isolate, void* buffer, int buffer_size);
490 virtual ~Assembler() { }
492 // GetCode emits any pending (non-emitted) code and fills the descriptor
493 // desc. GetCode() is idempotent; it returns the same result if no other
494 // Assembler functions are invoked in between GetCode() calls.
495 void GetCode(CodeDesc* desc);
497 // Read/Modify the code target in the branch/call instruction at pc.
498 inline static Address target_address_at(Address pc,
499 ConstantPoolArray* constant_pool);
500 inline static void set_target_address_at(Address pc,
501 ConstantPoolArray* constant_pool,
503 ICacheFlushMode icache_flush_mode =
504 FLUSH_ICACHE_IF_NEEDED);
505 static inline Address target_address_at(Address pc, Code* code) {
506 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
507 return target_address_at(pc, constant_pool);
509 static inline void set_target_address_at(Address pc,
512 ICacheFlushMode icache_flush_mode =
513 FLUSH_ICACHE_IF_NEEDED) {
514 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
515 set_target_address_at(pc, constant_pool, target);
518 // Return the code target address at a call site from the return address
519 // of that call in the instruction stream.
520 inline static Address target_address_from_return_address(Address pc);
522 // Return the code target address of the patch debug break slot
523 inline static Address break_address_from_return_address(Address pc);
525 // This sets the branch destination (which is in the instruction on x86).
526 // This is for calls and branches within generated code.
527 inline static void deserialization_set_special_target_at(
528 Address instruction_payload, Code* code, Address target) {
529 set_target_address_at(instruction_payload, code, target);
532 // This sets the internal reference at the pc.
533 inline static void deserialization_set_target_internal_reference_at(
534 Address pc, Address target,
535 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
537 static const int kSpecialTargetSize = kPointerSize;
539 // Distance between the address of the code target in the call instruction
540 // and the return address
541 static const int kCallTargetAddressOffset = kPointerSize;
542 // Distance between start of patched return sequence and the emitted address
544 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
546 // Distance between start of patched debug break slot and the emitted address
548 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
550 static const int kCallInstructionLength = 5;
551 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
552 static const int kJSReturnSequenceLength = 6;
554 // The debug break slot must be able to contain a call instruction.
555 static const int kDebugBreakSlotLength = kCallInstructionLength;
557 // One byte opcode for test al, 0xXX.
558 static const byte kTestAlByte = 0xA8;
559 // One byte opcode for nop.
560 static const byte kNopByte = 0x90;
562 // One byte opcode for a short unconditional jump.
563 static const byte kJmpShortOpcode = 0xEB;
564 // One byte prefix for a short conditional jump.
565 static const byte kJccShortPrefix = 0x70;
566 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
567 static const byte kJcShortOpcode = kJccShortPrefix | carry;
568 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
569 static const byte kJzShortOpcode = kJccShortPrefix | zero;
572 // ---------------------------------------------------------------------------
575 // - function names correspond one-to-one to ia32 instruction mnemonics
576 // - unless specified otherwise, instructions operate on 32bit operands
577 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
578 // - instructions on 16bit (word) operands/registers have a trailing '_w'
579 // - naming conflicts with C++ keywords are resolved via a trailing '_'
581 // NOTE ON INTERFACE: Currently, the interface is not very consistent
582 // in the sense that some operations (e.g. mov()) can be called in more
583 // the one way to generate the same instruction: The Register argument
584 // can in some cases be replaced with an Operand(Register) argument.
585 // This should be cleaned up and made more orthogonal. The questions
586 // is: should we always use Operands instead of Registers where an
587 // Operand is possible, or should we have a Register (overloaded) form
588 // instead? We must be careful to make sure that the selected instruction
589 // is obvious from the parameters to avoid hard-to-find code generation
592 // Insert the smallest number of nop instructions
593 // possible to align the pc offset to a multiple
594 // of m. m must be a power of 2.
596 void Nop(int bytes = 1);
597 // Aligns code to something that's optimal for a jump target for the platform.
598 void CodeTargetAlign();
607 void push(const Immediate& x);
608 void push_imm32(int32_t imm32);
609 void push(Register src);
610 void push(const Operand& src);
612 void pop(Register dst);
613 void pop(const Operand& dst);
615 void enter(const Immediate& size);
619 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
620 void mov_b(Register dst, const Operand& src);
621 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
622 void mov_b(const Operand& dst, int8_t imm8);
623 void mov_b(const Operand& dst, Register src);
625 void mov_w(Register dst, const Operand& src);
626 void mov_w(const Operand& dst, Register src);
627 void mov_w(const Operand& dst, int16_t imm16);
629 void mov(Register dst, int32_t imm32);
630 void mov(Register dst, const Immediate& x);
631 void mov(Register dst, Handle<Object> handle);
632 void mov(Register dst, const Operand& src);
633 void mov(Register dst, Register src);
634 void mov(const Operand& dst, const Immediate& x);
635 void mov(const Operand& dst, Handle<Object> handle);
636 void mov(const Operand& dst, Register src);
638 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
639 void movsx_b(Register dst, const Operand& src);
641 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
642 void movsx_w(Register dst, const Operand& src);
644 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
645 void movzx_b(Register dst, const Operand& src);
647 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
648 void movzx_w(Register dst, const Operand& src);
653 // Repetitive string instructions.
659 void xchg(Register dst, Register src);
660 void xchg(Register dst, const Operand& src);
663 void adc(Register dst, int32_t imm32);
664 void adc(Register dst, const Operand& src);
666 void add(Register dst, Register src) { add(dst, Operand(src)); }
667 void add(Register dst, const Operand& src);
668 void add(const Operand& dst, Register src);
669 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
670 void add(const Operand& dst, const Immediate& x);
672 void and_(Register dst, int32_t imm32);
673 void and_(Register dst, const Immediate& x);
674 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
675 void and_(Register dst, const Operand& src);
676 void and_(const Operand& dst, Register src);
677 void and_(const Operand& dst, const Immediate& x);
679 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
680 void cmpb(const Operand& op, int8_t imm8);
681 void cmpb(Register reg, const Operand& op);
682 void cmpb(const Operand& op, Register reg);
683 void cmpb_al(const Operand& op);
684 void cmpw_ax(const Operand& op);
685 void cmpw(const Operand& op, Immediate imm16);
686 void cmp(Register reg, int32_t imm32);
687 void cmp(Register reg, Handle<Object> handle);
688 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
689 void cmp(Register reg, const Operand& op);
690 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
691 void cmp(const Operand& op, const Immediate& imm);
692 void cmp(const Operand& op, Handle<Object> handle);
694 void dec_b(Register dst);
695 void dec_b(const Operand& dst);
697 void dec(Register dst);
698 void dec(const Operand& dst);
702 void idiv(Register src) { idiv(Operand(src)); }
703 void idiv(const Operand& src);
704 void div(Register src) { div(Operand(src)); }
705 void div(const Operand& src);
707 // Signed multiply instructions.
708 void imul(Register src); // edx:eax = eax * src.
709 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
710 void imul(Register dst, const Operand& src); // dst = dst * src.
711 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
712 void imul(Register dst, const Operand& src, int32_t imm32);
714 void inc(Register dst);
715 void inc(const Operand& dst);
717 void lea(Register dst, const Operand& src);
719 // Unsigned multiply instruction.
720 void mul(Register src); // edx:eax = eax * reg.
722 void neg(Register dst);
723 void neg(const Operand& dst);
725 void not_(Register dst);
726 void not_(const Operand& dst);
728 void or_(Register dst, int32_t imm32);
729 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
730 void or_(Register dst, const Operand& src);
731 void or_(const Operand& dst, Register src);
732 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
733 void or_(const Operand& dst, const Immediate& x);
735 void rcl(Register dst, uint8_t imm8);
736 void rcr(Register dst, uint8_t imm8);
738 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
739 void ror(const Operand& dst, uint8_t imm8);
740 void ror_cl(Register dst) { ror_cl(Operand(dst)); }
741 void ror_cl(const Operand& dst);
743 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
744 void sar(const Operand& dst, uint8_t imm8);
745 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
746 void sar_cl(const Operand& dst);
748 void sbb(Register dst, const Operand& src);
750 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
751 void shld(Register dst, const Operand& src);
753 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
754 void shl(const Operand& dst, uint8_t imm8);
755 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
756 void shl_cl(const Operand& dst);
758 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
759 void shrd(Register dst, const Operand& src);
761 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
762 void shr(const Operand& dst, uint8_t imm8);
763 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
764 void shr_cl(const Operand& dst);
766 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
767 void sub(const Operand& dst, const Immediate& x);
768 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
769 void sub(Register dst, const Operand& src);
770 void sub(const Operand& dst, Register src);
772 void test(Register reg, const Immediate& imm);
773 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
774 void test(Register reg, const Operand& op);
775 void test_b(Register reg, const Operand& op);
776 void test(const Operand& op, const Immediate& imm);
777 void test_b(Register reg, uint8_t imm8);
778 void test_b(const Operand& op, uint8_t imm8);
780 void xor_(Register dst, int32_t imm32);
781 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
782 void xor_(Register dst, const Operand& src);
783 void xor_(const Operand& dst, Register src);
784 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
785 void xor_(const Operand& dst, const Immediate& x);
788 void bt(const Operand& dst, Register src);
789 void bts(Register dst, Register src) { bts(Operand(dst), src); }
790 void bts(const Operand& dst, Register src);
791 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
792 void bsr(Register dst, const Operand& src);
801 // Label operations & relative jumps (PPUM Appendix D)
803 // Takes a branch opcode (cc) and a label (L) and generates
804 // either a backward branch or a forward branch and links it
805 // to the label fixup chain. Usage:
807 // Label L; // unbound label
808 // j(cc, &L); // forward branch to unbound label
809 // bind(&L); // bind label to the current pc
810 // j(cc, &L); // backward branch to bound label
811 // bind(&L); // illegal: a label may be bound only once
813 // Note: The same Label can be used for forward and backward branches
814 // but it may be bound only once.
816 void bind(Label* L); // binds an unbound label L to the current code position
820 void call(byte* entry, RelocInfo::Mode rmode);
821 int CallSize(const Operand& adr);
822 void call(Register reg) { call(Operand(reg)); }
823 void call(const Operand& adr);
824 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
825 void call(Handle<Code> code,
826 RelocInfo::Mode rmode,
827 TypeFeedbackId id = TypeFeedbackId::None());
830 // unconditional jump to L
831 void jmp(Label* L, Label::Distance distance = Label::kFar);
832 void jmp(byte* entry, RelocInfo::Mode rmode);
833 void jmp(Register reg) { jmp(Operand(reg)); }
834 void jmp(const Operand& adr);
835 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
840 Label::Distance distance = Label::kFar);
841 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
842 void j(Condition cc, Handle<Code> code);
844 // Floating-point operations
853 void fld_s(const Operand& adr);
854 void fld_d(const Operand& adr);
856 void fstp_s(const Operand& adr);
857 void fst_s(const Operand& adr);
858 void fstp_d(const Operand& adr);
859 void fst_d(const Operand& adr);
861 void fild_s(const Operand& adr);
862 void fild_d(const Operand& adr);
864 void fist_s(const Operand& adr);
866 void fistp_s(const Operand& adr);
867 void fistp_d(const Operand& adr);
869 // The fisttp instructions require SSE3.
870 void fisttp_s(const Operand& adr);
871 void fisttp_d(const Operand& adr);
886 void fadd_d(const Operand& adr);
894 void fisub_s(const Operand& adr);
896 void faddp(int i = 1);
897 void fsubp(int i = 1);
898 void fsubrp(int i = 1);
899 void fmulp(int i = 1);
900 void fdivp(int i = 1);
904 void fxch(int i = 1);
906 void ffree(int i = 0);
916 void fldcw(const Operand& adr);
917 void fnstcw(const Operand& adr);
920 void fnsave(const Operand& adr);
921 void frstor(const Operand& adr);
926 void setcc(Condition cc, Register reg);
930 // TODO(lrn): Need SFENCE for movnt?
932 // Check the code size generated from label to here.
933 int SizeOfCodeGeneratedSince(Label* label) {
934 return pc_offset() - label->pos();
937 // Mark address of the ExitJSFrame code.
938 void RecordJSReturn();
940 // Mark address of a debug break slot.
941 void RecordDebugBreakSlot();
943 // Record a comment relocation entry that can be used by a disassembler.
944 // Use --code-comments to enable.
945 void RecordComment(const char* msg);
947 // Record a deoptimization reason that can be used by a log or cpu profiler.
948 // Use --trace-deopt to enable.
949 void RecordDeoptReason(const int reason, const SourcePosition position);
951 // Writes a single byte or word of data in the code stream. Used for
952 // inline tables, e.g., jump-tables.
953 void db(uint8_t data);
954 void dd(uint32_t data);
955 void dd(Label* label);
957 // Check if there is less than kGap bytes available in the buffer.
958 // If this is the case, we need to grow the buffer before emitting
959 // an instruction or relocation information.
960 inline bool buffer_overflow() const {
961 return pc_ >= reloc_info_writer.pos() - kGap;
964 // Get the number of bytes available in the buffer.
965 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
967 static bool IsNop(Address addr);
969 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
971 int relocation_writer_size() {
972 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
975 // Avoid overflows for displacements etc.
976 static const int kMaximalBufferSize = 512*MB;
978 byte byte_at(int pos) { return buffer_[pos]; }
979 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
981 // Allocate a constant pool of the correct size for the generated code.
982 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
984 // Generate the constant pool for the generated code.
985 void PopulateConstantPool(ConstantPoolArray* constant_pool);
988 byte* addr_at(int pos) { return buffer_ + pos; }
992 uint32_t long_at(int pos) {
993 return *reinterpret_cast<uint32_t*>(addr_at(pos));
995 void long_at_put(int pos, uint32_t x) {
996 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1001 inline void emit(uint32_t x);
1002 inline void emit(Handle<Object> handle);
1003 inline void emit(uint32_t x,
1004 RelocInfo::Mode rmode,
1005 TypeFeedbackId id = TypeFeedbackId::None());
1006 inline void emit(Handle<Code> code,
1007 RelocInfo::Mode rmode,
1008 TypeFeedbackId id = TypeFeedbackId::None());
1009 inline void emit(const Immediate& x);
1010 inline void emit_w(const Immediate& x);
1012 // Emit the code-object-relative offset of the label's position
1013 inline void emit_code_relative_offset(Label* label);
1015 // instruction generation
1016 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1018 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1019 // with a given destination expression and an immediate operand. It attempts
1020 // to use the shortest encoding possible.
1021 // sel specifies the /n in the modrm byte (see the Intel PRM).
1022 void emit_arith(int sel, Operand dst, const Immediate& x);
1024 void emit_operand(Register reg, const Operand& adr);
1026 void emit_label(Label* label);
1028 void emit_farith(int b1, int b2, int i);
1031 void print(Label* L);
1032 void bind_to(Label* L, int pos);
1035 inline Displacement disp_at(Label* L);
1036 inline void disp_at_put(Label* L, Displacement disp);
1037 inline void emit_disp(Label* L, Displacement::Type type);
1038 inline void emit_near_disp(Label* L);
1040 // record reloc info for current pc_
1041 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1043 friend class CodePatcher;
1044 friend class EnsureSpace;
1046 // Internal reference positions, required for (potential) patching in
1047 // GrowBuffer(); contains only those internal references whose labels
1048 // are already bound.
1049 std::deque<int> internal_reference_positions_;
1052 RelocInfoWriter reloc_info_writer;
1054 PositionsRecorder positions_recorder_;
1055 friend class PositionsRecorder;
1059 // Helper class that ensures that there is enough space for generating
1060 // instructions and relocation information. The constructor makes
1061 // sure that there is enough space and (in debug mode) the destructor
1062 // checks that we did not generate too much.
1063 class EnsureSpace BASE_EMBEDDED {
1065 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1066 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1068 space_before_ = assembler_->available_space();
1074 int bytes_generated = space_before_ - assembler_->available_space();
1075 DCHECK(bytes_generated < assembler_->kGap);
1080 Assembler* assembler_;
1086 } } // namespace v8::internal
1088 #endif // V8_X87_ASSEMBLER_X87_H_