1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
39 #if V8_TARGET_ARCH_X87
41 #include "src/base/bits.h"
42 #include "src/base/cpu.h"
43 #include "src/disassembler.h"
44 #include "src/macro-assembler.h"
45 #include "src/serialize.h"
50 // -----------------------------------------------------------------------------
51 // Implementation of CpuFeatures
53 void CpuFeatures::ProbeImpl(bool cross_compile) {
56 // Only use statically determined features for cross compile (snapshot).
57 if (cross_compile) return;
61 void CpuFeatures::PrintTarget() { }
62 void CpuFeatures::PrintFeatures() { }
65 // -----------------------------------------------------------------------------
66 // Implementation of Displacement
68 void Displacement::init(Label* L, Type type) {
69 DCHECK(!L->is_bound());
73 DCHECK(next > 0); // Displacements must be at positions > 0
75 // Ensure that we _never_ overflow the next field.
76 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
77 data_ = NextField::encode(next) | TypeField::encode(type);
81 // -----------------------------------------------------------------------------
82 // Implementation of RelocInfo
85 const int RelocInfo::kApplyMask =
86 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
87 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
88 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
91 bool RelocInfo::IsCodedSpecially() {
92 // The deserializer needs to know whether a pointer is specially coded. Being
93 // specially coded on IA32 means that it is a relative address, as used by
94 // branch instructions. These are also the ones that need changing when a
96 return (1 << rmode_) & kApplyMask;
100 bool RelocInfo::IsInConstantPool() {
105 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
106 // Patch the code at the current address with the supplied instructions.
107 for (int i = 0; i < instruction_count; i++) {
108 *(pc_ + i) = *(instructions + i);
111 // Indicate that code has changed.
112 CpuFeatures::FlushICache(pc_, instruction_count);
116 // Patch the code at the current PC with a call to the target address.
117 // Additional guard int3 instructions can be added if required.
118 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
119 // Call instruction takes up 5 bytes and int3 takes up one byte.
120 static const int kCallCodeSize = 5;
121 int code_size = kCallCodeSize + guard_bytes;
123 // Create a code patcher.
124 CodePatcher patcher(pc_, code_size);
126 // Add a label for checking the size of the code used for returning.
128 Label check_codesize;
129 patcher.masm()->bind(&check_codesize);
133 patcher.masm()->call(target, RelocInfo::NONE32);
135 // Check that the size of the code generated is as expected.
136 DCHECK_EQ(kCallCodeSize,
137 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
139 // Add the requested number of int3 instructions after the call.
140 DCHECK_GE(guard_bytes, 0);
141 for (int i = 0; i < guard_bytes; i++) {
142 patcher.masm()->int3();
147 // -----------------------------------------------------------------------------
148 // Implementation of Operand
150 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
152 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
155 if (base.is(esp)) set_sib(times_1, esp, base);
156 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
159 if (base.is(esp)) set_sib(times_1, esp, base);
164 if (base.is(esp)) set_sib(times_1, esp, base);
165 set_dispr(disp, rmode);
170 Operand::Operand(Register base,
174 RelocInfo::Mode rmode) {
175 DCHECK(!index.is(esp)); // illegal addressing mode
176 // [base + index*scale + disp/r]
177 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
178 // [base + index*scale]
180 set_sib(scale, index, base);
181 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
182 // [base + index*scale + disp8]
184 set_sib(scale, index, base);
187 // [base + index*scale + disp/r]
189 set_sib(scale, index, base);
190 set_dispr(disp, rmode);
195 Operand::Operand(Register index,
198 RelocInfo::Mode rmode) {
199 DCHECK(!index.is(esp)); // illegal addressing mode
200 // [index*scale + disp/r]
202 set_sib(scale, index, ebp);
203 set_dispr(disp, rmode);
207 bool Operand::is_reg(Register reg) const {
208 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
209 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
213 bool Operand::is_reg_only() const {
214 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
218 Register Operand::reg() const {
219 DCHECK(is_reg_only());
220 return Register::from_code(buf_[0] & 0x07);
224 // -----------------------------------------------------------------------------
225 // Implementation of Assembler.
227 // Emit a single byte. Must always be inlined.
232 #ifdef GENERATED_CODE_COVERAGE
233 static void InitCoverageLog();
236 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
237 : AssemblerBase(isolate, buffer, buffer_size),
238 positions_recorder_(this) {
239 // Clear the buffer in debug mode unless it was provided by the
240 // caller in which case we can't be sure it's okay to overwrite
241 // existing code in it; see CodePatcher::CodePatcher(...).
244 memset(buffer_, 0xCC, buffer_size_); // int3
248 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
250 #ifdef GENERATED_CODE_COVERAGE
256 void Assembler::GetCode(CodeDesc* desc) {
257 // Finalize code (at this point overflow() may be true, but the gap ensures
258 // that we are still not overlapping instructions and relocation info).
259 reloc_info_writer.Finish();
260 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
261 // Set up code descriptor.
262 desc->buffer = buffer_;
263 desc->buffer_size = buffer_size_;
264 desc->instr_size = pc_offset();
265 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
270 void Assembler::Align(int m) {
271 DCHECK(base::bits::IsPowerOfTwo32(m));
273 int addr = pc_offset();
274 Nop((m - (addr & mask)) & mask);
278 bool Assembler::IsNop(Address addr) {
280 while (*a == 0x66) a++;
281 if (*a == 0x90) return true;
282 if (a[0] == 0xf && a[1] == 0x1f) return true;
287 void Assembler::Nop(int bytes) {
288 EnsureSpace ensure_space(this);
290 // Older CPUs that do not support SSE2 may not support multibyte NOP
292 for (; bytes > 0; bytes--) {
299 void Assembler::CodeTargetAlign() {
300 Align(16); // Preferred alignment of jump targets on ia32.
304 void Assembler::cpuid() {
305 EnsureSpace ensure_space(this);
311 void Assembler::pushad() {
312 EnsureSpace ensure_space(this);
317 void Assembler::popad() {
318 EnsureSpace ensure_space(this);
323 void Assembler::pushfd() {
324 EnsureSpace ensure_space(this);
329 void Assembler::popfd() {
330 EnsureSpace ensure_space(this);
335 void Assembler::push(const Immediate& x) {
336 EnsureSpace ensure_space(this);
347 void Assembler::push_imm32(int32_t imm32) {
348 EnsureSpace ensure_space(this);
354 void Assembler::push(Register src) {
355 EnsureSpace ensure_space(this);
356 EMIT(0x50 | src.code());
360 void Assembler::push(const Operand& src) {
361 EnsureSpace ensure_space(this);
363 emit_operand(esi, src);
367 void Assembler::pop(Register dst) {
368 DCHECK(reloc_info_writer.last_pc() != NULL);
369 EnsureSpace ensure_space(this);
370 EMIT(0x58 | dst.code());
374 void Assembler::pop(const Operand& dst) {
375 EnsureSpace ensure_space(this);
377 emit_operand(eax, dst);
381 void Assembler::enter(const Immediate& size) {
382 EnsureSpace ensure_space(this);
389 void Assembler::leave() {
390 EnsureSpace ensure_space(this);
395 void Assembler::mov_b(Register dst, const Operand& src) {
396 CHECK(dst.is_byte_register());
397 EnsureSpace ensure_space(this);
399 emit_operand(dst, src);
403 void Assembler::mov_b(const Operand& dst, int8_t imm8) {
404 EnsureSpace ensure_space(this);
406 emit_operand(eax, dst);
411 void Assembler::mov_b(const Operand& dst, Register src) {
412 CHECK(src.is_byte_register());
413 EnsureSpace ensure_space(this);
415 emit_operand(src, dst);
419 void Assembler::mov_w(Register dst, const Operand& src) {
420 EnsureSpace ensure_space(this);
423 emit_operand(dst, src);
427 void Assembler::mov_w(const Operand& dst, Register src) {
428 EnsureSpace ensure_space(this);
431 emit_operand(src, dst);
435 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
436 EnsureSpace ensure_space(this);
439 emit_operand(eax, dst);
440 EMIT(static_cast<int8_t>(imm16 & 0xff));
441 EMIT(static_cast<int8_t>(imm16 >> 8));
445 void Assembler::mov(Register dst, int32_t imm32) {
446 EnsureSpace ensure_space(this);
447 EMIT(0xB8 | dst.code());
452 void Assembler::mov(Register dst, const Immediate& x) {
453 EnsureSpace ensure_space(this);
454 EMIT(0xB8 | dst.code());
459 void Assembler::mov(Register dst, Handle<Object> handle) {
460 EnsureSpace ensure_space(this);
461 EMIT(0xB8 | dst.code());
466 void Assembler::mov(Register dst, const Operand& src) {
467 EnsureSpace ensure_space(this);
469 emit_operand(dst, src);
473 void Assembler::mov(Register dst, Register src) {
474 EnsureSpace ensure_space(this);
476 EMIT(0xC0 | src.code() << 3 | dst.code());
480 void Assembler::mov(const Operand& dst, const Immediate& x) {
481 EnsureSpace ensure_space(this);
483 emit_operand(eax, dst);
488 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
489 EnsureSpace ensure_space(this);
491 emit_operand(eax, dst);
496 void Assembler::mov(const Operand& dst, Register src) {
497 EnsureSpace ensure_space(this);
499 emit_operand(src, dst);
503 void Assembler::movsx_b(Register dst, const Operand& src) {
504 EnsureSpace ensure_space(this);
507 emit_operand(dst, src);
511 void Assembler::movsx_w(Register dst, const Operand& src) {
512 EnsureSpace ensure_space(this);
515 emit_operand(dst, src);
519 void Assembler::movzx_b(Register dst, const Operand& src) {
520 EnsureSpace ensure_space(this);
523 emit_operand(dst, src);
527 void Assembler::movzx_w(Register dst, const Operand& src) {
528 EnsureSpace ensure_space(this);
531 emit_operand(dst, src);
535 void Assembler::cld() {
536 EnsureSpace ensure_space(this);
541 void Assembler::rep_movs() {
542 EnsureSpace ensure_space(this);
548 void Assembler::rep_stos() {
549 EnsureSpace ensure_space(this);
555 void Assembler::stos() {
556 EnsureSpace ensure_space(this);
561 void Assembler::xchg(Register dst, Register src) {
562 EnsureSpace ensure_space(this);
563 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
564 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
567 EMIT(0xC0 | src.code() << 3 | dst.code());
572 void Assembler::xchg(Register dst, const Operand& src) {
573 EnsureSpace ensure_space(this);
575 emit_operand(dst, src);
579 void Assembler::adc(Register dst, int32_t imm32) {
580 EnsureSpace ensure_space(this);
581 emit_arith(2, Operand(dst), Immediate(imm32));
585 void Assembler::adc(Register dst, const Operand& src) {
586 EnsureSpace ensure_space(this);
588 emit_operand(dst, src);
592 void Assembler::add(Register dst, const Operand& src) {
593 EnsureSpace ensure_space(this);
595 emit_operand(dst, src);
599 void Assembler::add(const Operand& dst, Register src) {
600 EnsureSpace ensure_space(this);
602 emit_operand(src, dst);
606 void Assembler::add(const Operand& dst, const Immediate& x) {
607 DCHECK(reloc_info_writer.last_pc() != NULL);
608 EnsureSpace ensure_space(this);
609 emit_arith(0, dst, x);
613 void Assembler::and_(Register dst, int32_t imm32) {
614 and_(dst, Immediate(imm32));
618 void Assembler::and_(Register dst, const Immediate& x) {
619 EnsureSpace ensure_space(this);
620 emit_arith(4, Operand(dst), x);
624 void Assembler::and_(Register dst, const Operand& src) {
625 EnsureSpace ensure_space(this);
627 emit_operand(dst, src);
631 void Assembler::and_(const Operand& dst, const Immediate& x) {
632 EnsureSpace ensure_space(this);
633 emit_arith(4, dst, x);
637 void Assembler::and_(const Operand& dst, Register src) {
638 EnsureSpace ensure_space(this);
640 emit_operand(src, dst);
644 void Assembler::cmpb(const Operand& op, int8_t imm8) {
645 EnsureSpace ensure_space(this);
646 if (op.is_reg(eax)) {
650 emit_operand(edi, op); // edi == 7
656 void Assembler::cmpb(const Operand& op, Register reg) {
657 CHECK(reg.is_byte_register());
658 EnsureSpace ensure_space(this);
660 emit_operand(reg, op);
664 void Assembler::cmpb(Register reg, const Operand& op) {
665 CHECK(reg.is_byte_register());
666 EnsureSpace ensure_space(this);
668 emit_operand(reg, op);
672 void Assembler::cmpw(const Operand& op, Immediate imm16) {
673 DCHECK(imm16.is_int16());
674 EnsureSpace ensure_space(this);
677 emit_operand(edi, op);
682 void Assembler::cmp(Register reg, int32_t imm32) {
683 EnsureSpace ensure_space(this);
684 emit_arith(7, Operand(reg), Immediate(imm32));
688 void Assembler::cmp(Register reg, Handle<Object> handle) {
689 EnsureSpace ensure_space(this);
690 emit_arith(7, Operand(reg), Immediate(handle));
694 void Assembler::cmp(Register reg, const Operand& op) {
695 EnsureSpace ensure_space(this);
697 emit_operand(reg, op);
701 void Assembler::cmp(const Operand& op, const Immediate& imm) {
702 EnsureSpace ensure_space(this);
703 emit_arith(7, op, imm);
707 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
708 EnsureSpace ensure_space(this);
709 emit_arith(7, op, Immediate(handle));
713 void Assembler::cmpb_al(const Operand& op) {
714 EnsureSpace ensure_space(this);
715 EMIT(0x38); // CMP r/m8, r8
716 emit_operand(eax, op); // eax has same code as register al.
720 void Assembler::cmpw_ax(const Operand& op) {
721 EnsureSpace ensure_space(this);
723 EMIT(0x39); // CMP r/m16, r16
724 emit_operand(eax, op); // eax has same code as register ax.
728 void Assembler::dec_b(Register dst) {
729 CHECK(dst.is_byte_register());
730 EnsureSpace ensure_space(this);
732 EMIT(0xC8 | dst.code());
736 void Assembler::dec_b(const Operand& dst) {
737 EnsureSpace ensure_space(this);
739 emit_operand(ecx, dst);
743 void Assembler::dec(Register dst) {
744 EnsureSpace ensure_space(this);
745 EMIT(0x48 | dst.code());
749 void Assembler::dec(const Operand& dst) {
750 EnsureSpace ensure_space(this);
752 emit_operand(ecx, dst);
756 void Assembler::cdq() {
757 EnsureSpace ensure_space(this);
762 void Assembler::idiv(const Operand& src) {
763 EnsureSpace ensure_space(this);
765 emit_operand(edi, src);
769 void Assembler::div(const Operand& src) {
770 EnsureSpace ensure_space(this);
772 emit_operand(esi, src);
776 void Assembler::imul(Register reg) {
777 EnsureSpace ensure_space(this);
779 EMIT(0xE8 | reg.code());
783 void Assembler::imul(Register dst, const Operand& src) {
784 EnsureSpace ensure_space(this);
787 emit_operand(dst, src);
791 void Assembler::imul(Register dst, Register src, int32_t imm32) {
792 imul(dst, Operand(src), imm32);
796 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
797 EnsureSpace ensure_space(this);
798 if (is_int8(imm32)) {
800 emit_operand(dst, src);
804 emit_operand(dst, src);
810 void Assembler::inc(Register dst) {
811 EnsureSpace ensure_space(this);
812 EMIT(0x40 | dst.code());
816 void Assembler::inc(const Operand& dst) {
817 EnsureSpace ensure_space(this);
819 emit_operand(eax, dst);
823 void Assembler::lea(Register dst, const Operand& src) {
824 EnsureSpace ensure_space(this);
826 emit_operand(dst, src);
830 void Assembler::mul(Register src) {
831 EnsureSpace ensure_space(this);
833 EMIT(0xE0 | src.code());
837 void Assembler::neg(Register dst) {
838 EnsureSpace ensure_space(this);
840 EMIT(0xD8 | dst.code());
844 void Assembler::neg(const Operand& dst) {
845 EnsureSpace ensure_space(this);
847 emit_operand(ebx, dst);
851 void Assembler::not_(Register dst) {
852 EnsureSpace ensure_space(this);
854 EMIT(0xD0 | dst.code());
858 void Assembler::not_(const Operand& dst) {
859 EnsureSpace ensure_space(this);
861 emit_operand(edx, dst);
865 void Assembler::or_(Register dst, int32_t imm32) {
866 EnsureSpace ensure_space(this);
867 emit_arith(1, Operand(dst), Immediate(imm32));
871 void Assembler::or_(Register dst, const Operand& src) {
872 EnsureSpace ensure_space(this);
874 emit_operand(dst, src);
878 void Assembler::or_(const Operand& dst, const Immediate& x) {
879 EnsureSpace ensure_space(this);
880 emit_arith(1, dst, x);
884 void Assembler::or_(const Operand& dst, Register src) {
885 EnsureSpace ensure_space(this);
887 emit_operand(src, dst);
891 void Assembler::rcl(Register dst, uint8_t imm8) {
892 EnsureSpace ensure_space(this);
893 DCHECK(is_uint5(imm8)); // illegal shift count
896 EMIT(0xD0 | dst.code());
899 EMIT(0xD0 | dst.code());
905 void Assembler::rcr(Register dst, uint8_t imm8) {
906 EnsureSpace ensure_space(this);
907 DCHECK(is_uint5(imm8)); // illegal shift count
910 EMIT(0xD8 | dst.code());
913 EMIT(0xD8 | dst.code());
919 void Assembler::ror(const Operand& dst, uint8_t imm8) {
920 EnsureSpace ensure_space(this);
921 DCHECK(is_uint5(imm8)); // illegal shift count
924 emit_operand(ecx, dst);
927 emit_operand(ecx, dst);
933 void Assembler::ror_cl(const Operand& dst) {
934 EnsureSpace ensure_space(this);
936 emit_operand(ecx, dst);
940 void Assembler::sar(const Operand& dst, uint8_t imm8) {
941 EnsureSpace ensure_space(this);
942 DCHECK(is_uint5(imm8)); // illegal shift count
945 emit_operand(edi, dst);
948 emit_operand(edi, dst);
954 void Assembler::sar_cl(const Operand& dst) {
955 EnsureSpace ensure_space(this);
957 emit_operand(edi, dst);
961 void Assembler::sbb(Register dst, const Operand& src) {
962 EnsureSpace ensure_space(this);
964 emit_operand(dst, src);
968 void Assembler::shld(Register dst, const Operand& src) {
969 EnsureSpace ensure_space(this);
972 emit_operand(dst, src);
976 void Assembler::shl(const Operand& dst, uint8_t imm8) {
977 EnsureSpace ensure_space(this);
978 DCHECK(is_uint5(imm8)); // illegal shift count
981 emit_operand(esp, dst);
984 emit_operand(esp, dst);
990 void Assembler::shl_cl(const Operand& dst) {
991 EnsureSpace ensure_space(this);
993 emit_operand(esp, dst);
997 void Assembler::shrd(Register dst, const Operand& src) {
998 EnsureSpace ensure_space(this);
1001 emit_operand(dst, src);
1005 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1006 EnsureSpace ensure_space(this);
1007 DCHECK(is_uint5(imm8)); // illegal shift count
1010 emit_operand(ebp, dst);
1013 emit_operand(ebp, dst);
1019 void Assembler::shr_cl(const Operand& dst) {
1020 EnsureSpace ensure_space(this);
1022 emit_operand(ebp, dst);
1026 void Assembler::sub(const Operand& dst, const Immediate& x) {
1027 EnsureSpace ensure_space(this);
1028 emit_arith(5, dst, x);
1032 void Assembler::sub(Register dst, const Operand& src) {
1033 EnsureSpace ensure_space(this);
1035 emit_operand(dst, src);
1039 void Assembler::sub(const Operand& dst, Register src) {
1040 EnsureSpace ensure_space(this);
1042 emit_operand(src, dst);
1046 void Assembler::test(Register reg, const Immediate& imm) {
1047 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1048 test_b(reg, imm.x_);
1052 EnsureSpace ensure_space(this);
1053 // This is not using emit_arith because test doesn't support
1054 // sign-extension of 8-bit operands.
1059 EMIT(0xC0 | reg.code());
1065 void Assembler::test(Register reg, const Operand& op) {
1066 EnsureSpace ensure_space(this);
1068 emit_operand(reg, op);
1072 void Assembler::test_b(Register reg, const Operand& op) {
1073 CHECK(reg.is_byte_register());
1074 EnsureSpace ensure_space(this);
1076 emit_operand(reg, op);
1080 void Assembler::test(const Operand& op, const Immediate& imm) {
1081 if (op.is_reg_only()) {
1082 test(op.reg(), imm);
1085 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1086 return test_b(op, imm.x_);
1088 EnsureSpace ensure_space(this);
1090 emit_operand(eax, op);
1095 void Assembler::test_b(Register reg, uint8_t imm8) {
1096 EnsureSpace ensure_space(this);
1097 // Only use test against byte for registers that have a byte
1098 // variant: eax, ebx, ecx, and edx.
1102 } else if (reg.is_byte_register()) {
1103 emit_arith_b(0xF6, 0xC0, reg, imm8);
1106 EMIT(0xC0 | reg.code());
1112 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1113 if (op.is_reg_only()) {
1114 test_b(op.reg(), imm8);
1117 EnsureSpace ensure_space(this);
1119 emit_operand(eax, op);
1124 void Assembler::xor_(Register dst, int32_t imm32) {
1125 EnsureSpace ensure_space(this);
1126 emit_arith(6, Operand(dst), Immediate(imm32));
1130 void Assembler::xor_(Register dst, const Operand& src) {
1131 EnsureSpace ensure_space(this);
1133 emit_operand(dst, src);
1137 void Assembler::xor_(const Operand& dst, Register src) {
1138 EnsureSpace ensure_space(this);
1140 emit_operand(src, dst);
1144 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1145 EnsureSpace ensure_space(this);
1146 emit_arith(6, dst, x);
1150 void Assembler::bt(const Operand& dst, Register src) {
1151 EnsureSpace ensure_space(this);
1154 emit_operand(src, dst);
1158 void Assembler::bts(const Operand& dst, Register src) {
1159 EnsureSpace ensure_space(this);
1162 emit_operand(src, dst);
1166 void Assembler::bsr(Register dst, const Operand& src) {
1167 EnsureSpace ensure_space(this);
1170 emit_operand(dst, src);
1174 void Assembler::hlt() {
1175 EnsureSpace ensure_space(this);
1180 void Assembler::int3() {
1181 EnsureSpace ensure_space(this);
1186 void Assembler::nop() {
1187 EnsureSpace ensure_space(this);
1192 void Assembler::ret(int imm16) {
1193 EnsureSpace ensure_space(this);
1194 DCHECK(is_uint16(imm16));
1200 EMIT((imm16 >> 8) & 0xFF);
1205 void Assembler::ud2() {
1206 EnsureSpace ensure_space(this);
1212 // Labels refer to positions in the (to be) generated code.
1213 // There are bound, linked, and unused labels.
1215 // Bound labels refer to known positions in the already
1216 // generated code. pos() is the position the label refers to.
1218 // Linked labels refer to unknown positions in the code
1219 // to be generated; pos() is the position of the 32bit
1220 // Displacement of the last instruction using the label.
1223 void Assembler::print(Label* L) {
1224 if (L->is_unused()) {
1225 PrintF("unused label\n");
1226 } else if (L->is_bound()) {
1227 PrintF("bound label to %d\n", L->pos());
1228 } else if (L->is_linked()) {
1230 PrintF("unbound label");
1231 while (l.is_linked()) {
1232 Displacement disp = disp_at(&l);
1233 PrintF("@ %d ", l.pos());
1239 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1244 void Assembler::bind_to(Label* L, int pos) {
1245 EnsureSpace ensure_space(this);
1246 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1247 while (L->is_linked()) {
1248 Displacement disp = disp_at(L);
1249 int fixup_pos = L->pos();
1250 if (disp.type() == Displacement::CODE_ABSOLUTE) {
1251 long_at_put(fixup_pos, reinterpret_cast<int>(buffer_ + pos));
1252 internal_reference_positions_.push_back(fixup_pos);
1253 } else if (disp.type() == Displacement::CODE_RELATIVE) {
1254 // Relative to Code* heap object pointer.
1255 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1257 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1258 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1260 // Relative address, relative to point after address.
1261 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1262 long_at_put(fixup_pos, imm32);
1266 while (L->is_near_linked()) {
1267 int fixup_pos = L->near_link_pos();
1268 int offset_to_next =
1269 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1270 DCHECK(offset_to_next <= 0);
1271 // Relative address, relative to point after address.
1272 int disp = pos - fixup_pos - sizeof(int8_t);
1273 CHECK(0 <= disp && disp <= 127);
1274 set_byte_at(fixup_pos, disp);
1275 if (offset_to_next < 0) {
1276 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1285 void Assembler::bind(Label* L) {
1286 EnsureSpace ensure_space(this);
1287 DCHECK(!L->is_bound()); // label can only be bound once
1288 bind_to(L, pc_offset());
1292 void Assembler::call(Label* L) {
1293 positions_recorder()->WriteRecordedPositions();
1294 EnsureSpace ensure_space(this);
1295 if (L->is_bound()) {
1296 const int long_size = 5;
1297 int offs = L->pos() - pc_offset();
1299 // 1110 1000 #32-bit disp.
1301 emit(offs - long_size);
1303 // 1110 1000 #32-bit disp.
1305 emit_disp(L, Displacement::OTHER);
1310 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1311 positions_recorder()->WriteRecordedPositions();
1312 EnsureSpace ensure_space(this);
1313 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1315 if (RelocInfo::IsRuntimeEntry(rmode)) {
1316 emit(reinterpret_cast<uint32_t>(entry), rmode);
1318 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1323 int Assembler::CallSize(const Operand& adr) {
1324 // Call size is 1 (opcode) + adr.len_ (operand).
1325 return 1 + adr.len_;
1329 void Assembler::call(const Operand& adr) {
1330 positions_recorder()->WriteRecordedPositions();
1331 EnsureSpace ensure_space(this);
1333 emit_operand(edx, adr);
1337 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1338 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1342 void Assembler::call(Handle<Code> code,
1343 RelocInfo::Mode rmode,
1344 TypeFeedbackId ast_id) {
1345 positions_recorder()->WriteRecordedPositions();
1346 EnsureSpace ensure_space(this);
1347 DCHECK(RelocInfo::IsCodeTarget(rmode)
1348 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1350 emit(code, rmode, ast_id);
1354 void Assembler::jmp(Label* L, Label::Distance distance) {
1355 EnsureSpace ensure_space(this);
1356 if (L->is_bound()) {
1357 const int short_size = 2;
1358 const int long_size = 5;
1359 int offs = L->pos() - pc_offset();
1361 if (is_int8(offs - short_size)) {
1362 // 1110 1011 #8-bit disp.
1364 EMIT((offs - short_size) & 0xFF);
1366 // 1110 1001 #32-bit disp.
1368 emit(offs - long_size);
1370 } else if (distance == Label::kNear) {
1374 // 1110 1001 #32-bit disp.
1376 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1381 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1382 EnsureSpace ensure_space(this);
1383 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1385 if (RelocInfo::IsRuntimeEntry(rmode)) {
1386 emit(reinterpret_cast<uint32_t>(entry), rmode);
1388 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1393 void Assembler::jmp(const Operand& adr) {
1394 EnsureSpace ensure_space(this);
1396 emit_operand(esp, adr);
1400 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1401 EnsureSpace ensure_space(this);
1402 DCHECK(RelocInfo::IsCodeTarget(rmode));
1408 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1409 EnsureSpace ensure_space(this);
1410 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1411 if (L->is_bound()) {
1412 const int short_size = 2;
1413 const int long_size = 6;
1414 int offs = L->pos() - pc_offset();
1416 if (is_int8(offs - short_size)) {
1417 // 0111 tttn #8-bit disp
1419 EMIT((offs - short_size) & 0xFF);
1421 // 0000 1111 1000 tttn #32-bit disp
1424 emit(offs - long_size);
1426 } else if (distance == Label::kNear) {
1430 // 0000 1111 1000 tttn #32-bit disp
1431 // Note: could eliminate cond. jumps to this jump if condition
1432 // is the same however, seems to be rather unlikely case.
1435 emit_disp(L, Displacement::OTHER);
1440 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1441 EnsureSpace ensure_space(this);
1442 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1443 // 0000 1111 1000 tttn #32-bit disp.
1446 if (RelocInfo::IsRuntimeEntry(rmode)) {
1447 emit(reinterpret_cast<uint32_t>(entry), rmode);
1449 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1454 void Assembler::j(Condition cc, Handle<Code> code) {
1455 EnsureSpace ensure_space(this);
1456 // 0000 1111 1000 tttn #32-bit disp
1459 emit(code, RelocInfo::CODE_TARGET);
1463 // FPU instructions.
1465 void Assembler::fld(int i) {
1466 EnsureSpace ensure_space(this);
1467 emit_farith(0xD9, 0xC0, i);
1471 void Assembler::fstp(int i) {
1472 EnsureSpace ensure_space(this);
1473 emit_farith(0xDD, 0xD8, i);
1477 void Assembler::fld1() {
1478 EnsureSpace ensure_space(this);
1484 void Assembler::fldpi() {
1485 EnsureSpace ensure_space(this);
1491 void Assembler::fldz() {
1492 EnsureSpace ensure_space(this);
1498 void Assembler::fldln2() {
1499 EnsureSpace ensure_space(this);
1505 void Assembler::fld_s(const Operand& adr) {
1506 EnsureSpace ensure_space(this);
1508 emit_operand(eax, adr);
1512 void Assembler::fld_d(const Operand& adr) {
1513 EnsureSpace ensure_space(this);
1515 emit_operand(eax, adr);
1519 void Assembler::fstp_s(const Operand& adr) {
1520 EnsureSpace ensure_space(this);
1522 emit_operand(ebx, adr);
1526 void Assembler::fst_s(const Operand& adr) {
1527 EnsureSpace ensure_space(this);
1529 emit_operand(edx, adr);
1533 void Assembler::fldcw(const Operand& adr) {
1534 EnsureSpace ensure_space(this);
1536 emit_operand(ebp, adr);
1540 void Assembler::fnstcw(const Operand& adr) {
1541 EnsureSpace ensure_space(this);
1543 emit_operand(edi, adr);
1547 void Assembler::fstp_d(const Operand& adr) {
1548 EnsureSpace ensure_space(this);
1550 emit_operand(ebx, adr);
1554 void Assembler::fst_d(const Operand& adr) {
1555 EnsureSpace ensure_space(this);
1557 emit_operand(edx, adr);
1561 void Assembler::fild_s(const Operand& adr) {
1562 EnsureSpace ensure_space(this);
1564 emit_operand(eax, adr);
1568 void Assembler::fild_d(const Operand& adr) {
1569 EnsureSpace ensure_space(this);
1571 emit_operand(ebp, adr);
1575 void Assembler::fistp_s(const Operand& adr) {
1576 EnsureSpace ensure_space(this);
1578 emit_operand(ebx, adr);
1582 void Assembler::fisttp_s(const Operand& adr) {
1583 DCHECK(IsEnabled(SSE3));
1584 EnsureSpace ensure_space(this);
1586 emit_operand(ecx, adr);
1590 void Assembler::fisttp_d(const Operand& adr) {
1591 DCHECK(IsEnabled(SSE3));
1592 EnsureSpace ensure_space(this);
1594 emit_operand(ecx, adr);
1598 void Assembler::fist_s(const Operand& adr) {
1599 EnsureSpace ensure_space(this);
1601 emit_operand(edx, adr);
1605 void Assembler::fistp_d(const Operand& adr) {
1606 EnsureSpace ensure_space(this);
1608 emit_operand(edi, adr);
1612 void Assembler::fabs() {
1613 EnsureSpace ensure_space(this);
1619 void Assembler::fchs() {
1620 EnsureSpace ensure_space(this);
1626 void Assembler::fsqrt() {
1627 EnsureSpace ensure_space(this);
1633 void Assembler::fcos() {
1634 EnsureSpace ensure_space(this);
1640 void Assembler::fsin() {
1641 EnsureSpace ensure_space(this);
1647 void Assembler::fptan() {
1648 EnsureSpace ensure_space(this);
1654 void Assembler::fyl2x() {
1655 EnsureSpace ensure_space(this);
1661 void Assembler::f2xm1() {
1662 EnsureSpace ensure_space(this);
1668 void Assembler::fscale() {
1669 EnsureSpace ensure_space(this);
1675 void Assembler::fninit() {
1676 EnsureSpace ensure_space(this);
1682 void Assembler::fadd(int i) {
1683 EnsureSpace ensure_space(this);
1684 emit_farith(0xDC, 0xC0, i);
1688 void Assembler::fadd_i(int i) {
1689 EnsureSpace ensure_space(this);
1690 emit_farith(0xD8, 0xC0, i);
1694 void Assembler::fadd_d(const Operand& adr) {
1695 EnsureSpace ensure_space(this);
1697 emit_operand(eax, adr);
1701 void Assembler::fsub(int i) {
1702 EnsureSpace ensure_space(this);
1703 emit_farith(0xDC, 0xE8, i);
1707 void Assembler::fsub_i(int i) {
1708 EnsureSpace ensure_space(this);
1709 emit_farith(0xD8, 0xE0, i);
1713 void Assembler::fisub_s(const Operand& adr) {
1714 EnsureSpace ensure_space(this);
1716 emit_operand(esp, adr);
1720 void Assembler::fmul_i(int i) {
1721 EnsureSpace ensure_space(this);
1722 emit_farith(0xD8, 0xC8, i);
1726 void Assembler::fmul(int i) {
1727 EnsureSpace ensure_space(this);
1728 emit_farith(0xDC, 0xC8, i);
1732 void Assembler::fdiv(int i) {
1733 EnsureSpace ensure_space(this);
1734 emit_farith(0xDC, 0xF8, i);
1738 void Assembler::fdiv_i(int i) {
1739 EnsureSpace ensure_space(this);
1740 emit_farith(0xD8, 0xF0, i);
1744 void Assembler::faddp(int i) {
1745 EnsureSpace ensure_space(this);
1746 emit_farith(0xDE, 0xC0, i);
1750 void Assembler::fsubp(int i) {
1751 EnsureSpace ensure_space(this);
1752 emit_farith(0xDE, 0xE8, i);
1756 void Assembler::fsubrp(int i) {
1757 EnsureSpace ensure_space(this);
1758 emit_farith(0xDE, 0xE0, i);
1762 void Assembler::fmulp(int i) {
1763 EnsureSpace ensure_space(this);
1764 emit_farith(0xDE, 0xC8, i);
1768 void Assembler::fdivp(int i) {
1769 EnsureSpace ensure_space(this);
1770 emit_farith(0xDE, 0xF8, i);
1774 void Assembler::fprem() {
1775 EnsureSpace ensure_space(this);
1781 void Assembler::fprem1() {
1782 EnsureSpace ensure_space(this);
1788 void Assembler::fxch(int i) {
1789 EnsureSpace ensure_space(this);
1790 emit_farith(0xD9, 0xC8, i);
1794 void Assembler::fincstp() {
1795 EnsureSpace ensure_space(this);
1801 void Assembler::ffree(int i) {
1802 EnsureSpace ensure_space(this);
1803 emit_farith(0xDD, 0xC0, i);
1807 void Assembler::ftst() {
1808 EnsureSpace ensure_space(this);
1814 void Assembler::fxam() {
1815 EnsureSpace ensure_space(this);
1821 void Assembler::fucomp(int i) {
1822 EnsureSpace ensure_space(this);
1823 emit_farith(0xDD, 0xE8, i);
1827 void Assembler::fucompp() {
1828 EnsureSpace ensure_space(this);
1834 void Assembler::fucomi(int i) {
1835 EnsureSpace ensure_space(this);
1841 void Assembler::fucomip() {
1842 EnsureSpace ensure_space(this);
1848 void Assembler::fcompp() {
1849 EnsureSpace ensure_space(this);
1855 void Assembler::fnstsw_ax() {
1856 EnsureSpace ensure_space(this);
1862 void Assembler::fwait() {
1863 EnsureSpace ensure_space(this);
1868 void Assembler::frndint() {
1869 EnsureSpace ensure_space(this);
1875 void Assembler::fnclex() {
1876 EnsureSpace ensure_space(this);
1882 void Assembler::fnsave(const Operand& adr) {
1883 EnsureSpace ensure_space(this);
1885 emit_operand(esi, adr);
1889 void Assembler::frstor(const Operand& adr) {
1890 EnsureSpace ensure_space(this);
1892 emit_operand(esp, adr);
1896 void Assembler::sahf() {
1897 EnsureSpace ensure_space(this);
1902 void Assembler::setcc(Condition cc, Register reg) {
1903 DCHECK(reg.is_byte_register());
1904 EnsureSpace ensure_space(this);
1907 EMIT(0xC0 | reg.code());
1911 void Assembler::GrowBuffer() {
1912 DCHECK(buffer_overflow());
1913 if (!own_buffer_) FATAL("external code buffer is too small");
1915 // Compute new buffer size.
1916 CodeDesc desc; // the new buffer
1917 desc.buffer_size = 2 * buffer_size_;
1919 // Some internal data structures overflow for very large buffers,
1920 // they must ensure that kMaximalBufferSize is not too large.
1921 if ((desc.buffer_size > kMaximalBufferSize) ||
1922 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
1923 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
1926 // Set up new buffer.
1927 desc.buffer = NewArray<byte>(desc.buffer_size);
1928 desc.instr_size = pc_offset();
1929 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
1931 // Clear the buffer in debug mode. Use 'int3' instructions to make
1932 // sure to get into problems if we ever run uninitialized code.
1934 memset(desc.buffer, 0xCC, desc.buffer_size);
1938 int pc_delta = desc.buffer - buffer_;
1939 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
1940 MemMove(desc.buffer, buffer_, desc.instr_size);
1941 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
1944 DeleteArray(buffer_);
1945 buffer_ = desc.buffer;
1946 buffer_size_ = desc.buffer_size;
1948 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
1949 reloc_info_writer.last_pc() + pc_delta);
1951 // Relocate internal references.
1952 for (auto pos : internal_reference_positions_) {
1953 int32_t* p = reinterpret_cast<int32_t*>(buffer_ + pos);
1957 DCHECK(!buffer_overflow());
1961 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
1962 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
1963 DCHECK(is_uint8(imm8));
1964 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
1966 EMIT(op2 | dst.code());
1971 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
1972 DCHECK((0 <= sel) && (sel <= 7));
1973 Register ireg = { sel };
1975 EMIT(0x83); // using a sign-extended 8-bit immediate.
1976 emit_operand(ireg, dst);
1978 } else if (dst.is_reg(eax)) {
1979 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
1982 EMIT(0x81); // using a literal 32-bit immediate.
1983 emit_operand(ireg, dst);
1989 void Assembler::emit_operand(Register reg, const Operand& adr) {
1990 const unsigned length = adr.len_;
1993 // Emit updated ModRM byte containing the given register.
1994 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
1996 // Emit the rest of the encoded operand.
1997 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2000 // Emit relocation information if necessary.
2001 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2002 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2003 RecordRelocInfo(adr.rmode_);
2004 if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) { // Fixup for labels
2005 emit_label(*reinterpret_cast<Label**>(pc_));
2007 pc_ += sizeof(int32_t);
2013 void Assembler::emit_label(Label* label) {
2014 if (label->is_bound()) {
2015 internal_reference_positions_.push_back(pc_offset());
2016 emit(reinterpret_cast<uint32_t>(buffer_ + label->pos()));
2018 emit_disp(label, Displacement::CODE_ABSOLUTE);
2023 void Assembler::emit_farith(int b1, int b2, int i) {
2024 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2025 DCHECK(0 <= i && i < 8); // illegal stack offset
2031 void Assembler::db(uint8_t data) {
2032 EnsureSpace ensure_space(this);
2037 void Assembler::dd(uint32_t data) {
2038 EnsureSpace ensure_space(this);
2043 void Assembler::dd(Label* label) {
2044 EnsureSpace ensure_space(this);
2045 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2050 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2051 DCHECK(!RelocInfo::IsNone(rmode));
2052 // Don't record external references unless the heap will be serialized.
2053 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2054 !serializer_enabled() && !emit_debug_code()) {
2057 RelocInfo rinfo(pc_, rmode, data, NULL);
2058 reloc_info_writer.Write(&rinfo);
2062 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2063 // No out-of-line constant pool support.
2064 DCHECK(!FLAG_enable_ool_constant_pool);
2065 return isolate->factory()->empty_constant_pool_array();
2069 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2070 // No out-of-line constant pool support.
2071 DCHECK(!FLAG_enable_ool_constant_pool);
2076 #ifdef GENERATED_CODE_COVERAGE
2077 static FILE* coverage_log = NULL;
2080 static void InitCoverageLog() {
2081 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2082 if (file_name != NULL) {
2083 coverage_log = fopen(file_name, "aw+");
2088 void LogGeneratedCodeCoverage(const char* file_line) {
2089 const char* return_address = (&file_line)[-1];
2090 char* push_insn = const_cast<char*>(return_address - 12);
2091 push_insn[0] = 0xeb; // Relative branch insn.
2092 push_insn[1] = 13; // Skip over coverage insns.
2093 if (coverage_log != NULL) {
2094 fprintf(coverage_log, "%s\n", file_line);
2095 fflush(coverage_log);
2101 } } // namespace v8::internal
2103 #endif // V8_TARGET_ARCH_X87