1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
11 #if V8_TARGET_ARCH_X64
13 #include "src/base/lazy-instance.h"
14 #include "src/disasm.h"
20 // Operand size decides between 16, 32 and 64 bit operands.
21 REG_OPER_OP_ORDER = 1, // Register destination, operand source.
22 OPER_REG_OP_ORDER = 2, // Operand destination, register source.
23 // Fixed 8-bit operands.
24 BYTE_SIZE_OPERAND_FLAG = 4,
25 BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
26 BYTE_OPER_REG_OP_ORDER = OPER_REG_OP_ORDER | BYTE_SIZE_OPERAND_FLAG
30 //------------------------------------------------------------------
32 //------------------------------------------------------------------
34 int b; // -1 terminates, otherwise must be in range (0..255)
35 OperandType op_order_;
40 static const ByteMnemonic two_operands_instr[] = {
41 { 0x00, BYTE_OPER_REG_OP_ORDER, "add" },
42 { 0x01, OPER_REG_OP_ORDER, "add" },
43 { 0x02, BYTE_REG_OPER_OP_ORDER, "add" },
44 { 0x03, REG_OPER_OP_ORDER, "add" },
45 { 0x08, BYTE_OPER_REG_OP_ORDER, "or" },
46 { 0x09, OPER_REG_OP_ORDER, "or" },
47 { 0x0A, BYTE_REG_OPER_OP_ORDER, "or" },
48 { 0x0B, REG_OPER_OP_ORDER, "or" },
49 { 0x10, BYTE_OPER_REG_OP_ORDER, "adc" },
50 { 0x11, OPER_REG_OP_ORDER, "adc" },
51 { 0x12, BYTE_REG_OPER_OP_ORDER, "adc" },
52 { 0x13, REG_OPER_OP_ORDER, "adc" },
53 { 0x18, BYTE_OPER_REG_OP_ORDER, "sbb" },
54 { 0x19, OPER_REG_OP_ORDER, "sbb" },
55 { 0x1A, BYTE_REG_OPER_OP_ORDER, "sbb" },
56 { 0x1B, REG_OPER_OP_ORDER, "sbb" },
57 { 0x20, BYTE_OPER_REG_OP_ORDER, "and" },
58 { 0x21, OPER_REG_OP_ORDER, "and" },
59 { 0x22, BYTE_REG_OPER_OP_ORDER, "and" },
60 { 0x23, REG_OPER_OP_ORDER, "and" },
61 { 0x28, BYTE_OPER_REG_OP_ORDER, "sub" },
62 { 0x29, OPER_REG_OP_ORDER, "sub" },
63 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" },
64 { 0x2B, REG_OPER_OP_ORDER, "sub" },
65 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" },
66 { 0x31, OPER_REG_OP_ORDER, "xor" },
67 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" },
68 { 0x33, REG_OPER_OP_ORDER, "xor" },
69 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" },
70 { 0x39, OPER_REG_OP_ORDER, "cmp" },
71 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" },
72 { 0x3B, REG_OPER_OP_ORDER, "cmp" },
73 { 0x63, REG_OPER_OP_ORDER, "movsxl" },
74 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" },
75 { 0x85, REG_OPER_OP_ORDER, "test" },
76 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" },
77 { 0x87, REG_OPER_OP_ORDER, "xchg" },
78 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" },
79 { 0x89, OPER_REG_OP_ORDER, "mov" },
80 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" },
81 { 0x8B, REG_OPER_OP_ORDER, "mov" },
82 { 0x8D, REG_OPER_OP_ORDER, "lea" },
83 { -1, UNSET_OP_ORDER, "" }
87 static const ByteMnemonic zero_operands_instr[] = {
88 { 0xC3, UNSET_OP_ORDER, "ret" },
89 { 0xC9, UNSET_OP_ORDER, "leave" },
90 { 0xF4, UNSET_OP_ORDER, "hlt" },
91 { 0xFC, UNSET_OP_ORDER, "cld" },
92 { 0xCC, UNSET_OP_ORDER, "int3" },
93 { 0x60, UNSET_OP_ORDER, "pushad" },
94 { 0x61, UNSET_OP_ORDER, "popad" },
95 { 0x9C, UNSET_OP_ORDER, "pushfd" },
96 { 0x9D, UNSET_OP_ORDER, "popfd" },
97 { 0x9E, UNSET_OP_ORDER, "sahf" },
98 { 0x99, UNSET_OP_ORDER, "cdq" },
99 { 0x9B, UNSET_OP_ORDER, "fwait" },
100 { 0xA4, UNSET_OP_ORDER, "movs" },
101 { 0xA5, UNSET_OP_ORDER, "movs" },
102 { 0xA6, UNSET_OP_ORDER, "cmps" },
103 { 0xA7, UNSET_OP_ORDER, "cmps" },
104 { -1, UNSET_OP_ORDER, "" }
108 static const ByteMnemonic call_jump_instr[] = {
109 { 0xE8, UNSET_OP_ORDER, "call" },
110 { 0xE9, UNSET_OP_ORDER, "jmp" },
111 { -1, UNSET_OP_ORDER, "" }
115 static const ByteMnemonic short_immediate_instr[] = {
116 { 0x05, UNSET_OP_ORDER, "add" },
117 { 0x0D, UNSET_OP_ORDER, "or" },
118 { 0x15, UNSET_OP_ORDER, "adc" },
119 { 0x1D, UNSET_OP_ORDER, "sbb" },
120 { 0x25, UNSET_OP_ORDER, "and" },
121 { 0x2D, UNSET_OP_ORDER, "sub" },
122 { 0x35, UNSET_OP_ORDER, "xor" },
123 { 0x3D, UNSET_OP_ORDER, "cmp" },
124 { -1, UNSET_OP_ORDER, "" }
128 static const char* const conditional_code_suffix[] = {
129 "o", "no", "c", "nc", "z", "nz", "na", "a",
130 "s", "ns", "pe", "po", "l", "ge", "le", "g"
134 enum InstructionType {
138 JUMP_CONDITIONAL_SHORT_INSTR,
140 PUSHPOP_INSTR, // Has implicit 64-bit operand size.
143 SHORT_IMMEDIATE_INSTR
148 ESCAPE_PREFIX = 0x0F,
149 OPERAND_SIZE_OVERRIDE_PREFIX = 0x66,
150 ADDRESS_SIZE_OVERRIDE_PREFIX = 0x67,
155 REPEQ_PREFIX = REP_PREFIX
159 struct InstructionDesc {
161 InstructionType type;
162 OperandType op_order_;
163 bool byte_size_operation; // Fixed 8-bit operation.
167 class InstructionTable {
170 const InstructionDesc& Get(byte x) const {
171 return instructions_[x];
175 InstructionDesc instructions_[256];
178 void CopyTable(const ByteMnemonic bm[], InstructionType type);
179 void SetTableRange(InstructionType type, byte start, byte end, bool byte_size,
181 void AddJumpConditionalShort();
185 InstructionTable::InstructionTable() {
191 void InstructionTable::Clear() {
192 for (int i = 0; i < 256; i++) {
193 instructions_[i].mnem = "(bad)";
194 instructions_[i].type = NO_INSTR;
195 instructions_[i].op_order_ = UNSET_OP_ORDER;
196 instructions_[i].byte_size_operation = false;
201 void InstructionTable::Init() {
202 CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
203 CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
204 CopyTable(call_jump_instr, CALL_JUMP_INSTR);
205 CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
206 AddJumpConditionalShort();
207 SetTableRange(PUSHPOP_INSTR, 0x50, 0x57, false, "push");
208 SetTableRange(PUSHPOP_INSTR, 0x58, 0x5F, false, "pop");
209 SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, false, "mov");
213 void InstructionTable::CopyTable(const ByteMnemonic bm[],
214 InstructionType type) {
215 for (int i = 0; bm[i].b >= 0; i++) {
216 InstructionDesc* id = &instructions_[bm[i].b];
217 id->mnem = bm[i].mnem;
218 OperandType op_order = bm[i].op_order_;
220 static_cast<OperandType>(op_order & ~BYTE_SIZE_OPERAND_FLAG);
221 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
223 id->byte_size_operation = ((op_order & BYTE_SIZE_OPERAND_FLAG) != 0);
228 void InstructionTable::SetTableRange(InstructionType type,
233 for (byte b = start; b <= end; b++) {
234 InstructionDesc* id = &instructions_[b];
235 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
238 id->byte_size_operation = byte_size;
243 void InstructionTable::AddJumpConditionalShort() {
244 for (byte b = 0x70; b <= 0x7F; b++) {
245 InstructionDesc* id = &instructions_[b];
246 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
247 id->mnem = NULL; // Computed depending on condition code.
248 id->type = JUMP_CONDITIONAL_SHORT_INSTR;
253 static v8::base::LazyInstance<InstructionTable>::type instruction_table =
254 LAZY_INSTANCE_INITIALIZER;
257 static const InstructionDesc cmov_instructions[16] = {
258 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
259 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
260 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
261 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
262 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
263 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
264 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
265 {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
266 {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
267 {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
268 {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
269 {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
270 {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
271 {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
272 {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
273 {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
277 //------------------------------------------------------------------------------
278 // DisassemblerX64 implementation.
280 enum UnimplementedOpcodeAction {
281 CONTINUE_ON_UNIMPLEMENTED_OPCODE,
282 ABORT_ON_UNIMPLEMENTED_OPCODE
286 // A new DisassemblerX64 object is created to disassemble each instruction.
287 // The object can only disassemble a single instruction.
288 class DisassemblerX64 {
290 DisassemblerX64(const NameConverter& converter,
291 UnimplementedOpcodeAction unimplemented_action =
292 ABORT_ON_UNIMPLEMENTED_OPCODE)
293 : converter_(converter),
295 abort_on_unimplemented_(unimplemented_action ==
296 ABORT_ON_UNIMPLEMENTED_OPCODE),
303 byte_size_operand_(false),
304 instruction_table_(instruction_table.Pointer()) {
305 tmp_buffer_[0] = '\0';
308 virtual ~DisassemblerX64() {
311 // Writes one disassembled instruction into 'buffer' (0-terminated).
312 // Returns the length of the disassembled machine instruction in bytes.
313 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
317 OPERAND_BYTE_SIZE = 0,
318 OPERAND_WORD_SIZE = 1,
319 OPERAND_DOUBLEWORD_SIZE = 2,
320 OPERAND_QUADWORD_SIZE = 3
323 const NameConverter& converter_;
324 v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
325 unsigned int tmp_buffer_pos_;
326 bool abort_on_unimplemented_;
329 byte operand_size_; // 0x66 or (if no group 3 prefix is present) 0x0.
330 byte group_1_prefix_; // 0xF2, 0xF3, or (if no group 1 prefix is present) 0.
331 byte vex_byte0_; // 0xc4 or 0xc5
333 byte vex_byte2_; // only for 3 bytes vex prefix
334 // Byte size operand override.
335 bool byte_size_operand_;
336 const InstructionTable* const instruction_table_;
338 void setRex(byte rex) {
339 DCHECK_EQ(0x40, rex & 0xF0);
343 bool rex() { return rex_ != 0; }
345 bool rex_b() { return (rex_ & 0x01) != 0; }
347 // Actual number of base register given the low bits and the rex.b state.
348 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); }
350 bool rex_x() { return (rex_ & 0x02) != 0; }
352 bool rex_r() { return (rex_ & 0x04) != 0; }
354 bool rex_w() { return (rex_ & 0x08) != 0; }
357 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
358 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
359 return (checked & 4) != 1;
363 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
364 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
365 return (checked & 3) == 1;
369 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
370 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
371 return (checked & 3) == 2;
375 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
376 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
377 return (checked & 3) == 3;
381 if (vex_byte0_ == VEX2_PREFIX) return true;
382 return (vex_byte1_ & 3) == 1;
386 if (vex_byte0_ == VEX2_PREFIX) return false;
387 return (vex_byte1_ & 3) == 2;
391 if (vex_byte0_ == VEX2_PREFIX) return false;
392 return (vex_byte1_ & 3) == 3;
396 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
397 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
398 return ~(checked >> 3) & 0xf;
401 OperandSize operand_size() {
402 if (byte_size_operand_) return OPERAND_BYTE_SIZE;
403 if (rex_w()) return OPERAND_QUADWORD_SIZE;
404 if (operand_size_ != 0) return OPERAND_WORD_SIZE;
405 return OPERAND_DOUBLEWORD_SIZE;
408 char operand_size_code() {
409 return "bwlq"[operand_size()];
412 char float_size_code() { return "sd"[rex_w()]; }
414 const char* NameOfCPURegister(int reg) const {
415 return converter_.NameOfCPURegister(reg);
418 const char* NameOfByteCPURegister(int reg) const {
419 return converter_.NameOfByteCPURegister(reg);
422 const char* NameOfXMMRegister(int reg) const {
423 return converter_.NameOfXMMRegister(reg);
426 const char* NameOfAddress(byte* addr) const {
427 return converter_.NameOfAddress(addr);
430 // Disassembler helper functions.
431 void get_modrm(byte data,
435 *mod = (data >> 6) & 3;
436 *regop = ((data & 0x38) >> 3) | (rex_r() ? 8 : 0);
437 *rm = (data & 7) | (rex_b() ? 8 : 0);
440 void get_sib(byte data,
444 *scale = (data >> 6) & 3;
445 *index = ((data >> 3) & 7) | (rex_x() ? 8 : 0);
446 *base = (data & 7) | (rex_b() ? 8 : 0);
449 typedef const char* (DisassemblerX64::*RegisterNameMapping)(int reg) const;
451 int PrintRightOperandHelper(byte* modrmp,
452 RegisterNameMapping register_name);
453 int PrintRightOperand(byte* modrmp);
454 int PrintRightByteOperand(byte* modrmp);
455 int PrintRightXMMOperand(byte* modrmp);
456 int PrintOperands(const char* mnem,
457 OperandType op_order,
459 int PrintImmediate(byte* data, OperandSize size);
460 int PrintImmediateOp(byte* data);
461 const char* TwoByteMnemonic(byte opcode);
462 int TwoByteOpcodeInstruction(byte* data);
463 int F6F7Instruction(byte* data);
464 int ShiftInstruction(byte* data);
465 int JumpShort(byte* data);
466 int JumpConditional(byte* data);
467 int JumpConditionalShort(byte* data);
468 int SetCC(byte* data);
469 int FPUInstruction(byte* data);
470 int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
471 int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
472 int AVXInstruction(byte* data);
473 void AppendToBuffer(const char* format, ...);
475 void UnimplementedInstruction() {
476 if (abort_on_unimplemented_) {
479 AppendToBuffer("'Unimplemented Instruction'");
485 void DisassemblerX64::AppendToBuffer(const char* format, ...) {
486 v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
488 va_start(args, format);
489 int result = v8::internal::VSNPrintF(buf, format, args);
491 tmp_buffer_pos_ += result;
495 int DisassemblerX64::PrintRightOperandHelper(
497 RegisterNameMapping direct_register_name) {
499 get_modrm(*modrmp, &mod, ®op, &rm);
500 RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
501 &DisassemblerX64::NameOfCPURegister;
505 int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 1);
506 AppendToBuffer("[rip+0x%x]", disp);
508 } else if ((rm & 7) == 4) {
509 // Codes for SIB byte.
510 byte sib = *(modrmp + 1);
511 int scale, index, base;
512 get_sib(sib, &scale, &index, &base);
513 if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
514 // index == rsp means no index. Only use sib byte with no index for
516 AppendToBuffer("[%s]", NameOfCPURegister(base));
518 } else if (base == 5) {
519 // base == rbp means no base register (when mod == 0).
520 int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
521 AppendToBuffer("[%s*%d%s0x%x]",
522 NameOfCPURegister(index),
524 disp < 0 ? "-" : "+",
525 disp < 0 ? -disp : disp);
527 } else if (index != 4 && base != 5) {
528 // [base+index*scale]
529 AppendToBuffer("[%s+%s*%d]",
530 NameOfCPURegister(base),
531 NameOfCPURegister(index),
535 UnimplementedInstruction();
539 AppendToBuffer("[%s]", NameOfCPURegister(rm));
543 case 1: // fall through
546 byte sib = *(modrmp + 1);
547 int scale, index, base;
548 get_sib(sib, &scale, &index, &base);
549 int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 2)
550 : *reinterpret_cast<int8_t*>(modrmp + 2);
551 if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
552 AppendToBuffer("[%s%s0x%x]",
553 NameOfCPURegister(base),
554 disp < 0 ? "-" : "+",
555 disp < 0 ? -disp : disp);
557 AppendToBuffer("[%s+%s*%d%s0x%x]",
558 NameOfCPURegister(base),
559 NameOfCPURegister(index),
561 disp < 0 ? "-" : "+",
562 disp < 0 ? -disp : disp);
564 return mod == 2 ? 6 : 3;
567 int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 1)
568 : *reinterpret_cast<int8_t*>(modrmp + 1);
569 AppendToBuffer("[%s%s0x%x]",
570 NameOfCPURegister(rm),
571 disp < 0 ? "-" : "+",
572 disp < 0 ? -disp : disp);
573 return (mod == 2) ? 5 : 2;
577 AppendToBuffer("%s", (this->*register_name)(rm));
580 UnimplementedInstruction();
587 int DisassemblerX64::PrintImmediate(byte* data, OperandSize size) {
591 case OPERAND_BYTE_SIZE:
595 case OPERAND_WORD_SIZE:
596 value = *reinterpret_cast<int16_t*>(data);
599 case OPERAND_DOUBLEWORD_SIZE:
600 value = *reinterpret_cast<uint32_t*>(data);
603 case OPERAND_QUADWORD_SIZE:
604 value = *reinterpret_cast<int32_t*>(data);
609 value = 0; // Initialize variables on all paths to satisfy the compiler.
612 AppendToBuffer("%" V8_PTR_PREFIX "x", value);
617 int DisassemblerX64::PrintRightOperand(byte* modrmp) {
618 return PrintRightOperandHelper(modrmp,
619 &DisassemblerX64::NameOfCPURegister);
623 int DisassemblerX64::PrintRightByteOperand(byte* modrmp) {
624 return PrintRightOperandHelper(modrmp,
625 &DisassemblerX64::NameOfByteCPURegister);
629 int DisassemblerX64::PrintRightXMMOperand(byte* modrmp) {
630 return PrintRightOperandHelper(modrmp,
631 &DisassemblerX64::NameOfXMMRegister);
635 // Returns number of bytes used including the current *data.
636 // Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
637 int DisassemblerX64::PrintOperands(const char* mnem,
638 OperandType op_order,
642 get_modrm(modrm, &mod, ®op, &rm);
644 const char* register_name =
645 byte_size_operand_ ? NameOfByteCPURegister(regop)
646 : NameOfCPURegister(regop);
648 case REG_OPER_OP_ORDER: {
649 AppendToBuffer("%s%c %s,",
653 advance = byte_size_operand_ ? PrintRightByteOperand(data)
654 : PrintRightOperand(data);
657 case OPER_REG_OP_ORDER: {
658 AppendToBuffer("%s%c ", mnem, operand_size_code());
659 advance = byte_size_operand_ ? PrintRightByteOperand(data)
660 : PrintRightOperand(data);
661 AppendToBuffer(",%s", register_name);
672 // Returns number of bytes used by machine instruction, including *data byte.
673 // Writes immediate instructions to 'tmp_buffer_'.
674 int DisassemblerX64::PrintImmediateOp(byte* data) {
675 bool byte_size_immediate = (*data & 0x02) != 0;
676 byte modrm = *(data + 1);
678 get_modrm(modrm, &mod, ®op, &rm);
679 const char* mnem = "Imm???";
706 UnimplementedInstruction();
708 AppendToBuffer("%s%c ", mnem, operand_size_code());
709 int count = PrintRightOperand(data + 1);
710 AppendToBuffer(",0x");
711 OperandSize immediate_size =
712 byte_size_immediate ? OPERAND_BYTE_SIZE : operand_size();
713 count += PrintImmediate(data + 1 + count, immediate_size);
718 // Returns number of bytes used, including *data.
719 int DisassemblerX64::F6F7Instruction(byte* data) {
720 DCHECK(*data == 0xF7 || *data == 0xF6);
721 byte modrm = *(data + 1);
723 get_modrm(modrm, &mod, ®op, &rm);
724 if (mod == 3 && regop != 0) {
725 const char* mnem = NULL;
746 UnimplementedInstruction();
748 AppendToBuffer("%s%c %s",
751 NameOfCPURegister(rm));
753 } else if (regop == 0) {
754 AppendToBuffer("test%c ", operand_size_code());
755 int count = PrintRightOperand(data + 1); // Use name of 64-bit register.
756 AppendToBuffer(",0x");
757 count += PrintImmediate(data + 1 + count, operand_size());
760 UnimplementedInstruction();
766 int DisassemblerX64::ShiftInstruction(byte* data) {
767 byte op = *data & (~1);
769 if (op != 0xD0 && op != 0xD2 && op != 0xC0) {
770 UnimplementedInstruction();
775 byte modrm = *(data + count);
777 get_modrm(modrm, &mod, ®op, &rm);
778 regop &= 0x7; // The REX.R bit does not affect the operation.
779 const char* mnem = NULL;
803 UnimplementedInstruction();
806 DCHECK_NOT_NULL(mnem);
807 AppendToBuffer("%s%c ", mnem, operand_size_code());
809 count += PrintRightOperand(data + count);
811 AppendToBuffer(", cl");
818 imm8 = *(data + count);
821 AppendToBuffer(", %d", imm8);
827 // Returns number of bytes used, including *data.
828 int DisassemblerX64::JumpShort(byte* data) {
829 DCHECK_EQ(0xEB, *data);
830 byte b = *(data + 1);
831 byte* dest = data + static_cast<int8_t>(b) + 2;
832 AppendToBuffer("jmp %s", NameOfAddress(dest));
837 // Returns number of bytes used, including *data.
838 int DisassemblerX64::JumpConditional(byte* data) {
839 DCHECK_EQ(0x0F, *data);
840 byte cond = *(data + 1) & 0x0F;
841 byte* dest = data + *reinterpret_cast<int32_t*>(data + 2) + 6;
842 const char* mnem = conditional_code_suffix[cond];
843 AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
844 return 6; // includes 0x0F
848 // Returns number of bytes used, including *data.
849 int DisassemblerX64::JumpConditionalShort(byte* data) {
850 byte cond = *data & 0x0F;
851 byte b = *(data + 1);
852 byte* dest = data + static_cast<int8_t>(b) + 2;
853 const char* mnem = conditional_code_suffix[cond];
854 AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
859 // Returns number of bytes used, including *data.
860 int DisassemblerX64::SetCC(byte* data) {
861 DCHECK_EQ(0x0F, *data);
862 byte cond = *(data + 1) & 0x0F;
863 const char* mnem = conditional_code_suffix[cond];
864 AppendToBuffer("set%s%c ", mnem, operand_size_code());
865 PrintRightByteOperand(data + 2);
866 return 3; // includes 0x0F
870 int DisassemblerX64::AVXInstruction(byte* data) {
872 byte* current = data + 1;
873 if (vex_66() && vex_0f38()) {
874 int mod, regop, rm, vvvv = vex_vreg();
875 get_modrm(*current, &mod, ®op, &rm);
878 AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
879 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
880 current += PrintRightXMMOperand(current);
883 AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
884 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
885 current += PrintRightXMMOperand(current);
888 AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
889 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
890 current += PrintRightXMMOperand(current);
893 AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
894 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
895 current += PrintRightXMMOperand(current);
898 AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
899 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
900 current += PrintRightXMMOperand(current);
903 AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
904 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
905 current += PrintRightXMMOperand(current);
908 AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
909 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
910 current += PrintRightXMMOperand(current);
913 AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
914 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
915 current += PrintRightXMMOperand(current);
918 AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
919 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
920 current += PrintRightXMMOperand(current);
923 AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
924 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
925 current += PrintRightXMMOperand(current);
928 AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
929 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
930 current += PrintRightXMMOperand(current);
933 AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
934 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
935 current += PrintRightXMMOperand(current);
938 UnimplementedInstruction();
940 } else if (vex_f2() && vex_0f()) {
941 int mod, regop, rm, vvvv = vex_vreg();
942 get_modrm(*current, &mod, ®op, &rm);
945 AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
946 NameOfXMMRegister(vvvv));
947 current += PrintRightXMMOperand(current);
950 AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
951 NameOfXMMRegister(vvvv));
952 current += PrintRightXMMOperand(current);
955 AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
956 NameOfXMMRegister(vvvv));
957 current += PrintRightXMMOperand(current);
960 AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
961 NameOfXMMRegister(vvvv));
962 current += PrintRightXMMOperand(current);
965 UnimplementedInstruction();
968 UnimplementedInstruction();
971 return static_cast<int>(current - data);
975 // Returns number of bytes used, including *data.
976 int DisassemblerX64::FPUInstruction(byte* data) {
977 byte escape_opcode = *data;
978 DCHECK_EQ(0xD8, escape_opcode & 0xF8);
979 byte modrm_byte = *(data+1);
981 if (modrm_byte >= 0xC0) {
982 return RegisterFPUInstruction(escape_opcode, modrm_byte);
984 return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
988 int DisassemblerX64::MemoryFPUInstruction(int escape_opcode,
991 const char* mnem = "?";
992 int regop = (modrm_byte >> 3) & 0x7; // reg/op field of modrm byte.
993 switch (escape_opcode) {
994 case 0xD9: switch (regop) {
995 case 0: mnem = "fld_s"; break;
996 case 3: mnem = "fstp_s"; break;
997 case 7: mnem = "fstcw"; break;
998 default: UnimplementedInstruction();
1002 case 0xDB: switch (regop) {
1003 case 0: mnem = "fild_s"; break;
1004 case 1: mnem = "fisttp_s"; break;
1005 case 2: mnem = "fist_s"; break;
1006 case 3: mnem = "fistp_s"; break;
1007 default: UnimplementedInstruction();
1011 case 0xDD: switch (regop) {
1012 case 0: mnem = "fld_d"; break;
1013 case 3: mnem = "fstp_d"; break;
1014 default: UnimplementedInstruction();
1018 case 0xDF: switch (regop) {
1019 case 5: mnem = "fild_d"; break;
1020 case 7: mnem = "fistp_d"; break;
1021 default: UnimplementedInstruction();
1025 default: UnimplementedInstruction();
1027 AppendToBuffer("%s ", mnem);
1028 int count = PrintRightOperand(modrm_start);
1032 int DisassemblerX64::RegisterFPUInstruction(int escape_opcode,
1034 bool has_register = false; // Is the FPU register encoded in modrm_byte?
1035 const char* mnem = "?";
1037 switch (escape_opcode) {
1039 UnimplementedInstruction();
1043 switch (modrm_byte & 0xF8) {
1046 has_register = true;
1050 has_register = true;
1053 switch (modrm_byte) {
1054 case 0xE0: mnem = "fchs"; break;
1055 case 0xE1: mnem = "fabs"; break;
1056 case 0xE3: mnem = "fninit"; break;
1057 case 0xE4: mnem = "ftst"; break;
1058 case 0xE8: mnem = "fld1"; break;
1059 case 0xEB: mnem = "fldpi"; break;
1060 case 0xED: mnem = "fldln2"; break;
1061 case 0xEE: mnem = "fldz"; break;
1062 case 0xF0: mnem = "f2xm1"; break;
1063 case 0xF1: mnem = "fyl2x"; break;
1064 case 0xF2: mnem = "fptan"; break;
1065 case 0xF5: mnem = "fprem1"; break;
1066 case 0xF7: mnem = "fincstp"; break;
1067 case 0xF8: mnem = "fprem"; break;
1068 case 0xFC: mnem = "frndint"; break;
1069 case 0xFD: mnem = "fscale"; break;
1070 case 0xFE: mnem = "fsin"; break;
1071 case 0xFF: mnem = "fcos"; break;
1072 default: UnimplementedInstruction();
1078 if (modrm_byte == 0xE9) {
1081 UnimplementedInstruction();
1086 if ((modrm_byte & 0xF8) == 0xE8) {
1088 has_register = true;
1089 } else if (modrm_byte == 0xE2) {
1091 } else if (modrm_byte == 0xE3) {
1094 UnimplementedInstruction();
1099 has_register = true;
1100 switch (modrm_byte & 0xF8) {
1101 case 0xC0: mnem = "fadd"; break;
1102 case 0xE8: mnem = "fsub"; break;
1103 case 0xC8: mnem = "fmul"; break;
1104 case 0xF8: mnem = "fdiv"; break;
1105 default: UnimplementedInstruction();
1110 has_register = true;
1111 switch (modrm_byte & 0xF8) {
1112 case 0xC0: mnem = "ffree"; break;
1113 case 0xD8: mnem = "fstp"; break;
1114 default: UnimplementedInstruction();
1119 if (modrm_byte == 0xD9) {
1122 has_register = true;
1123 switch (modrm_byte & 0xF8) {
1124 case 0xC0: mnem = "faddp"; break;
1125 case 0xE8: mnem = "fsubp"; break;
1126 case 0xC8: mnem = "fmulp"; break;
1127 case 0xF8: mnem = "fdivp"; break;
1128 default: UnimplementedInstruction();
1134 if (modrm_byte == 0xE0) {
1136 } else if ((modrm_byte & 0xF8) == 0xE8) {
1138 has_register = true;
1142 default: UnimplementedInstruction();
1146 AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
1148 AppendToBuffer("%s", mnem);
1155 // Handle all two-byte opcodes, which start with 0x0F.
1156 // These instructions may be affected by an 0x66, 0xF2, or 0xF3 prefix.
1157 // We do not use any three-byte opcodes, which start with 0x0F38 or 0x0F3A.
1158 int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
1159 byte opcode = *(data + 1);
1160 byte* current = data + 2;
1161 // At return, "current" points to the start of the next instruction.
1162 const char* mnemonic = TwoByteMnemonic(opcode);
1163 if (operand_size_ == 0x66) {
1164 // 0x66 0x0F prefix.
1166 if (opcode == 0x3A) {
1167 byte third_byte = *current;
1169 if (third_byte == 0x17) {
1170 get_modrm(*current, &mod, ®op, &rm);
1171 AppendToBuffer("extractps "); // reg/m32, xmm, imm8
1172 current += PrintRightOperand(current);
1173 AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
1175 } else if (third_byte == 0x0b) {
1176 get_modrm(*current, &mod, ®op, &rm);
1177 // roundsd xmm, xmm/m64, imm8
1178 AppendToBuffer("roundsd %s,", NameOfXMMRegister(regop));
1179 current += PrintRightXMMOperand(current);
1180 AppendToBuffer(",%d", (*current) & 3);
1183 UnimplementedInstruction();
1186 get_modrm(*current, &mod, ®op, &rm);
1187 if (opcode == 0x1f) {
1189 if (rm == 4) { // SIB byte present.
1192 if (mod == 1) { // Byte displacement.
1194 } else if (mod == 2) { // 32-bit displacement.
1196 } // else no immediate displacement.
1197 AppendToBuffer("nop");
1198 } else if (opcode == 0x28) {
1199 AppendToBuffer("movapd %s,", NameOfXMMRegister(regop));
1200 current += PrintRightXMMOperand(current);
1201 } else if (opcode == 0x29) {
1202 AppendToBuffer("movapd ");
1203 current += PrintRightXMMOperand(current);
1204 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1205 } else if (opcode == 0x6E) {
1206 AppendToBuffer("mov%c %s,",
1207 rex_w() ? 'q' : 'd',
1208 NameOfXMMRegister(regop));
1209 current += PrintRightOperand(current);
1210 } else if (opcode == 0x6F) {
1211 AppendToBuffer("movdqa %s,",
1212 NameOfXMMRegister(regop));
1213 current += PrintRightXMMOperand(current);
1214 } else if (opcode == 0x7E) {
1215 AppendToBuffer("mov%c ",
1216 rex_w() ? 'q' : 'd');
1217 current += PrintRightOperand(current);
1218 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1219 } else if (opcode == 0x7F) {
1220 AppendToBuffer("movdqa ");
1221 current += PrintRightXMMOperand(current);
1222 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1223 } else if (opcode == 0xD6) {
1224 AppendToBuffer("movq ");
1225 current += PrintRightXMMOperand(current);
1226 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1227 } else if (opcode == 0x50) {
1228 AppendToBuffer("movmskpd %s,", NameOfCPURegister(regop));
1229 current += PrintRightXMMOperand(current);
1230 } else if (opcode == 0x72) {
1232 AppendToBuffer("%s,%s,%d", (regop == 6) ? "pslld" : "psrld",
1233 NameOfXMMRegister(rm), *current & 0x7f);
1235 } else if (opcode == 0x73) {
1237 AppendToBuffer("%s,%s,%d", (regop == 6) ? "psllq" : "psrlq",
1238 NameOfXMMRegister(rm), *current & 0x7f);
1241 const char* mnemonic = "?";
1242 if (opcode == 0x54) {
1244 } else if (opcode == 0x56) {
1246 } else if (opcode == 0x57) {
1248 } else if (opcode == 0x2E) {
1249 mnemonic = "ucomisd";
1250 } else if (opcode == 0x2F) {
1251 mnemonic = "comisd";
1252 } else if (opcode == 0x76) {
1253 mnemonic = "pcmpeqd";
1255 UnimplementedInstruction();
1257 AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
1258 current += PrintRightXMMOperand(current);
1261 } else if (group_1_prefix_ == 0xF2) {
1262 // Beginning of instructions with prefix 0xF2.
1264 if (opcode == 0x11 || opcode == 0x10) {
1265 // MOVSD: Move scalar double-precision fp to/from/between XMM registers.
1266 AppendToBuffer("movsd ");
1268 get_modrm(*current, &mod, ®op, &rm);
1269 if (opcode == 0x11) {
1270 current += PrintRightXMMOperand(current);
1271 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1273 AppendToBuffer("%s,", NameOfXMMRegister(regop));
1274 current += PrintRightXMMOperand(current);
1276 } else if (opcode == 0x2A) {
1277 // CVTSI2SD: integer to XMM double conversion.
1279 get_modrm(*current, &mod, ®op, &rm);
1280 AppendToBuffer("%sd %s,", mnemonic, NameOfXMMRegister(regop));
1281 current += PrintRightOperand(current);
1282 } else if (opcode == 0x2C) {
1284 // Convert with truncation scalar double-precision FP to integer.
1286 get_modrm(*current, &mod, ®op, &rm);
1287 AppendToBuffer("cvttsd2si%c %s,",
1288 operand_size_code(), NameOfCPURegister(regop));
1289 current += PrintRightXMMOperand(current);
1290 } else if (opcode == 0x2D) {
1291 // CVTSD2SI: Convert scalar double-precision FP to integer.
1293 get_modrm(*current, &mod, ®op, &rm);
1294 AppendToBuffer("cvtsd2si%c %s,",
1295 operand_size_code(), NameOfCPURegister(regop));
1296 current += PrintRightXMMOperand(current);
1297 } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
1298 // XMM arithmetic. Mnemonic was retrieved at the start of this function.
1300 get_modrm(*current, &mod, ®op, &rm);
1301 AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
1302 current += PrintRightXMMOperand(current);
1303 } else if (opcode == 0xC2) {
1304 // Intel manual 2A, Table 3-18.
1306 get_modrm(*current, &mod, ®op, &rm);
1307 const char* const pseudo_op[] = {
1317 AppendToBuffer("%s %s,%s",
1318 pseudo_op[current[1]],
1319 NameOfXMMRegister(regop),
1320 NameOfXMMRegister(rm));
1323 UnimplementedInstruction();
1325 } else if (group_1_prefix_ == 0xF3) {
1326 // Instructions with prefix 0xF3.
1327 if (opcode == 0x11 || opcode == 0x10) {
1328 // MOVSS: Move scalar double-precision fp to/from/between XMM registers.
1329 AppendToBuffer("movss ");
1331 get_modrm(*current, &mod, ®op, &rm);
1332 if (opcode == 0x11) {
1333 current += PrintRightOperand(current);
1334 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1336 AppendToBuffer("%s,", NameOfXMMRegister(regop));
1337 current += PrintRightOperand(current);
1339 } else if (opcode == 0x2A) {
1340 // CVTSI2SS: integer to XMM single conversion.
1342 get_modrm(*current, &mod, ®op, &rm);
1343 AppendToBuffer("%ss %s,", mnemonic, NameOfXMMRegister(regop));
1344 current += PrintRightOperand(current);
1345 } else if (opcode == 0x2C) {
1347 // Convert with truncation scalar single-precision FP to dword integer.
1349 get_modrm(*current, &mod, ®op, &rm);
1350 AppendToBuffer("cvttss2si%c %s,",
1351 operand_size_code(), NameOfCPURegister(regop));
1352 current += PrintRightXMMOperand(current);
1353 } else if (opcode == 0x58) {
1355 get_modrm(*current, &mod, ®op, &rm);
1356 AppendToBuffer("addss %s,", NameOfXMMRegister(regop));
1357 current += PrintRightXMMOperand(current);
1358 } else if (opcode == 0x59) {
1360 get_modrm(*current, &mod, ®op, &rm);
1361 AppendToBuffer("mulss %s,", NameOfXMMRegister(regop));
1362 current += PrintRightXMMOperand(current);
1363 } else if (opcode == 0x5A) {
1365 // Convert scalar single-precision FP to scalar double-precision FP.
1367 get_modrm(*current, &mod, ®op, &rm);
1368 AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
1369 current += PrintRightXMMOperand(current);
1370 } else if (opcode == 0x5c) {
1372 get_modrm(*current, &mod, ®op, &rm);
1373 AppendToBuffer("subss %s,", NameOfXMMRegister(regop));
1374 current += PrintRightXMMOperand(current);
1375 } else if (opcode == 0x5e) {
1377 get_modrm(*current, &mod, ®op, &rm);
1378 AppendToBuffer("divss %s,", NameOfXMMRegister(regop));
1379 current += PrintRightXMMOperand(current);
1380 } else if (opcode == 0x7E) {
1382 get_modrm(*current, &mod, ®op, &rm);
1383 AppendToBuffer("movq %s,", NameOfXMMRegister(regop));
1384 current += PrintRightXMMOperand(current);
1386 UnimplementedInstruction();
1388 } else if (opcode == 0x1F) {
1391 get_modrm(*current, &mod, ®op, &rm);
1393 if (rm == 4) { // SIB byte present.
1396 if (mod == 1) { // Byte displacement.
1398 } else if (mod == 2) { // 32-bit displacement.
1400 } // else no immediate displacement.
1401 AppendToBuffer("nop");
1403 } else if (opcode == 0x28) {
1404 // movaps xmm, xmm/m128
1406 get_modrm(*current, &mod, ®op, &rm);
1407 AppendToBuffer("movaps %s,", NameOfXMMRegister(regop));
1408 current += PrintRightXMMOperand(current);
1410 } else if (opcode == 0x29) {
1411 // movaps xmm/m128, xmm
1413 get_modrm(*current, &mod, ®op, &rm);
1414 AppendToBuffer("movaps ");
1415 current += PrintRightXMMOperand(current);
1416 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1418 } else if (opcode == 0x2e) {
1420 get_modrm(*current, &mod, ®op, &rm);
1421 AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
1422 current += PrintRightXMMOperand(current);
1423 } else if (opcode == 0xA2) {
1425 AppendToBuffer("%s", mnemonic);
1427 } else if ((opcode & 0xF0) == 0x40) {
1428 // CMOVcc: conditional move.
1429 int condition = opcode & 0x0F;
1430 const InstructionDesc& idesc = cmov_instructions[condition];
1431 byte_size_operand_ = idesc.byte_size_operation;
1432 current += PrintOperands(idesc.mnem, idesc.op_order_, current);
1434 } else if (opcode >= 0x53 && opcode <= 0x5F) {
1435 const char* const pseudo_op[] = {
1451 get_modrm(*current, &mod, ®op, &rm);
1452 AppendToBuffer("%s %s,",
1453 pseudo_op[opcode - 0x53],
1454 NameOfXMMRegister(regop));
1455 current += PrintRightXMMOperand(current);
1457 } else if (opcode == 0xC6) {
1458 // shufps xmm, xmm/m128, imm8
1460 get_modrm(*current, &mod, ®op, &rm);
1461 AppendToBuffer("shufps %s, ", NameOfXMMRegister(regop));
1462 current += PrintRightXMMOperand(current);
1463 AppendToBuffer(", %d", (*current) & 3);
1466 } else if (opcode == 0x50) {
1467 // movmskps reg, xmm
1469 get_modrm(*current, &mod, ®op, &rm);
1470 AppendToBuffer("movmskps %s,", NameOfCPURegister(regop));
1471 current += PrintRightXMMOperand(current);
1473 } else if ((opcode & 0xF0) == 0x80) {
1474 // Jcc: Conditional jump (branch).
1475 current = data + JumpConditional(data);
1477 } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
1478 opcode == 0xB7 || opcode == 0xAF) {
1479 // Size-extending moves, IMUL.
1480 current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);
1482 } else if ((opcode & 0xF0) == 0x90) {
1483 // SETcc: Set byte on condition. Needs pointer to beginning of instruction.
1484 current = data + SetCC(data);
1486 } else if (opcode == 0xAB || opcode == 0xA5 || opcode == 0xAD) {
1487 // SHLD, SHRD (double-precision shift), BTS (bit set).
1488 AppendToBuffer("%s ", mnemonic);
1490 get_modrm(*current, &mod, ®op, &rm);
1491 current += PrintRightOperand(current);
1492 if (opcode == 0xAB) {
1493 AppendToBuffer(",%s", NameOfCPURegister(regop));
1495 AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
1497 } else if (opcode == 0xBD) {
1498 AppendToBuffer("%s%c ", mnemonic, operand_size_code());
1500 get_modrm(*current, &mod, ®op, &rm);
1501 AppendToBuffer("%s,", NameOfCPURegister(regop));
1502 current += PrintRightOperand(current);
1503 } else if (opcode == 0x0B) {
1504 AppendToBuffer("ud2");
1506 UnimplementedInstruction();
1508 return static_cast<int>(current - data);
1512 // Mnemonics for two-byte opcode instructions starting with 0x0F.
1513 // The argument is the second byte of the two-byte opcode.
1514 // Returns NULL if the instruction is not handled here.
1515 const char* DisassemblerX64::TwoByteMnemonic(byte opcode) {
1519 case 0x2A: // F2/F3 prefix.
1521 case 0x51: // F2 prefix.
1523 case 0x58: // F2 prefix.
1525 case 0x59: // F2 prefix.
1527 case 0x5A: // F2 prefix.
1529 case 0x5C: // F2 prefix.
1531 case 0x5E: // F2 prefix.
1559 // Disassembles the instruction at instr, and writes it into out_buffer.
1560 int DisassemblerX64::InstructionDecode(v8::internal::Vector<char> out_buffer,
1562 tmp_buffer_pos_ = 0; // starting to write as position 0
1564 bool processed = true; // Will be set to false if the current instruction
1565 // is not in 'instructions' table.
1568 // Scan for prefixes.
1571 if (current == OPERAND_SIZE_OVERRIDE_PREFIX) { // Group 3 prefix.
1572 operand_size_ = current;
1573 } else if ((current & 0xF0) == 0x40) { // REX prefix.
1575 if (rex_w()) AppendToBuffer("REX.W ");
1576 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3).
1577 group_1_prefix_ = current;
1578 } else if (current == VEX3_PREFIX) {
1579 vex_byte0_ = current;
1580 vex_byte1_ = *(data + 1);
1581 vex_byte2_ = *(data + 2);
1582 setRex(0x40 | (~(vex_byte1_ >> 5) & 7) | ((vex_byte2_ >> 4) & 8));
1584 } else if (current == VEX2_PREFIX) {
1585 vex_byte0_ = current;
1586 vex_byte1_ = *(data + 1);
1587 setRex(0x40 | (~(vex_byte1_ >> 5) & 4));
1589 } else { // Not a prefix - an opcode.
1595 // Decode AVX instructions.
1596 if (vex_byte0_ != 0) {
1598 data += AVXInstruction(data);
1600 const InstructionDesc& idesc = instruction_table_->Get(current);
1601 byte_size_operand_ = idesc.byte_size_operation;
1602 switch (idesc.type) {
1603 case ZERO_OPERANDS_INSTR:
1604 if (current >= 0xA4 && current <= 0xA7) {
1605 // String move or compare operations.
1606 if (group_1_prefix_ == REP_PREFIX) {
1608 AppendToBuffer("rep ");
1610 if (rex_w()) AppendToBuffer("REX.W ");
1611 AppendToBuffer("%s%c", idesc.mnem, operand_size_code());
1613 AppendToBuffer("%s", idesc.mnem, operand_size_code());
1618 case TWO_OPERANDS_INSTR:
1620 data += PrintOperands(idesc.mnem, idesc.op_order_, data);
1623 case JUMP_CONDITIONAL_SHORT_INSTR:
1624 data += JumpConditionalShort(data);
1627 case REGISTER_INSTR:
1628 AppendToBuffer("%s%c %s", idesc.mnem, operand_size_code(),
1629 NameOfCPURegister(base_reg(current & 0x07)));
1633 AppendToBuffer("%s %s", idesc.mnem,
1634 NameOfCPURegister(base_reg(current & 0x07)));
1637 case MOVE_REG_INSTR: {
1639 switch (operand_size()) {
1640 case OPERAND_WORD_SIZE:
1642 reinterpret_cast<byte*>(*reinterpret_cast<int16_t*>(data + 1));
1645 case OPERAND_DOUBLEWORD_SIZE:
1647 reinterpret_cast<byte*>(*reinterpret_cast<uint32_t*>(data + 1));
1650 case OPERAND_QUADWORD_SIZE:
1652 reinterpret_cast<byte*>(*reinterpret_cast<int64_t*>(data + 1));
1658 AppendToBuffer("mov%c %s,%s", operand_size_code(),
1659 NameOfCPURegister(base_reg(current & 0x07)),
1660 NameOfAddress(addr));
1664 case CALL_JUMP_INSTR: {
1665 byte* addr = data + *reinterpret_cast<int32_t*>(data + 1) + 5;
1666 AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
1671 case SHORT_IMMEDIATE_INSTR: {
1673 reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data + 1));
1674 AppendToBuffer("%s rax,%s", idesc.mnem, NameOfAddress(addr));
1684 UNIMPLEMENTED(); // This type is not implemented.
1688 // The first byte didn't match any of the simple opcodes, so we
1689 // need to do special processing on it.
1693 AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data + 1));
1697 case 0x69: // fall through
1700 count += PrintOperands("imul", REG_OPER_OP_ORDER, data + count);
1701 AppendToBuffer(",0x");
1702 if (*data == 0x69) {
1703 count += PrintImmediate(data + count, operand_size());
1705 count += PrintImmediate(data + count, OPERAND_BYTE_SIZE);
1711 case 0x81: // fall through
1712 case 0x83: // 0x81 with sign extension bit set
1713 data += PrintImmediateOp(data);
1717 data += TwoByteOpcodeInstruction(data);
1723 get_modrm(*data, &mod, ®op, &rm);
1725 AppendToBuffer("pop ");
1726 data += PrintRightOperand(data);
1734 get_modrm(*data, &mod, ®op, &rm);
1735 const char* mnem = NULL;
1755 AppendToBuffer(((regop <= 1) ? "%s%c " : "%s "),
1757 operand_size_code());
1758 data += PrintRightOperand(data);
1762 case 0xC7: // imm32, fall through
1765 bool is_byte = *data == 0xC6;
1768 AppendToBuffer("movb ");
1769 data += PrintRightByteOperand(data);
1770 int32_t imm = *data;
1771 AppendToBuffer(",0x%x", imm);
1774 AppendToBuffer("mov%c ", operand_size_code());
1775 data += PrintRightOperand(data);
1776 if (operand_size() == OPERAND_WORD_SIZE) {
1777 int16_t imm = *reinterpret_cast<int16_t*>(data);
1778 AppendToBuffer(",0x%x", imm);
1781 int32_t imm = *reinterpret_cast<int32_t*>(data);
1782 AppendToBuffer(",0x%x", imm);
1791 AppendToBuffer("cmpb ");
1792 data += PrintRightByteOperand(data);
1793 int32_t imm = *data;
1794 AppendToBuffer(",0x%x", imm);
1799 case 0x88: // 8bit, fall through
1802 bool is_byte = *data == 0x88;
1805 get_modrm(*data, &mod, ®op, &rm);
1807 AppendToBuffer("movb ");
1808 data += PrintRightByteOperand(data);
1809 AppendToBuffer(",%s", NameOfByteCPURegister(regop));
1811 AppendToBuffer("mov%c ", operand_size_code());
1812 data += PrintRightOperand(data);
1813 AppendToBuffer(",%s", NameOfCPURegister(regop));
1826 int reg = (*data & 0x7) | (rex_b() ? 8 : 0);
1828 AppendToBuffer("nop"); // Common name for xchg rax,rax.
1830 AppendToBuffer("xchg%c rax,%s",
1831 operand_size_code(),
1832 NameOfCPURegister(reg));
1853 // mov reg8,imm8 or mov reg32,imm32
1854 byte opcode = *data;
1856 bool is_32bit = (opcode >= 0xB8);
1857 int reg = (opcode & 0x7) | (rex_b() ? 8 : 0);
1859 AppendToBuffer("mov%c %s,",
1860 operand_size_code(),
1861 NameOfCPURegister(reg));
1862 data += PrintImmediate(data, OPERAND_DOUBLEWORD_SIZE);
1864 AppendToBuffer("movb %s,",
1865 NameOfByteCPURegister(reg));
1866 data += PrintImmediate(data, OPERAND_BYTE_SIZE);
1873 get_modrm(*data, &mod, ®op, &rm);
1875 AppendToBuffer("decb ");
1876 data += PrintRightByteOperand(data);
1878 UnimplementedInstruction();
1883 AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data + 1));
1888 AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
1892 case 0xA1: // Fall through.
1894 switch (operand_size()) {
1895 case OPERAND_DOUBLEWORD_SIZE: {
1896 const char* memory_location = NameOfAddress(
1897 reinterpret_cast<byte*>(
1898 *reinterpret_cast<int32_t*>(data + 1)));
1899 if (*data == 0xA1) { // Opcode 0xA1
1900 AppendToBuffer("movzxlq rax,(%s)", memory_location);
1901 } else { // Opcode 0xA3
1902 AppendToBuffer("movzxlq (%s),rax", memory_location);
1907 case OPERAND_QUADWORD_SIZE: {
1908 // New x64 instruction mov rax,(imm_64).
1909 const char* memory_location = NameOfAddress(
1910 *reinterpret_cast<byte**>(data + 1));
1911 if (*data == 0xA1) { // Opcode 0xA1
1912 AppendToBuffer("movq rax,(%s)", memory_location);
1913 } else { // Opcode 0xA3
1914 AppendToBuffer("movq (%s),rax", memory_location);
1920 UnimplementedInstruction();
1926 AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data + 1));
1932 switch (operand_size()) {
1933 case OPERAND_WORD_SIZE:
1934 value = *reinterpret_cast<uint16_t*>(data + 1);
1937 case OPERAND_DOUBLEWORD_SIZE:
1938 value = *reinterpret_cast<uint32_t*>(data + 1);
1941 case OPERAND_QUADWORD_SIZE:
1942 value = *reinterpret_cast<int32_t*>(data + 1);
1948 AppendToBuffer("test%c rax,0x%" V8_PTR_PREFIX "x",
1949 operand_size_code(),
1953 case 0xD1: // fall through
1954 case 0xD3: // fall through
1956 data += ShiftInstruction(data);
1958 case 0xD0: // fall through
1959 case 0xD2: // fall through
1961 byte_size_operand_ = true;
1962 data += ShiftInstruction(data);
1965 case 0xD9: // fall through
1966 case 0xDA: // fall through
1967 case 0xDB: // fall through
1968 case 0xDC: // fall through
1969 case 0xDD: // fall through
1970 case 0xDE: // fall through
1972 data += FPUInstruction(data);
1976 data += JumpShort(data);
1980 byte_size_operand_ = true; // fall through
1982 data += F6F7Instruction(data);
1986 AppendToBuffer("cmp al,0x%x", *reinterpret_cast<int8_t*>(data + 1));
1991 UnimplementedInstruction();
1996 if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
1997 tmp_buffer_[tmp_buffer_pos_] = '\0';
2000 int instr_len = static_cast<int>(data - instr);
2001 DCHECK(instr_len > 0); // Ensure progress.
2004 // Instruction bytes.
2005 for (byte* bp = instr; bp < data; bp++) {
2006 outp += v8::internal::SNPrintF(out_buffer + outp, "%02x", *bp);
2008 for (int i = 6 - instr_len; i >= 0; i--) {
2009 outp += v8::internal::SNPrintF(out_buffer + outp, " ");
2012 outp += v8::internal::SNPrintF(out_buffer + outp, " %s",
2013 tmp_buffer_.start());
2018 //------------------------------------------------------------------------------
2021 static const char* const cpu_regs[16] = {
2022 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2023 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2027 static const char* const byte_cpu_regs[16] = {
2028 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2029 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
2033 static const char* const xmm_regs[16] = {
2034 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2035 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
2039 const char* NameConverter::NameOfAddress(byte* addr) const {
2040 v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
2041 return tmp_buffer_.start();
2045 const char* NameConverter::NameOfConstant(byte* addr) const {
2046 return NameOfAddress(addr);
2050 const char* NameConverter::NameOfCPURegister(int reg) const {
2051 if (0 <= reg && reg < 16)
2052 return cpu_regs[reg];
2057 const char* NameConverter::NameOfByteCPURegister(int reg) const {
2058 if (0 <= reg && reg < 16)
2059 return byte_cpu_regs[reg];
2064 const char* NameConverter::NameOfXMMRegister(int reg) const {
2065 if (0 <= reg && reg < 16)
2066 return xmm_regs[reg];
2071 const char* NameConverter::NameInCode(byte* addr) const {
2072 // X64 does not embed debug strings at the moment.
2078 //------------------------------------------------------------------------------
2080 Disassembler::Disassembler(const NameConverter& converter)
2081 : converter_(converter) { }
2083 Disassembler::~Disassembler() { }
2086 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
2087 byte* instruction) {
2088 DisassemblerX64 d(converter_, CONTINUE_ON_UNIMPLEMENTED_OPCODE);
2089 return d.InstructionDecode(buffer, instruction);
2093 // The X64 assembler does not use constant pools.
2094 int Disassembler::ConstantPoolSizeAt(byte* instruction) {
2099 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
2100 NameConverter converter;
2101 Disassembler d(converter);
2102 for (byte* pc = begin; pc < end;) {
2103 v8::internal::EmbeddedVector<char, 128> buffer;
2106 pc += d.InstructionDecode(buffer, pc);
2107 fprintf(f, "%p", prev_pc);
2110 for (byte* bp = prev_pc; bp < pc; bp++) {
2111 fprintf(f, "%02x", *bp);
2113 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
2116 fprintf(f, " %s\n", buffer.start());
2120 } // namespace disasm
2122 #endif // V8_TARGET_ARCH_X64