1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
11 #if V8_TARGET_ARCH_X64
13 #include "src/base/lazy-instance.h"
14 #include "src/disasm.h"
20 // Operand size decides between 16, 32 and 64 bit operands.
21 REG_OPER_OP_ORDER = 1, // Register destination, operand source.
22 OPER_REG_OP_ORDER = 2, // Operand destination, register source.
23 // Fixed 8-bit operands.
24 BYTE_SIZE_OPERAND_FLAG = 4,
25 BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
26 BYTE_OPER_REG_OP_ORDER = OPER_REG_OP_ORDER | BYTE_SIZE_OPERAND_FLAG
30 //------------------------------------------------------------------
32 //------------------------------------------------------------------
34 int b; // -1 terminates, otherwise must be in range (0..255)
35 OperandType op_order_;
40 static const ByteMnemonic two_operands_instr[] = {
41 { 0x00, BYTE_OPER_REG_OP_ORDER, "add" },
42 { 0x01, OPER_REG_OP_ORDER, "add" },
43 { 0x02, BYTE_REG_OPER_OP_ORDER, "add" },
44 { 0x03, REG_OPER_OP_ORDER, "add" },
45 { 0x08, BYTE_OPER_REG_OP_ORDER, "or" },
46 { 0x09, OPER_REG_OP_ORDER, "or" },
47 { 0x0A, BYTE_REG_OPER_OP_ORDER, "or" },
48 { 0x0B, REG_OPER_OP_ORDER, "or" },
49 { 0x10, BYTE_OPER_REG_OP_ORDER, "adc" },
50 { 0x11, OPER_REG_OP_ORDER, "adc" },
51 { 0x12, BYTE_REG_OPER_OP_ORDER, "adc" },
52 { 0x13, REG_OPER_OP_ORDER, "adc" },
53 { 0x18, BYTE_OPER_REG_OP_ORDER, "sbb" },
54 { 0x19, OPER_REG_OP_ORDER, "sbb" },
55 { 0x1A, BYTE_REG_OPER_OP_ORDER, "sbb" },
56 { 0x1B, REG_OPER_OP_ORDER, "sbb" },
57 { 0x20, BYTE_OPER_REG_OP_ORDER, "and" },
58 { 0x21, OPER_REG_OP_ORDER, "and" },
59 { 0x22, BYTE_REG_OPER_OP_ORDER, "and" },
60 { 0x23, REG_OPER_OP_ORDER, "and" },
61 { 0x28, BYTE_OPER_REG_OP_ORDER, "sub" },
62 { 0x29, OPER_REG_OP_ORDER, "sub" },
63 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" },
64 { 0x2B, REG_OPER_OP_ORDER, "sub" },
65 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" },
66 { 0x31, OPER_REG_OP_ORDER, "xor" },
67 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" },
68 { 0x33, REG_OPER_OP_ORDER, "xor" },
69 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" },
70 { 0x39, OPER_REG_OP_ORDER, "cmp" },
71 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" },
72 { 0x3B, REG_OPER_OP_ORDER, "cmp" },
73 { 0x63, REG_OPER_OP_ORDER, "movsxl" },
74 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" },
75 { 0x85, REG_OPER_OP_ORDER, "test" },
76 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" },
77 { 0x87, REG_OPER_OP_ORDER, "xchg" },
78 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" },
79 { 0x89, OPER_REG_OP_ORDER, "mov" },
80 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" },
81 { 0x8B, REG_OPER_OP_ORDER, "mov" },
82 { 0x8D, REG_OPER_OP_ORDER, "lea" },
83 { -1, UNSET_OP_ORDER, "" }
87 static const ByteMnemonic zero_operands_instr[] = {
88 { 0xC3, UNSET_OP_ORDER, "ret" },
89 { 0xC9, UNSET_OP_ORDER, "leave" },
90 { 0xF4, UNSET_OP_ORDER, "hlt" },
91 { 0xFC, UNSET_OP_ORDER, "cld" },
92 { 0xCC, UNSET_OP_ORDER, "int3" },
93 { 0x60, UNSET_OP_ORDER, "pushad" },
94 { 0x61, UNSET_OP_ORDER, "popad" },
95 { 0x9C, UNSET_OP_ORDER, "pushfd" },
96 { 0x9D, UNSET_OP_ORDER, "popfd" },
97 { 0x9E, UNSET_OP_ORDER, "sahf" },
98 { 0x99, UNSET_OP_ORDER, "cdq" },
99 { 0x9B, UNSET_OP_ORDER, "fwait" },
100 { 0xA4, UNSET_OP_ORDER, "movs" },
101 { 0xA5, UNSET_OP_ORDER, "movs" },
102 { 0xA6, UNSET_OP_ORDER, "cmps" },
103 { 0xA7, UNSET_OP_ORDER, "cmps" },
104 { -1, UNSET_OP_ORDER, "" }
108 static const ByteMnemonic call_jump_instr[] = {
109 { 0xE8, UNSET_OP_ORDER, "call" },
110 { 0xE9, UNSET_OP_ORDER, "jmp" },
111 { -1, UNSET_OP_ORDER, "" }
115 static const ByteMnemonic short_immediate_instr[] = {
116 { 0x05, UNSET_OP_ORDER, "add" },
117 { 0x0D, UNSET_OP_ORDER, "or" },
118 { 0x15, UNSET_OP_ORDER, "adc" },
119 { 0x1D, UNSET_OP_ORDER, "sbb" },
120 { 0x25, UNSET_OP_ORDER, "and" },
121 { 0x2D, UNSET_OP_ORDER, "sub" },
122 { 0x35, UNSET_OP_ORDER, "xor" },
123 { 0x3D, UNSET_OP_ORDER, "cmp" },
124 { -1, UNSET_OP_ORDER, "" }
128 static const char* const conditional_code_suffix[] = {
129 "o", "no", "c", "nc", "z", "nz", "na", "a",
130 "s", "ns", "pe", "po", "l", "ge", "le", "g"
134 enum InstructionType {
138 JUMP_CONDITIONAL_SHORT_INSTR,
140 PUSHPOP_INSTR, // Has implicit 64-bit operand size.
143 SHORT_IMMEDIATE_INSTR
148 ESCAPE_PREFIX = 0x0F,
149 OPERAND_SIZE_OVERRIDE_PREFIX = 0x66,
150 ADDRESS_SIZE_OVERRIDE_PREFIX = 0x67,
155 REPEQ_PREFIX = REP_PREFIX
159 struct InstructionDesc {
161 InstructionType type;
162 OperandType op_order_;
163 bool byte_size_operation; // Fixed 8-bit operation.
167 class InstructionTable {
170 const InstructionDesc& Get(byte x) const {
171 return instructions_[x];
175 InstructionDesc instructions_[256];
178 void CopyTable(const ByteMnemonic bm[], InstructionType type);
179 void SetTableRange(InstructionType type, byte start, byte end, bool byte_size,
181 void AddJumpConditionalShort();
185 InstructionTable::InstructionTable() {
191 void InstructionTable::Clear() {
192 for (int i = 0; i < 256; i++) {
193 instructions_[i].mnem = "(bad)";
194 instructions_[i].type = NO_INSTR;
195 instructions_[i].op_order_ = UNSET_OP_ORDER;
196 instructions_[i].byte_size_operation = false;
201 void InstructionTable::Init() {
202 CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
203 CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
204 CopyTable(call_jump_instr, CALL_JUMP_INSTR);
205 CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
206 AddJumpConditionalShort();
207 SetTableRange(PUSHPOP_INSTR, 0x50, 0x57, false, "push");
208 SetTableRange(PUSHPOP_INSTR, 0x58, 0x5F, false, "pop");
209 SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, false, "mov");
213 void InstructionTable::CopyTable(const ByteMnemonic bm[],
214 InstructionType type) {
215 for (int i = 0; bm[i].b >= 0; i++) {
216 InstructionDesc* id = &instructions_[bm[i].b];
217 id->mnem = bm[i].mnem;
218 OperandType op_order = bm[i].op_order_;
220 static_cast<OperandType>(op_order & ~BYTE_SIZE_OPERAND_FLAG);
221 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
223 id->byte_size_operation = ((op_order & BYTE_SIZE_OPERAND_FLAG) != 0);
228 void InstructionTable::SetTableRange(InstructionType type,
233 for (byte b = start; b <= end; b++) {
234 InstructionDesc* id = &instructions_[b];
235 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
238 id->byte_size_operation = byte_size;
243 void InstructionTable::AddJumpConditionalShort() {
244 for (byte b = 0x70; b <= 0x7F; b++) {
245 InstructionDesc* id = &instructions_[b];
246 DCHECK_EQ(NO_INSTR, id->type); // Information not already entered
247 id->mnem = NULL; // Computed depending on condition code.
248 id->type = JUMP_CONDITIONAL_SHORT_INSTR;
253 static v8::base::LazyInstance<InstructionTable>::type instruction_table =
254 LAZY_INSTANCE_INITIALIZER;
257 static const InstructionDesc cmov_instructions[16] = {
258 {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
259 {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
260 {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
261 {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
262 {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
263 {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
264 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
265 {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
266 {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
267 {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
268 {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
269 {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
270 {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
271 {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
272 {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
273 {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
277 //------------------------------------------------------------------------------
278 // DisassemblerX64 implementation.
280 enum UnimplementedOpcodeAction {
281 CONTINUE_ON_UNIMPLEMENTED_OPCODE,
282 ABORT_ON_UNIMPLEMENTED_OPCODE
286 // A new DisassemblerX64 object is created to disassemble each instruction.
287 // The object can only disassemble a single instruction.
288 class DisassemblerX64 {
290 DisassemblerX64(const NameConverter& converter,
291 UnimplementedOpcodeAction unimplemented_action =
292 ABORT_ON_UNIMPLEMENTED_OPCODE)
293 : converter_(converter),
295 abort_on_unimplemented_(unimplemented_action ==
296 ABORT_ON_UNIMPLEMENTED_OPCODE),
303 byte_size_operand_(false),
304 instruction_table_(instruction_table.Pointer()) {
305 tmp_buffer_[0] = '\0';
308 virtual ~DisassemblerX64() {
311 // Writes one disassembled instruction into 'buffer' (0-terminated).
312 // Returns the length of the disassembled machine instruction in bytes.
313 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
317 OPERAND_BYTE_SIZE = 0,
318 OPERAND_WORD_SIZE = 1,
319 OPERAND_DOUBLEWORD_SIZE = 2,
320 OPERAND_QUADWORD_SIZE = 3
323 const NameConverter& converter_;
324 v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
325 unsigned int tmp_buffer_pos_;
326 bool abort_on_unimplemented_;
329 byte operand_size_; // 0x66 or (if no group 3 prefix is present) 0x0.
330 byte group_1_prefix_; // 0xF2, 0xF3, or (if no group 1 prefix is present) 0.
331 byte vex_byte0_; // 0xc4 or 0xc5
333 byte vex_byte2_; // only for 3 bytes vex prefix
334 // Byte size operand override.
335 bool byte_size_operand_;
336 const InstructionTable* const instruction_table_;
338 void setRex(byte rex) {
339 DCHECK_EQ(0x40, rex & 0xF0);
343 bool rex() { return rex_ != 0; }
345 bool rex_b() { return (rex_ & 0x01) != 0; }
347 // Actual number of base register given the low bits and the rex.b state.
348 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); }
350 bool rex_x() { return (rex_ & 0x02) != 0; }
352 bool rex_r() { return (rex_ & 0x04) != 0; }
354 bool rex_w() { return (rex_ & 0x08) != 0; }
357 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
358 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
359 return (checked & 4) != 1;
363 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
364 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
365 return (checked & 3) == 1;
369 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
370 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
371 return (checked & 3) == 2;
375 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
376 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
377 return (checked & 3) == 3;
381 if (vex_byte0_ == VEX2_PREFIX) return true;
382 return (vex_byte1_ & 3) == 1;
386 if (vex_byte0_ == VEX2_PREFIX) return false;
387 return (vex_byte1_ & 3) == 2;
391 if (vex_byte0_ == VEX2_PREFIX) return false;
392 return (vex_byte1_ & 3) == 3;
396 DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
397 byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
398 return ~(checked >> 3) & 0xf;
401 OperandSize operand_size() {
402 if (byte_size_operand_) return OPERAND_BYTE_SIZE;
403 if (rex_w()) return OPERAND_QUADWORD_SIZE;
404 if (operand_size_ != 0) return OPERAND_WORD_SIZE;
405 return OPERAND_DOUBLEWORD_SIZE;
408 char operand_size_code() {
409 return "bwlq"[operand_size()];
412 char float_size_code() { return "sd"[rex_w()]; }
414 const char* NameOfCPURegister(int reg) const {
415 return converter_.NameOfCPURegister(reg);
418 const char* NameOfByteCPURegister(int reg) const {
419 return converter_.NameOfByteCPURegister(reg);
422 const char* NameOfXMMRegister(int reg) const {
423 return converter_.NameOfXMMRegister(reg);
426 const char* NameOfAddress(byte* addr) const {
427 return converter_.NameOfAddress(addr);
430 // Disassembler helper functions.
431 void get_modrm(byte data,
435 *mod = (data >> 6) & 3;
436 *regop = ((data & 0x38) >> 3) | (rex_r() ? 8 : 0);
437 *rm = (data & 7) | (rex_b() ? 8 : 0);
440 void get_sib(byte data,
444 *scale = (data >> 6) & 3;
445 *index = ((data >> 3) & 7) | (rex_x() ? 8 : 0);
446 *base = (data & 7) | (rex_b() ? 8 : 0);
449 typedef const char* (DisassemblerX64::*RegisterNameMapping)(int reg) const;
451 int PrintRightOperandHelper(byte* modrmp,
452 RegisterNameMapping register_name);
453 int PrintRightOperand(byte* modrmp);
454 int PrintRightByteOperand(byte* modrmp);
455 int PrintRightXMMOperand(byte* modrmp);
456 int PrintOperands(const char* mnem,
457 OperandType op_order,
459 int PrintImmediate(byte* data, OperandSize size);
460 int PrintImmediateOp(byte* data);
461 const char* TwoByteMnemonic(byte opcode);
462 int TwoByteOpcodeInstruction(byte* data);
463 int F6F7Instruction(byte* data);
464 int ShiftInstruction(byte* data);
465 int JumpShort(byte* data);
466 int JumpConditional(byte* data);
467 int JumpConditionalShort(byte* data);
468 int SetCC(byte* data);
469 int FPUInstruction(byte* data);
470 int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
471 int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
472 int AVXInstruction(byte* data);
473 void AppendToBuffer(const char* format, ...);
475 void UnimplementedInstruction() {
476 if (abort_on_unimplemented_) {
479 AppendToBuffer("'Unimplemented Instruction'");
485 void DisassemblerX64::AppendToBuffer(const char* format, ...) {
486 v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
488 va_start(args, format);
489 int result = v8::internal::VSNPrintF(buf, format, args);
491 tmp_buffer_pos_ += result;
495 int DisassemblerX64::PrintRightOperandHelper(
497 RegisterNameMapping direct_register_name) {
499 get_modrm(*modrmp, &mod, ®op, &rm);
500 RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
501 &DisassemblerX64::NameOfCPURegister;
505 int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 1);
506 AppendToBuffer("[rip+0x%x]", disp);
508 } else if ((rm & 7) == 4) {
509 // Codes for SIB byte.
510 byte sib = *(modrmp + 1);
511 int scale, index, base;
512 get_sib(sib, &scale, &index, &base);
513 if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
514 // index == rsp means no index. Only use sib byte with no index for
516 AppendToBuffer("[%s]", NameOfCPURegister(base));
518 } else if (base == 5) {
519 // base == rbp means no base register (when mod == 0).
520 int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
521 AppendToBuffer("[%s*%d%s0x%x]",
522 NameOfCPURegister(index),
524 disp < 0 ? "-" : "+",
525 disp < 0 ? -disp : disp);
527 } else if (index != 4 && base != 5) {
528 // [base+index*scale]
529 AppendToBuffer("[%s+%s*%d]",
530 NameOfCPURegister(base),
531 NameOfCPURegister(index),
535 UnimplementedInstruction();
539 AppendToBuffer("[%s]", NameOfCPURegister(rm));
543 case 1: // fall through
546 byte sib = *(modrmp + 1);
547 int scale, index, base;
548 get_sib(sib, &scale, &index, &base);
549 int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 2)
550 : *reinterpret_cast<int8_t*>(modrmp + 2);
551 if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
552 AppendToBuffer("[%s%s0x%x]",
553 NameOfCPURegister(base),
554 disp < 0 ? "-" : "+",
555 disp < 0 ? -disp : disp);
557 AppendToBuffer("[%s+%s*%d%s0x%x]",
558 NameOfCPURegister(base),
559 NameOfCPURegister(index),
561 disp < 0 ? "-" : "+",
562 disp < 0 ? -disp : disp);
564 return mod == 2 ? 6 : 3;
567 int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 1)
568 : *reinterpret_cast<int8_t*>(modrmp + 1);
569 AppendToBuffer("[%s%s0x%x]",
570 NameOfCPURegister(rm),
571 disp < 0 ? "-" : "+",
572 disp < 0 ? -disp : disp);
573 return (mod == 2) ? 5 : 2;
577 AppendToBuffer("%s", (this->*register_name)(rm));
580 UnimplementedInstruction();
587 int DisassemblerX64::PrintImmediate(byte* data, OperandSize size) {
591 case OPERAND_BYTE_SIZE:
595 case OPERAND_WORD_SIZE:
596 value = *reinterpret_cast<int16_t*>(data);
599 case OPERAND_DOUBLEWORD_SIZE:
600 value = *reinterpret_cast<uint32_t*>(data);
603 case OPERAND_QUADWORD_SIZE:
604 value = *reinterpret_cast<int32_t*>(data);
609 value = 0; // Initialize variables on all paths to satisfy the compiler.
612 AppendToBuffer("%" V8_PTR_PREFIX "x", value);
617 int DisassemblerX64::PrintRightOperand(byte* modrmp) {
618 return PrintRightOperandHelper(modrmp,
619 &DisassemblerX64::NameOfCPURegister);
623 int DisassemblerX64::PrintRightByteOperand(byte* modrmp) {
624 return PrintRightOperandHelper(modrmp,
625 &DisassemblerX64::NameOfByteCPURegister);
629 int DisassemblerX64::PrintRightXMMOperand(byte* modrmp) {
630 return PrintRightOperandHelper(modrmp,
631 &DisassemblerX64::NameOfXMMRegister);
635 // Returns number of bytes used including the current *data.
636 // Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
637 int DisassemblerX64::PrintOperands(const char* mnem,
638 OperandType op_order,
642 get_modrm(modrm, &mod, ®op, &rm);
644 const char* register_name =
645 byte_size_operand_ ? NameOfByteCPURegister(regop)
646 : NameOfCPURegister(regop);
648 case REG_OPER_OP_ORDER: {
649 AppendToBuffer("%s%c %s,",
653 advance = byte_size_operand_ ? PrintRightByteOperand(data)
654 : PrintRightOperand(data);
657 case OPER_REG_OP_ORDER: {
658 AppendToBuffer("%s%c ", mnem, operand_size_code());
659 advance = byte_size_operand_ ? PrintRightByteOperand(data)
660 : PrintRightOperand(data);
661 AppendToBuffer(",%s", register_name);
672 // Returns number of bytes used by machine instruction, including *data byte.
673 // Writes immediate instructions to 'tmp_buffer_'.
674 int DisassemblerX64::PrintImmediateOp(byte* data) {
675 bool byte_size_immediate = (*data & 0x02) != 0;
676 byte modrm = *(data + 1);
678 get_modrm(modrm, &mod, ®op, &rm);
679 const char* mnem = "Imm???";
706 UnimplementedInstruction();
708 AppendToBuffer("%s%c ", mnem, operand_size_code());
709 int count = PrintRightOperand(data + 1);
710 AppendToBuffer(",0x");
711 OperandSize immediate_size =
712 byte_size_immediate ? OPERAND_BYTE_SIZE : operand_size();
713 count += PrintImmediate(data + 1 + count, immediate_size);
718 // Returns number of bytes used, including *data.
719 int DisassemblerX64::F6F7Instruction(byte* data) {
720 DCHECK(*data == 0xF7 || *data == 0xF6);
721 byte modrm = *(data + 1);
723 get_modrm(modrm, &mod, ®op, &rm);
724 if (mod == 3 && regop != 0) {
725 const char* mnem = NULL;
746 UnimplementedInstruction();
748 AppendToBuffer("%s%c %s",
751 NameOfCPURegister(rm));
753 } else if (regop == 0) {
754 AppendToBuffer("test%c ", operand_size_code());
755 int count = PrintRightOperand(data + 1); // Use name of 64-bit register.
756 AppendToBuffer(",0x");
757 count += PrintImmediate(data + 1 + count, operand_size());
760 UnimplementedInstruction();
766 int DisassemblerX64::ShiftInstruction(byte* data) {
767 byte op = *data & (~1);
769 if (op != 0xD0 && op != 0xD2 && op != 0xC0) {
770 UnimplementedInstruction();
775 byte modrm = *(data + count);
777 get_modrm(modrm, &mod, ®op, &rm);
778 regop &= 0x7; // The REX.R bit does not affect the operation.
779 const char* mnem = NULL;
803 UnimplementedInstruction();
806 DCHECK_NOT_NULL(mnem);
807 AppendToBuffer("%s%c ", mnem, operand_size_code());
809 count += PrintRightOperand(data + count);
811 AppendToBuffer(", cl");
818 imm8 = *(data + count);
821 AppendToBuffer(", %d", imm8);
827 // Returns number of bytes used, including *data.
828 int DisassemblerX64::JumpShort(byte* data) {
829 DCHECK_EQ(0xEB, *data);
830 byte b = *(data + 1);
831 byte* dest = data + static_cast<int8_t>(b) + 2;
832 AppendToBuffer("jmp %s", NameOfAddress(dest));
837 // Returns number of bytes used, including *data.
838 int DisassemblerX64::JumpConditional(byte* data) {
839 DCHECK_EQ(0x0F, *data);
840 byte cond = *(data + 1) & 0x0F;
841 byte* dest = data + *reinterpret_cast<int32_t*>(data + 2) + 6;
842 const char* mnem = conditional_code_suffix[cond];
843 AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
844 return 6; // includes 0x0F
848 // Returns number of bytes used, including *data.
849 int DisassemblerX64::JumpConditionalShort(byte* data) {
850 byte cond = *data & 0x0F;
851 byte b = *(data + 1);
852 byte* dest = data + static_cast<int8_t>(b) + 2;
853 const char* mnem = conditional_code_suffix[cond];
854 AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
859 // Returns number of bytes used, including *data.
860 int DisassemblerX64::SetCC(byte* data) {
861 DCHECK_EQ(0x0F, *data);
862 byte cond = *(data + 1) & 0x0F;
863 const char* mnem = conditional_code_suffix[cond];
864 AppendToBuffer("set%s%c ", mnem, operand_size_code());
865 PrintRightByteOperand(data + 2);
866 return 3; // includes 0x0F
870 int DisassemblerX64::AVXInstruction(byte* data) {
872 byte* current = data + 1;
873 if (vex_66() && vex_0f38()) {
874 int mod, regop, rm, vvvv = vex_vreg();
875 get_modrm(*current, &mod, ®op, &rm);
878 AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
879 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
880 current += PrintRightXMMOperand(current);
883 AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
884 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
885 current += PrintRightXMMOperand(current);
888 AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
889 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
890 current += PrintRightXMMOperand(current);
893 AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
894 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
895 current += PrintRightXMMOperand(current);
898 AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
899 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
900 current += PrintRightXMMOperand(current);
903 AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
904 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
905 current += PrintRightXMMOperand(current);
908 AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
909 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
910 current += PrintRightXMMOperand(current);
913 AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
914 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
915 current += PrintRightXMMOperand(current);
918 AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
919 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
920 current += PrintRightXMMOperand(current);
923 AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
924 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
925 current += PrintRightXMMOperand(current);
928 AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
929 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
930 current += PrintRightXMMOperand(current);
933 AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
934 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
935 current += PrintRightXMMOperand(current);
938 UnimplementedInstruction();
940 } else if (vex_f2() && vex_0f()) {
941 int mod, regop, rm, vvvv = vex_vreg();
942 get_modrm(*current, &mod, ®op, &rm);
945 AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
946 NameOfXMMRegister(vvvv));
947 current += PrintRightXMMOperand(current);
950 AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
951 NameOfXMMRegister(vvvv));
952 current += PrintRightXMMOperand(current);
955 AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
956 NameOfXMMRegister(vvvv));
957 current += PrintRightXMMOperand(current);
960 AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
961 NameOfXMMRegister(vvvv));
962 current += PrintRightXMMOperand(current);
965 AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
966 NameOfXMMRegister(vvvv));
967 current += PrintRightXMMOperand(current);
970 AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
971 NameOfXMMRegister(vvvv));
972 current += PrintRightXMMOperand(current);
975 UnimplementedInstruction();
978 UnimplementedInstruction();
981 return static_cast<int>(current - data);
985 // Returns number of bytes used, including *data.
986 int DisassemblerX64::FPUInstruction(byte* data) {
987 byte escape_opcode = *data;
988 DCHECK_EQ(0xD8, escape_opcode & 0xF8);
989 byte modrm_byte = *(data+1);
991 if (modrm_byte >= 0xC0) {
992 return RegisterFPUInstruction(escape_opcode, modrm_byte);
994 return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
998 int DisassemblerX64::MemoryFPUInstruction(int escape_opcode,
1000 byte* modrm_start) {
1001 const char* mnem = "?";
1002 int regop = (modrm_byte >> 3) & 0x7; // reg/op field of modrm byte.
1003 switch (escape_opcode) {
1004 case 0xD9: switch (regop) {
1005 case 0: mnem = "fld_s"; break;
1006 case 3: mnem = "fstp_s"; break;
1007 case 7: mnem = "fstcw"; break;
1008 default: UnimplementedInstruction();
1012 case 0xDB: switch (regop) {
1013 case 0: mnem = "fild_s"; break;
1014 case 1: mnem = "fisttp_s"; break;
1015 case 2: mnem = "fist_s"; break;
1016 case 3: mnem = "fistp_s"; break;
1017 default: UnimplementedInstruction();
1021 case 0xDD: switch (regop) {
1022 case 0: mnem = "fld_d"; break;
1023 case 3: mnem = "fstp_d"; break;
1024 default: UnimplementedInstruction();
1028 case 0xDF: switch (regop) {
1029 case 5: mnem = "fild_d"; break;
1030 case 7: mnem = "fistp_d"; break;
1031 default: UnimplementedInstruction();
1035 default: UnimplementedInstruction();
1037 AppendToBuffer("%s ", mnem);
1038 int count = PrintRightOperand(modrm_start);
1042 int DisassemblerX64::RegisterFPUInstruction(int escape_opcode,
1044 bool has_register = false; // Is the FPU register encoded in modrm_byte?
1045 const char* mnem = "?";
1047 switch (escape_opcode) {
1049 UnimplementedInstruction();
1053 switch (modrm_byte & 0xF8) {
1056 has_register = true;
1060 has_register = true;
1063 switch (modrm_byte) {
1064 case 0xE0: mnem = "fchs"; break;
1065 case 0xE1: mnem = "fabs"; break;
1066 case 0xE3: mnem = "fninit"; break;
1067 case 0xE4: mnem = "ftst"; break;
1068 case 0xE8: mnem = "fld1"; break;
1069 case 0xEB: mnem = "fldpi"; break;
1070 case 0xED: mnem = "fldln2"; break;
1071 case 0xEE: mnem = "fldz"; break;
1072 case 0xF0: mnem = "f2xm1"; break;
1073 case 0xF1: mnem = "fyl2x"; break;
1074 case 0xF2: mnem = "fptan"; break;
1075 case 0xF5: mnem = "fprem1"; break;
1076 case 0xF7: mnem = "fincstp"; break;
1077 case 0xF8: mnem = "fprem"; break;
1078 case 0xFC: mnem = "frndint"; break;
1079 case 0xFD: mnem = "fscale"; break;
1080 case 0xFE: mnem = "fsin"; break;
1081 case 0xFF: mnem = "fcos"; break;
1082 default: UnimplementedInstruction();
1088 if (modrm_byte == 0xE9) {
1091 UnimplementedInstruction();
1096 if ((modrm_byte & 0xF8) == 0xE8) {
1098 has_register = true;
1099 } else if (modrm_byte == 0xE2) {
1101 } else if (modrm_byte == 0xE3) {
1104 UnimplementedInstruction();
1109 has_register = true;
1110 switch (modrm_byte & 0xF8) {
1111 case 0xC0: mnem = "fadd"; break;
1112 case 0xE8: mnem = "fsub"; break;
1113 case 0xC8: mnem = "fmul"; break;
1114 case 0xF8: mnem = "fdiv"; break;
1115 default: UnimplementedInstruction();
1120 has_register = true;
1121 switch (modrm_byte & 0xF8) {
1122 case 0xC0: mnem = "ffree"; break;
1123 case 0xD8: mnem = "fstp"; break;
1124 default: UnimplementedInstruction();
1129 if (modrm_byte == 0xD9) {
1132 has_register = true;
1133 switch (modrm_byte & 0xF8) {
1134 case 0xC0: mnem = "faddp"; break;
1135 case 0xE8: mnem = "fsubp"; break;
1136 case 0xC8: mnem = "fmulp"; break;
1137 case 0xF8: mnem = "fdivp"; break;
1138 default: UnimplementedInstruction();
1144 if (modrm_byte == 0xE0) {
1146 } else if ((modrm_byte & 0xF8) == 0xE8) {
1148 has_register = true;
1152 default: UnimplementedInstruction();
1156 AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
1158 AppendToBuffer("%s", mnem);
1165 // Handle all two-byte opcodes, which start with 0x0F.
1166 // These instructions may be affected by an 0x66, 0xF2, or 0xF3 prefix.
1167 // We do not use any three-byte opcodes, which start with 0x0F38 or 0x0F3A.
1168 int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
1169 byte opcode = *(data + 1);
1170 byte* current = data + 2;
1171 // At return, "current" points to the start of the next instruction.
1172 const char* mnemonic = TwoByteMnemonic(opcode);
1173 if (operand_size_ == 0x66) {
1174 // 0x66 0x0F prefix.
1176 if (opcode == 0x3A) {
1177 byte third_byte = *current;
1179 if (third_byte == 0x17) {
1180 get_modrm(*current, &mod, ®op, &rm);
1181 AppendToBuffer("extractps "); // reg/m32, xmm, imm8
1182 current += PrintRightOperand(current);
1183 AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
1185 } else if (third_byte == 0x0b) {
1186 get_modrm(*current, &mod, ®op, &rm);
1187 // roundsd xmm, xmm/m64, imm8
1188 AppendToBuffer("roundsd %s,", NameOfXMMRegister(regop));
1189 current += PrintRightXMMOperand(current);
1190 AppendToBuffer(",%d", (*current) & 3);
1192 } else if (third_byte == 0x16) {
1193 get_modrm(*current, &mod, ®op, &rm);
1194 AppendToBuffer("pextrd "); // reg/m32, xmm, imm8
1195 current += PrintRightOperand(current);
1196 AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
1198 } else if (third_byte == 0x22) {
1199 get_modrm(*current, &mod, ®op, &rm);
1200 AppendToBuffer("pinsrd "); // xmm, reg/m32, imm8
1201 AppendToBuffer(" %s,", NameOfXMMRegister(regop));
1202 current += PrintRightOperand(current);
1203 AppendToBuffer(",%d", (*current) & 3);
1206 UnimplementedInstruction();
1209 get_modrm(*current, &mod, ®op, &rm);
1210 if (opcode == 0x1f) {
1212 if (rm == 4) { // SIB byte present.
1215 if (mod == 1) { // Byte displacement.
1217 } else if (mod == 2) { // 32-bit displacement.
1219 } // else no immediate displacement.
1220 AppendToBuffer("nop");
1221 } else if (opcode == 0x28) {
1222 AppendToBuffer("movapd %s,", NameOfXMMRegister(regop));
1223 current += PrintRightXMMOperand(current);
1224 } else if (opcode == 0x29) {
1225 AppendToBuffer("movapd ");
1226 current += PrintRightXMMOperand(current);
1227 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1228 } else if (opcode == 0x6E) {
1229 AppendToBuffer("mov%c %s,",
1230 rex_w() ? 'q' : 'd',
1231 NameOfXMMRegister(regop));
1232 current += PrintRightOperand(current);
1233 } else if (opcode == 0x6F) {
1234 AppendToBuffer("movdqa %s,",
1235 NameOfXMMRegister(regop));
1236 current += PrintRightXMMOperand(current);
1237 } else if (opcode == 0x7E) {
1238 AppendToBuffer("mov%c ",
1239 rex_w() ? 'q' : 'd');
1240 current += PrintRightOperand(current);
1241 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1242 } else if (opcode == 0x7F) {
1243 AppendToBuffer("movdqa ");
1244 current += PrintRightXMMOperand(current);
1245 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1246 } else if (opcode == 0xD6) {
1247 AppendToBuffer("movq ");
1248 current += PrintRightXMMOperand(current);
1249 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1250 } else if (opcode == 0x50) {
1251 AppendToBuffer("movmskpd %s,", NameOfCPURegister(regop));
1252 current += PrintRightXMMOperand(current);
1253 } else if (opcode == 0x72) {
1255 AppendToBuffer("%s %s,%d", (regop == 6) ? "pslld" : "psrld",
1256 NameOfXMMRegister(rm), *current & 0x7f);
1258 } else if (opcode == 0x73) {
1260 AppendToBuffer("%s %s,%d", (regop == 6) ? "psllq" : "psrlq",
1261 NameOfXMMRegister(rm), *current & 0x7f);
1264 const char* mnemonic = "?";
1265 if (opcode == 0x54) {
1267 } else if (opcode == 0x56) {
1269 } else if (opcode == 0x57) {
1271 } else if (opcode == 0x2E) {
1272 mnemonic = "ucomisd";
1273 } else if (opcode == 0x2F) {
1274 mnemonic = "comisd";
1275 } else if (opcode == 0x76) {
1276 mnemonic = "pcmpeqd";
1277 } else if (opcode == 0x62) {
1278 mnemonic = "punpckldq";
1279 } else if (opcode == 0x6A) {
1280 mnemonic = "punpckhdq";
1282 UnimplementedInstruction();
1284 AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
1285 current += PrintRightXMMOperand(current);
1288 } else if (group_1_prefix_ == 0xF2) {
1289 // Beginning of instructions with prefix 0xF2.
1291 if (opcode == 0x11 || opcode == 0x10) {
1292 // MOVSD: Move scalar double-precision fp to/from/between XMM registers.
1293 AppendToBuffer("movsd ");
1295 get_modrm(*current, &mod, ®op, &rm);
1296 if (opcode == 0x11) {
1297 current += PrintRightXMMOperand(current);
1298 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1300 AppendToBuffer("%s,", NameOfXMMRegister(regop));
1301 current += PrintRightXMMOperand(current);
1303 } else if (opcode == 0x2A) {
1304 // CVTSI2SD: integer to XMM double conversion.
1306 get_modrm(*current, &mod, ®op, &rm);
1307 AppendToBuffer("%sd %s,", mnemonic, NameOfXMMRegister(regop));
1308 current += PrintRightOperand(current);
1309 } else if (opcode == 0x2C) {
1311 // Convert with truncation scalar double-precision FP to integer.
1313 get_modrm(*current, &mod, ®op, &rm);
1314 AppendToBuffer("cvttsd2si%c %s,",
1315 operand_size_code(), NameOfCPURegister(regop));
1316 current += PrintRightXMMOperand(current);
1317 } else if (opcode == 0x2D) {
1318 // CVTSD2SI: Convert scalar double-precision FP to integer.
1320 get_modrm(*current, &mod, ®op, &rm);
1321 AppendToBuffer("cvtsd2si%c %s,",
1322 operand_size_code(), NameOfCPURegister(regop));
1323 current += PrintRightXMMOperand(current);
1324 } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
1325 // XMM arithmetic. Mnemonic was retrieved at the start of this function.
1327 get_modrm(*current, &mod, ®op, &rm);
1328 AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
1329 current += PrintRightXMMOperand(current);
1330 } else if (opcode == 0xC2) {
1331 // Intel manual 2A, Table 3-18.
1333 get_modrm(*current, &mod, ®op, &rm);
1334 const char* const pseudo_op[] = {
1344 AppendToBuffer("%s %s,%s",
1345 pseudo_op[current[1]],
1346 NameOfXMMRegister(regop),
1347 NameOfXMMRegister(rm));
1350 UnimplementedInstruction();
1352 } else if (group_1_prefix_ == 0xF3) {
1353 // Instructions with prefix 0xF3.
1354 if (opcode == 0x11 || opcode == 0x10) {
1355 // MOVSS: Move scalar double-precision fp to/from/between XMM registers.
1356 AppendToBuffer("movss ");
1358 get_modrm(*current, &mod, ®op, &rm);
1359 if (opcode == 0x11) {
1360 current += PrintRightOperand(current);
1361 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1363 AppendToBuffer("%s,", NameOfXMMRegister(regop));
1364 current += PrintRightOperand(current);
1366 } else if (opcode == 0x2A) {
1367 // CVTSI2SS: integer to XMM single conversion.
1369 get_modrm(*current, &mod, ®op, &rm);
1370 AppendToBuffer("%ss %s,", mnemonic, NameOfXMMRegister(regop));
1371 current += PrintRightOperand(current);
1372 } else if (opcode == 0x2C) {
1374 // Convert with truncation scalar single-precision FP to dword integer.
1376 get_modrm(*current, &mod, ®op, &rm);
1377 AppendToBuffer("cvttss2si%c %s,",
1378 operand_size_code(), NameOfCPURegister(regop));
1379 current += PrintRightXMMOperand(current);
1380 } else if (opcode == 0x58) {
1382 get_modrm(*current, &mod, ®op, &rm);
1383 AppendToBuffer("addss %s,", NameOfXMMRegister(regop));
1384 current += PrintRightXMMOperand(current);
1385 } else if (opcode == 0x59) {
1387 get_modrm(*current, &mod, ®op, &rm);
1388 AppendToBuffer("mulss %s,", NameOfXMMRegister(regop));
1389 current += PrintRightXMMOperand(current);
1390 } else if (opcode == 0x5A) {
1392 // Convert scalar single-precision FP to scalar double-precision FP.
1394 get_modrm(*current, &mod, ®op, &rm);
1395 AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
1396 current += PrintRightXMMOperand(current);
1397 } else if (opcode == 0x5c) {
1399 get_modrm(*current, &mod, ®op, &rm);
1400 AppendToBuffer("subss %s,", NameOfXMMRegister(regop));
1401 current += PrintRightXMMOperand(current);
1402 } else if (opcode == 0x5e) {
1404 get_modrm(*current, &mod, ®op, &rm);
1405 AppendToBuffer("divss %s,", NameOfXMMRegister(regop));
1406 current += PrintRightXMMOperand(current);
1407 } else if (opcode == 0x7E) {
1409 get_modrm(*current, &mod, ®op, &rm);
1410 AppendToBuffer("movq %s,", NameOfXMMRegister(regop));
1411 current += PrintRightXMMOperand(current);
1413 UnimplementedInstruction();
1415 } else if (opcode == 0x1F) {
1418 get_modrm(*current, &mod, ®op, &rm);
1420 if (rm == 4) { // SIB byte present.
1423 if (mod == 1) { // Byte displacement.
1425 } else if (mod == 2) { // 32-bit displacement.
1427 } // else no immediate displacement.
1428 AppendToBuffer("nop");
1430 } else if (opcode == 0x28) {
1431 // movaps xmm, xmm/m128
1433 get_modrm(*current, &mod, ®op, &rm);
1434 AppendToBuffer("movaps %s,", NameOfXMMRegister(regop));
1435 current += PrintRightXMMOperand(current);
1437 } else if (opcode == 0x29) {
1438 // movaps xmm/m128, xmm
1440 get_modrm(*current, &mod, ®op, &rm);
1441 AppendToBuffer("movaps ");
1442 current += PrintRightXMMOperand(current);
1443 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1445 } else if (opcode == 0x2e) {
1447 get_modrm(*current, &mod, ®op, &rm);
1448 AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
1449 current += PrintRightXMMOperand(current);
1450 } else if (opcode == 0xA2) {
1452 AppendToBuffer("%s", mnemonic);
1454 } else if ((opcode & 0xF0) == 0x40) {
1455 // CMOVcc: conditional move.
1456 int condition = opcode & 0x0F;
1457 const InstructionDesc& idesc = cmov_instructions[condition];
1458 byte_size_operand_ = idesc.byte_size_operation;
1459 current += PrintOperands(idesc.mnem, idesc.op_order_, current);
1461 } else if (opcode >= 0x53 && opcode <= 0x5F) {
1462 const char* const pseudo_op[] = {
1478 get_modrm(*current, &mod, ®op, &rm);
1479 AppendToBuffer("%s %s,",
1480 pseudo_op[opcode - 0x53],
1481 NameOfXMMRegister(regop));
1482 current += PrintRightXMMOperand(current);
1484 } else if (opcode == 0xC6) {
1485 // shufps xmm, xmm/m128, imm8
1487 get_modrm(*current, &mod, ®op, &rm);
1488 AppendToBuffer("shufps %s, ", NameOfXMMRegister(regop));
1489 current += PrintRightXMMOperand(current);
1490 AppendToBuffer(", %d", (*current) & 3);
1493 } else if (opcode == 0x50) {
1494 // movmskps reg, xmm
1496 get_modrm(*current, &mod, ®op, &rm);
1497 AppendToBuffer("movmskps %s,", NameOfCPURegister(regop));
1498 current += PrintRightXMMOperand(current);
1500 } else if ((opcode & 0xF0) == 0x80) {
1501 // Jcc: Conditional jump (branch).
1502 current = data + JumpConditional(data);
1504 } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
1505 opcode == 0xB7 || opcode == 0xAF) {
1506 // Size-extending moves, IMUL.
1507 current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);
1509 } else if ((opcode & 0xF0) == 0x90) {
1510 // SETcc: Set byte on condition. Needs pointer to beginning of instruction.
1511 current = data + SetCC(data);
1513 } else if (opcode == 0xAB || opcode == 0xA5 || opcode == 0xAD) {
1514 // SHLD, SHRD (double-precision shift), BTS (bit set).
1515 AppendToBuffer("%s ", mnemonic);
1517 get_modrm(*current, &mod, ®op, &rm);
1518 current += PrintRightOperand(current);
1519 if (opcode == 0xAB) {
1520 AppendToBuffer(",%s", NameOfCPURegister(regop));
1522 AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
1524 } else if (opcode == 0xBD) {
1525 AppendToBuffer("%s%c ", mnemonic, operand_size_code());
1527 get_modrm(*current, &mod, ®op, &rm);
1528 AppendToBuffer("%s,", NameOfCPURegister(regop));
1529 current += PrintRightOperand(current);
1530 } else if (opcode == 0x0B) {
1531 AppendToBuffer("ud2");
1533 UnimplementedInstruction();
1535 return static_cast<int>(current - data);
1539 // Mnemonics for two-byte opcode instructions starting with 0x0F.
1540 // The argument is the second byte of the two-byte opcode.
1541 // Returns NULL if the instruction is not handled here.
1542 const char* DisassemblerX64::TwoByteMnemonic(byte opcode) {
1546 case 0x2A: // F2/F3 prefix.
1548 case 0x51: // F2 prefix.
1550 case 0x58: // F2 prefix.
1552 case 0x59: // F2 prefix.
1554 case 0x5A: // F2 prefix.
1556 case 0x5D: // F2 prefix.
1558 case 0x5C: // F2 prefix.
1560 case 0x5E: // F2 prefix.
1562 case 0x5F: // F2 prefix.
1590 // Disassembles the instruction at instr, and writes it into out_buffer.
1591 int DisassemblerX64::InstructionDecode(v8::internal::Vector<char> out_buffer,
1593 tmp_buffer_pos_ = 0; // starting to write as position 0
1595 bool processed = true; // Will be set to false if the current instruction
1596 // is not in 'instructions' table.
1599 // Scan for prefixes.
1602 if (current == OPERAND_SIZE_OVERRIDE_PREFIX) { // Group 3 prefix.
1603 operand_size_ = current;
1604 } else if ((current & 0xF0) == 0x40) { // REX prefix.
1606 if (rex_w()) AppendToBuffer("REX.W ");
1607 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3).
1608 group_1_prefix_ = current;
1609 } else if (current == VEX3_PREFIX) {
1610 vex_byte0_ = current;
1611 vex_byte1_ = *(data + 1);
1612 vex_byte2_ = *(data + 2);
1613 setRex(0x40 | (~(vex_byte1_ >> 5) & 7) | ((vex_byte2_ >> 4) & 8));
1615 } else if (current == VEX2_PREFIX) {
1616 vex_byte0_ = current;
1617 vex_byte1_ = *(data + 1);
1618 setRex(0x40 | (~(vex_byte1_ >> 5) & 4));
1620 } else { // Not a prefix - an opcode.
1626 // Decode AVX instructions.
1627 if (vex_byte0_ != 0) {
1629 data += AVXInstruction(data);
1631 const InstructionDesc& idesc = instruction_table_->Get(current);
1632 byte_size_operand_ = idesc.byte_size_operation;
1633 switch (idesc.type) {
1634 case ZERO_OPERANDS_INSTR:
1635 if (current >= 0xA4 && current <= 0xA7) {
1636 // String move or compare operations.
1637 if (group_1_prefix_ == REP_PREFIX) {
1639 AppendToBuffer("rep ");
1641 if (rex_w()) AppendToBuffer("REX.W ");
1642 AppendToBuffer("%s%c", idesc.mnem, operand_size_code());
1644 AppendToBuffer("%s", idesc.mnem, operand_size_code());
1649 case TWO_OPERANDS_INSTR:
1651 data += PrintOperands(idesc.mnem, idesc.op_order_, data);
1654 case JUMP_CONDITIONAL_SHORT_INSTR:
1655 data += JumpConditionalShort(data);
1658 case REGISTER_INSTR:
1659 AppendToBuffer("%s%c %s", idesc.mnem, operand_size_code(),
1660 NameOfCPURegister(base_reg(current & 0x07)));
1664 AppendToBuffer("%s %s", idesc.mnem,
1665 NameOfCPURegister(base_reg(current & 0x07)));
1668 case MOVE_REG_INSTR: {
1670 switch (operand_size()) {
1671 case OPERAND_WORD_SIZE:
1673 reinterpret_cast<byte*>(*reinterpret_cast<int16_t*>(data + 1));
1676 case OPERAND_DOUBLEWORD_SIZE:
1678 reinterpret_cast<byte*>(*reinterpret_cast<uint32_t*>(data + 1));
1681 case OPERAND_QUADWORD_SIZE:
1683 reinterpret_cast<byte*>(*reinterpret_cast<int64_t*>(data + 1));
1689 AppendToBuffer("mov%c %s,%s", operand_size_code(),
1690 NameOfCPURegister(base_reg(current & 0x07)),
1691 NameOfAddress(addr));
1695 case CALL_JUMP_INSTR: {
1696 byte* addr = data + *reinterpret_cast<int32_t*>(data + 1) + 5;
1697 AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
1702 case SHORT_IMMEDIATE_INSTR: {
1704 reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data + 1));
1705 AppendToBuffer("%s rax,%s", idesc.mnem, NameOfAddress(addr));
1715 UNIMPLEMENTED(); // This type is not implemented.
1719 // The first byte didn't match any of the simple opcodes, so we
1720 // need to do special processing on it.
1724 AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data + 1));
1728 case 0x69: // fall through
1731 count += PrintOperands("imul", REG_OPER_OP_ORDER, data + count);
1732 AppendToBuffer(",0x");
1733 if (*data == 0x69) {
1734 count += PrintImmediate(data + count, operand_size());
1736 count += PrintImmediate(data + count, OPERAND_BYTE_SIZE);
1742 case 0x81: // fall through
1743 case 0x83: // 0x81 with sign extension bit set
1744 data += PrintImmediateOp(data);
1748 data += TwoByteOpcodeInstruction(data);
1754 get_modrm(*data, &mod, ®op, &rm);
1756 AppendToBuffer("pop ");
1757 data += PrintRightOperand(data);
1765 get_modrm(*data, &mod, ®op, &rm);
1766 const char* mnem = NULL;
1786 AppendToBuffer(((regop <= 1) ? "%s%c " : "%s "),
1788 operand_size_code());
1789 data += PrintRightOperand(data);
1793 case 0xC7: // imm32, fall through
1796 bool is_byte = *data == 0xC6;
1799 AppendToBuffer("movb ");
1800 data += PrintRightByteOperand(data);
1801 int32_t imm = *data;
1802 AppendToBuffer(",0x%x", imm);
1805 AppendToBuffer("mov%c ", operand_size_code());
1806 data += PrintRightOperand(data);
1807 if (operand_size() == OPERAND_WORD_SIZE) {
1808 int16_t imm = *reinterpret_cast<int16_t*>(data);
1809 AppendToBuffer(",0x%x", imm);
1812 int32_t imm = *reinterpret_cast<int32_t*>(data);
1813 AppendToBuffer(",0x%x", imm);
1822 AppendToBuffer("cmpb ");
1823 data += PrintRightByteOperand(data);
1824 int32_t imm = *data;
1825 AppendToBuffer(",0x%x", imm);
1830 case 0x88: // 8bit, fall through
1833 bool is_byte = *data == 0x88;
1836 get_modrm(*data, &mod, ®op, &rm);
1838 AppendToBuffer("movb ");
1839 data += PrintRightByteOperand(data);
1840 AppendToBuffer(",%s", NameOfByteCPURegister(regop));
1842 AppendToBuffer("mov%c ", operand_size_code());
1843 data += PrintRightOperand(data);
1844 AppendToBuffer(",%s", NameOfCPURegister(regop));
1857 int reg = (*data & 0x7) | (rex_b() ? 8 : 0);
1859 AppendToBuffer("nop"); // Common name for xchg rax,rax.
1861 AppendToBuffer("xchg%c rax,%s",
1862 operand_size_code(),
1863 NameOfCPURegister(reg));
1884 // mov reg8,imm8 or mov reg32,imm32
1885 byte opcode = *data;
1887 bool is_32bit = (opcode >= 0xB8);
1888 int reg = (opcode & 0x7) | (rex_b() ? 8 : 0);
1890 AppendToBuffer("mov%c %s,",
1891 operand_size_code(),
1892 NameOfCPURegister(reg));
1893 data += PrintImmediate(data, OPERAND_DOUBLEWORD_SIZE);
1895 AppendToBuffer("movb %s,",
1896 NameOfByteCPURegister(reg));
1897 data += PrintImmediate(data, OPERAND_BYTE_SIZE);
1904 get_modrm(*data, &mod, ®op, &rm);
1906 AppendToBuffer("decb ");
1907 data += PrintRightByteOperand(data);
1909 UnimplementedInstruction();
1914 AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data + 1));
1919 AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
1923 case 0xA1: // Fall through.
1925 switch (operand_size()) {
1926 case OPERAND_DOUBLEWORD_SIZE: {
1927 const char* memory_location = NameOfAddress(
1928 reinterpret_cast<byte*>(
1929 *reinterpret_cast<int32_t*>(data + 1)));
1930 if (*data == 0xA1) { // Opcode 0xA1
1931 AppendToBuffer("movzxlq rax,(%s)", memory_location);
1932 } else { // Opcode 0xA3
1933 AppendToBuffer("movzxlq (%s),rax", memory_location);
1938 case OPERAND_QUADWORD_SIZE: {
1939 // New x64 instruction mov rax,(imm_64).
1940 const char* memory_location = NameOfAddress(
1941 *reinterpret_cast<byte**>(data + 1));
1942 if (*data == 0xA1) { // Opcode 0xA1
1943 AppendToBuffer("movq rax,(%s)", memory_location);
1944 } else { // Opcode 0xA3
1945 AppendToBuffer("movq (%s),rax", memory_location);
1951 UnimplementedInstruction();
1957 AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data + 1));
1963 switch (operand_size()) {
1964 case OPERAND_WORD_SIZE:
1965 value = *reinterpret_cast<uint16_t*>(data + 1);
1968 case OPERAND_DOUBLEWORD_SIZE:
1969 value = *reinterpret_cast<uint32_t*>(data + 1);
1972 case OPERAND_QUADWORD_SIZE:
1973 value = *reinterpret_cast<int32_t*>(data + 1);
1979 AppendToBuffer("test%c rax,0x%" V8_PTR_PREFIX "x",
1980 operand_size_code(),
1984 case 0xD1: // fall through
1985 case 0xD3: // fall through
1987 data += ShiftInstruction(data);
1989 case 0xD0: // fall through
1990 case 0xD2: // fall through
1992 byte_size_operand_ = true;
1993 data += ShiftInstruction(data);
1996 case 0xD9: // fall through
1997 case 0xDA: // fall through
1998 case 0xDB: // fall through
1999 case 0xDC: // fall through
2000 case 0xDD: // fall through
2001 case 0xDE: // fall through
2003 data += FPUInstruction(data);
2007 data += JumpShort(data);
2011 byte_size_operand_ = true; // fall through
2013 data += F6F7Instruction(data);
2017 AppendToBuffer("cmp al,0x%x", *reinterpret_cast<int8_t*>(data + 1));
2022 UnimplementedInstruction();
2027 if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
2028 tmp_buffer_[tmp_buffer_pos_] = '\0';
2031 int instr_len = static_cast<int>(data - instr);
2032 DCHECK(instr_len > 0); // Ensure progress.
2035 // Instruction bytes.
2036 for (byte* bp = instr; bp < data; bp++) {
2037 outp += v8::internal::SNPrintF(out_buffer + outp, "%02x", *bp);
2039 for (int i = 6 - instr_len; i >= 0; i--) {
2040 outp += v8::internal::SNPrintF(out_buffer + outp, " ");
2043 outp += v8::internal::SNPrintF(out_buffer + outp, " %s",
2044 tmp_buffer_.start());
2049 //------------------------------------------------------------------------------
2052 static const char* const cpu_regs[16] = {
2053 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2054 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2058 static const char* const byte_cpu_regs[16] = {
2059 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2060 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
2064 static const char* const xmm_regs[16] = {
2065 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2066 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
2070 const char* NameConverter::NameOfAddress(byte* addr) const {
2071 v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
2072 return tmp_buffer_.start();
2076 const char* NameConverter::NameOfConstant(byte* addr) const {
2077 return NameOfAddress(addr);
2081 const char* NameConverter::NameOfCPURegister(int reg) const {
2082 if (0 <= reg && reg < 16)
2083 return cpu_regs[reg];
2088 const char* NameConverter::NameOfByteCPURegister(int reg) const {
2089 if (0 <= reg && reg < 16)
2090 return byte_cpu_regs[reg];
2095 const char* NameConverter::NameOfXMMRegister(int reg) const {
2096 if (0 <= reg && reg < 16)
2097 return xmm_regs[reg];
2102 const char* NameConverter::NameInCode(byte* addr) const {
2103 // X64 does not embed debug strings at the moment.
2109 //------------------------------------------------------------------------------
2111 Disassembler::Disassembler(const NameConverter& converter)
2112 : converter_(converter) { }
2114 Disassembler::~Disassembler() { }
2117 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
2118 byte* instruction) {
2119 DisassemblerX64 d(converter_, CONTINUE_ON_UNIMPLEMENTED_OPCODE);
2120 return d.InstructionDecode(buffer, instruction);
2124 // The X64 assembler does not use constant pools.
2125 int Disassembler::ConstantPoolSizeAt(byte* instruction) {
2130 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
2131 NameConverter converter;
2132 Disassembler d(converter);
2133 for (byte* pc = begin; pc < end;) {
2134 v8::internal::EmbeddedVector<char, 128> buffer;
2137 pc += d.InstructionDecode(buffer, pc);
2138 fprintf(f, "%p", prev_pc);
2141 for (byte* bp = prev_pc; bp < pc; bp++) {
2142 fprintf(f, "%02x", *bp);
2144 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
2147 fprintf(f, " %s\n", buffer.start());
2151 } // namespace disasm
2153 #endif // V8_TARGET_ARCH_X64