1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
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16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
35 // A lightweight X64 Assembler.
37 #ifndef V8_X64_ASSEMBLER_X64_H_
38 #define V8_X64_ASSEMBLER_X64_H_
42 #include "src/assembler.h"
43 #include "src/serialize.h"
52 // 1) We would prefer to use an enum, but enum values are assignment-
53 // compatible with int, which has caused code-generation bugs.
55 // 2) We would prefer to use a class instead of a struct but we don't like
56 // the register initialization to depend on the particular initialization
57 // order (which appears to be different on OS X, Linux, and Windows for the
58 // installed versions of C++ we tried). Using a struct permits C-style
59 // "initialization". Also, the Register objects cannot be const as this
60 // forces initialization stubs in MSVC, making us dependent on initialization
63 // 3) By not using an enum, we are possibly preventing the compiler from
64 // doing certain constant folds, which may significantly reduce the
65 // code generated for some assembly instructions (because they boil down
66 // to a few constants). If this is a problem, we could change the code
67 // such that we use an enum in optimized mode, and the struct in debug
68 // mode. This way we get the compile-time error checking in debug mode
69 // and best performance in optimized code.
73 // The non-allocatable registers are:
74 // rsp - stack pointer
75 // rbp - frame pointer
76 // r10 - fixed scratch register
77 // r12 - smi constant register
78 // r13 - root register
79 static const int kMaxNumAllocatableRegisters = 11;
80 static int NumAllocatableRegisters() {
81 return kMaxNumAllocatableRegisters;
83 static const int kNumRegisters = 16;
85 static int ToAllocationIndex(Register reg) {
86 return kAllocationIndexByRegisterCode[reg.code()];
89 static Register FromAllocationIndex(int index) {
90 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
91 Register result = { kRegisterCodeByAllocationIndex[index] };
95 static const char* AllocationIndexToString(int index) {
96 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
97 const char* const names[] = {
113 static Register from_code(int code) {
114 Register r = { code };
117 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
118 bool is(Register reg) const { return code_ == reg.code_; }
119 // rax, rbx, rcx and rdx are byte registers, the rest are not.
120 bool is_byte_register() const { return code_ <= 3; }
129 // Return the high bit of the register code as a 0 or 1. Used often
130 // when constructing the REX prefix byte.
131 int high_bit() const {
134 // Return the 3 low bits of the register code. Used when encoding registers
135 // in modR/M, SIB, and opcode bytes.
136 int low_bits() const {
140 // Unfortunately we can't make this private in a struct when initializing
145 static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters];
146 static const int kAllocationIndexByRegisterCode[kNumRegisters];
149 const int kRegister_rax_Code = 0;
150 const int kRegister_rcx_Code = 1;
151 const int kRegister_rdx_Code = 2;
152 const int kRegister_rbx_Code = 3;
153 const int kRegister_rsp_Code = 4;
154 const int kRegister_rbp_Code = 5;
155 const int kRegister_rsi_Code = 6;
156 const int kRegister_rdi_Code = 7;
157 const int kRegister_r8_Code = 8;
158 const int kRegister_r9_Code = 9;
159 const int kRegister_r10_Code = 10;
160 const int kRegister_r11_Code = 11;
161 const int kRegister_r12_Code = 12;
162 const int kRegister_r13_Code = 13;
163 const int kRegister_r14_Code = 14;
164 const int kRegister_r15_Code = 15;
165 const int kRegister_no_reg_Code = -1;
167 const Register rax = { kRegister_rax_Code };
168 const Register rcx = { kRegister_rcx_Code };
169 const Register rdx = { kRegister_rdx_Code };
170 const Register rbx = { kRegister_rbx_Code };
171 const Register rsp = { kRegister_rsp_Code };
172 const Register rbp = { kRegister_rbp_Code };
173 const Register rsi = { kRegister_rsi_Code };
174 const Register rdi = { kRegister_rdi_Code };
175 const Register r8 = { kRegister_r8_Code };
176 const Register r9 = { kRegister_r9_Code };
177 const Register r10 = { kRegister_r10_Code };
178 const Register r11 = { kRegister_r11_Code };
179 const Register r12 = { kRegister_r12_Code };
180 const Register r13 = { kRegister_r13_Code };
181 const Register r14 = { kRegister_r14_Code };
182 const Register r15 = { kRegister_r15_Code };
183 const Register no_reg = { kRegister_no_reg_Code };
186 // Windows calling convention
187 const Register arg_reg_1 = { kRegister_rcx_Code };
188 const Register arg_reg_2 = { kRegister_rdx_Code };
189 const Register arg_reg_3 = { kRegister_r8_Code };
190 const Register arg_reg_4 = { kRegister_r9_Code };
192 // AMD64 calling convention
193 const Register arg_reg_1 = { kRegister_rdi_Code };
194 const Register arg_reg_2 = { kRegister_rsi_Code };
195 const Register arg_reg_3 = { kRegister_rdx_Code };
196 const Register arg_reg_4 = { kRegister_rcx_Code };
200 static const int kMaxNumRegisters = 16;
201 static const int kMaxNumAllocatableRegisters = 15;
202 static int NumAllocatableRegisters() {
203 return kMaxNumAllocatableRegisters;
206 // TODO(turbofan): Proper support for float32.
207 static int NumAllocatableAliasedRegisters() {
208 return NumAllocatableRegisters();
211 static int ToAllocationIndex(XMMRegister reg) {
212 DCHECK(reg.code() != 0);
213 return reg.code() - 1;
216 static XMMRegister FromAllocationIndex(int index) {
217 DCHECK(0 <= index && index < kMaxNumAllocatableRegisters);
218 XMMRegister result = { index + 1 };
222 static const char* AllocationIndexToString(int index) {
223 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
224 const char* const names[] = {
244 static XMMRegister from_code(int code) {
246 DCHECK(code < kMaxNumRegisters);
247 XMMRegister r = { code };
250 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; }
251 bool is(XMMRegister reg) const { return code_ == reg.code_; }
257 // Return the high bit of the register code as a 0 or 1. Used often
258 // when constructing the REX prefix byte.
259 int high_bit() const {
262 // Return the 3 low bits of the register code. Used when encoding registers
263 // in modR/M, SIB, and opcode bytes.
264 int low_bits() const {
271 const XMMRegister xmm0 = { 0 };
272 const XMMRegister xmm1 = { 1 };
273 const XMMRegister xmm2 = { 2 };
274 const XMMRegister xmm3 = { 3 };
275 const XMMRegister xmm4 = { 4 };
276 const XMMRegister xmm5 = { 5 };
277 const XMMRegister xmm6 = { 6 };
278 const XMMRegister xmm7 = { 7 };
279 const XMMRegister xmm8 = { 8 };
280 const XMMRegister xmm9 = { 9 };
281 const XMMRegister xmm10 = { 10 };
282 const XMMRegister xmm11 = { 11 };
283 const XMMRegister xmm12 = { 12 };
284 const XMMRegister xmm13 = { 13 };
285 const XMMRegister xmm14 = { 14 };
286 const XMMRegister xmm15 = { 15 };
289 typedef XMMRegister DoubleRegister;
293 // any value < 0 is considered no_condition
313 // Fake conditions that are handled by the
314 // opcodes using them.
319 not_carry = above_equal,
321 not_zero = not_equal,
324 last_condition = greater
328 // Returns the equivalent of !cc.
329 // Negation of the default no_condition (-1) results in a non-default
330 // no_condition value (-2). As long as tests for no_condition check
331 // for condition < 0, this will work as expected.
332 inline Condition NegateCondition(Condition cc) {
333 return static_cast<Condition>(cc ^ 1);
337 // Commute a condition such that {a cond b == b cond' a}.
338 inline Condition CommuteCondition(Condition cc) {
355 return greater_equal;
362 // -----------------------------------------------------------------------------
363 // Machine instruction Immediates
365 class Immediate BASE_EMBEDDED {
367 explicit Immediate(int32_t value) : value_(value) {}
368 explicit Immediate(Smi* value) {
369 DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
370 value_ = static_cast<int32_t>(reinterpret_cast<intptr_t>(value));
376 friend class Assembler;
380 // -----------------------------------------------------------------------------
381 // Machine instruction Operands
388 times_int_size = times_4,
389 times_pointer_size = (kPointerSize == 8) ? times_8 : times_4
393 class Operand BASE_EMBEDDED {
396 Operand(Register base, int32_t disp);
398 // [base + index*scale + disp/r]
399 Operand(Register base,
404 // [index*scale + disp/r]
405 Operand(Register index,
409 // Offset from existing memory operand.
410 // Offset is added to existing displacement as 32-bit signed values and
411 // this must not overflow.
412 Operand(const Operand& base, int32_t offset);
415 explicit Operand(Label* label);
417 // Checks whether either base or index register is the given register.
418 // Does not check the "reg" part of the Operand.
419 bool AddressUsesRegister(Register reg) const;
421 // Queries related to the size of the generated instruction.
422 // Whether the generated instruction will have a REX prefix.
423 bool requires_rex() const { return rex_ != 0; }
424 // Size of the ModR/M, SIB and displacement parts of the generated
426 int operand_size() const { return len_; }
431 // The number of bytes of buf_ in use.
434 // Set the ModR/M byte without an encoded 'reg' register. The
435 // register is encoded later as part of the emit_operand operation.
436 // set_modrm can be called before or after set_sib and set_disp*.
437 inline void set_modrm(int mod, Register rm);
439 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
440 inline void set_sib(ScaleFactor scale, Register index, Register base);
442 // Adds operand displacement fields (offsets added to the memory address).
443 // Needs to be called after set_sib, not before it.
444 inline void set_disp8(int disp);
445 inline void set_disp32(int disp);
446 inline void set_disp64(int64_t disp); // for labels.
448 friend class Assembler;
452 #define ASSEMBLER_INSTRUCTION_LIST(V) \
476 // Shift instructions on operands/registers with kPointerSize, kInt32Size and
478 #define SHIFT_INSTRUCTION_LIST(V) \
488 class Assembler : public AssemblerBase {
490 // We check before assembling an instruction that there is sufficient
491 // space to write an instruction and its relocation information.
492 // The relocation writer's position must be kGap bytes above the end of
493 // the generated instructions. This leaves enough space for the
494 // longest possible x64 instruction, 15 bytes, and the longest possible
495 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
496 // (There is a 15 byte limit on x64 instruction length that rules out some
497 // otherwise valid instructions.)
498 // This allows for a single, fast space check per instruction.
499 static const int kGap = 32;
502 // Create an assembler. Instructions and relocation information are emitted
503 // into a buffer, with the instructions starting from the beginning and the
504 // relocation information starting from the end of the buffer. See CodeDesc
505 // for a detailed comment on the layout (globals.h).
507 // If the provided buffer is NULL, the assembler allocates and grows its own
508 // buffer, and buffer_size determines the initial buffer size. The buffer is
509 // owned by the assembler and deallocated upon destruction of the assembler.
511 // If the provided buffer is not NULL, the assembler uses the provided buffer
512 // for code generation and assumes its size to be buffer_size. If the buffer
513 // is too small, a fatal error occurs. No deallocation of the buffer is done
514 // upon destruction of the assembler.
515 Assembler(Isolate* isolate, void* buffer, int buffer_size);
516 virtual ~Assembler() { }
518 // GetCode emits any pending (non-emitted) code and fills the descriptor
519 // desc. GetCode() is idempotent; it returns the same result if no other
520 // Assembler functions are invoked in between GetCode() calls.
521 void GetCode(CodeDesc* desc);
523 // Read/Modify the code target in the relative branch/call instruction at pc.
524 // On the x64 architecture, we use relative jumps with a 32-bit displacement
525 // to jump to other Code objects in the Code space in the heap.
526 // Jumps to C functions are done indirectly through a 64-bit register holding
527 // the absolute address of the target.
528 // These functions convert between absolute Addresses of Code objects and
529 // the relative displacements stored in the code.
530 static inline Address target_address_at(Address pc,
531 ConstantPoolArray* constant_pool);
532 static inline void set_target_address_at(Address pc,
533 ConstantPoolArray* constant_pool,
535 ICacheFlushMode icache_flush_mode =
536 FLUSH_ICACHE_IF_NEEDED) ;
537 static inline Address target_address_at(Address pc, Code* code) {
538 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
539 return target_address_at(pc, constant_pool);
541 static inline void set_target_address_at(Address pc,
544 ICacheFlushMode icache_flush_mode =
545 FLUSH_ICACHE_IF_NEEDED) {
546 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
547 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
550 // Return the code target address at a call site from the return address
551 // of that call in the instruction stream.
552 static inline Address target_address_from_return_address(Address pc);
554 // Return the code target address of the patch debug break slot
555 inline static Address break_address_from_return_address(Address pc);
557 // This sets the branch destination (which is in the instruction on x64).
558 // This is for calls and branches within generated code.
559 inline static void deserialization_set_special_target_at(
560 Address instruction_payload, Code* code, Address target) {
561 set_target_address_at(instruction_payload, code, target);
564 static inline RelocInfo::Mode RelocInfoNone() {
565 if (kPointerSize == kInt64Size) {
566 return RelocInfo::NONE64;
568 DCHECK(kPointerSize == kInt32Size);
569 return RelocInfo::NONE32;
573 inline Handle<Object> code_target_object_handle_at(Address pc);
574 inline Address runtime_entry_at(Address pc);
575 // Number of bytes taken up by the branch target in the code.
576 static const int kSpecialTargetSize = 4; // Use 32-bit displacement.
577 // Distance between the address of the code target in the call instruction
578 // and the return address pushed on the stack.
579 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
580 // The length of call(kScratchRegister).
581 static const int kCallScratchRegisterInstructionLength = 3;
582 // The length of call(Immediate32).
583 static const int kShortCallInstructionLength = 5;
584 // The length of movq(kScratchRegister, address).
585 static const int kMoveAddressIntoScratchRegisterInstructionLength =
587 // The length of movq(kScratchRegister, address) and call(kScratchRegister).
588 static const int kCallSequenceLength =
589 kMoveAddressIntoScratchRegisterInstructionLength +
590 kCallScratchRegisterInstructionLength;
592 // The js return and debug break slot must be able to contain an indirect
593 // call sequence, some x64 JS code is padded with int3 to make it large
594 // enough to hold an instruction when the debugger patches it.
595 static const int kJSReturnSequenceLength = kCallSequenceLength;
596 static const int kDebugBreakSlotLength = kCallSequenceLength;
597 static const int kPatchDebugBreakSlotReturnOffset = kCallTargetAddressOffset;
598 // Distance between the start of the JS return sequence and where the
599 // 32-bit displacement of a short call would be. The short call is from
600 // SetDebugBreakAtIC from debug-x64.cc.
601 static const int kPatchReturnSequenceAddressOffset =
602 kJSReturnSequenceLength - kPatchDebugBreakSlotReturnOffset;
603 // Distance between the start of the JS return sequence and where the
604 // 32-bit displacement of a short call would be. The short call is from
605 // SetDebugBreakAtIC from debug-x64.cc.
606 static const int kPatchDebugBreakSlotAddressOffset =
607 kDebugBreakSlotLength - kPatchDebugBreakSlotReturnOffset;
608 static const int kRealPatchReturnSequenceAddressOffset =
609 kMoveAddressIntoScratchRegisterInstructionLength - kPointerSize;
611 // One byte opcode for test eax,0xXXXXXXXX.
612 static const byte kTestEaxByte = 0xA9;
613 // One byte opcode for test al, 0xXX.
614 static const byte kTestAlByte = 0xA8;
615 // One byte opcode for nop.
616 static const byte kNopByte = 0x90;
618 // One byte prefix for a short conditional jump.
619 static const byte kJccShortPrefix = 0x70;
620 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
621 static const byte kJcShortOpcode = kJccShortPrefix | carry;
622 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
623 static const byte kJzShortOpcode = kJccShortPrefix | zero;
626 // ---------------------------------------------------------------------------
629 // Function names correspond one-to-one to x64 instruction mnemonics.
630 // Unless specified otherwise, instructions operate on 64-bit operands.
632 // If we need versions of an assembly instruction that operate on different
633 // width arguments, we add a single-letter suffix specifying the width.
634 // This is done for the following instructions: mov, cmp, inc, dec,
635 // add, sub, and test.
636 // There are no versions of these instructions without the suffix.
637 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
638 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
639 // - Instructions on 32-bit (doubleword) operands/registers use 'l'.
640 // - Instructions on 64-bit (quadword) operands/registers use 'q'.
641 // - Instructions on operands/registers with pointer size use 'p'.
643 STATIC_ASSERT(kPointerSize == kInt64Size || kPointerSize == kInt32Size);
645 #define DECLARE_INSTRUCTION(instruction) \
647 void instruction##p(P1 p1) { \
648 emit_##instruction(p1, kPointerSize); \
652 void instruction##l(P1 p1) { \
653 emit_##instruction(p1, kInt32Size); \
657 void instruction##q(P1 p1) { \
658 emit_##instruction(p1, kInt64Size); \
661 template<class P1, class P2> \
662 void instruction##p(P1 p1, P2 p2) { \
663 emit_##instruction(p1, p2, kPointerSize); \
666 template<class P1, class P2> \
667 void instruction##l(P1 p1, P2 p2) { \
668 emit_##instruction(p1, p2, kInt32Size); \
671 template<class P1, class P2> \
672 void instruction##q(P1 p1, P2 p2) { \
673 emit_##instruction(p1, p2, kInt64Size); \
676 template<class P1, class P2, class P3> \
677 void instruction##p(P1 p1, P2 p2, P3 p3) { \
678 emit_##instruction(p1, p2, p3, kPointerSize); \
681 template<class P1, class P2, class P3> \
682 void instruction##l(P1 p1, P2 p2, P3 p3) { \
683 emit_##instruction(p1, p2, p3, kInt32Size); \
686 template<class P1, class P2, class P3> \
687 void instruction##q(P1 p1, P2 p2, P3 p3) { \
688 emit_##instruction(p1, p2, p3, kInt64Size); \
690 ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
691 #undef DECLARE_INSTRUCTION
693 // Insert the smallest number of nop instructions
694 // possible to align the pc offset to a multiple
695 // of m, where m must be a power of 2.
697 void Nop(int bytes = 1);
698 // Aligns code to something that's optimal for a jump target for the platform.
699 void CodeTargetAlign();
705 void pushq(Immediate value);
706 // Push a 32 bit integer, and guarantee that it is actually pushed as a
707 // 32 bit value, the normal push will optimize the 8 bit case.
708 void pushq_imm32(int32_t imm32);
709 void pushq(Register src);
710 void pushq(const Operand& src);
712 void popq(Register dst);
713 void popq(const Operand& dst);
715 void enter(Immediate size);
719 void movb(Register dst, const Operand& src);
720 void movb(Register dst, Immediate imm);
721 void movb(const Operand& dst, Register src);
722 void movb(const Operand& dst, Immediate imm);
724 // Move the low 16 bits of a 64-bit register value to a 16-bit
726 void movw(Register dst, const Operand& src);
727 void movw(const Operand& dst, Register src);
728 void movw(const Operand& dst, Immediate imm);
730 // Move the offset of the label location relative to the current
731 // position (after the move) to the destination.
732 void movl(const Operand& dst, Label* src);
734 // Loads a pointer into a register with a relocation mode.
735 void movp(Register dst, void* ptr, RelocInfo::Mode rmode);
737 // Loads a 64-bit immediate into a register.
738 void movq(Register dst, int64_t value);
739 void movq(Register dst, uint64_t value);
741 void movsxbl(Register dst, Register src);
742 void movsxbl(Register dst, const Operand& src);
743 void movsxbq(Register dst, const Operand& src);
744 void movsxwl(Register dst, Register src);
745 void movsxwl(Register dst, const Operand& src);
746 void movsxwq(Register dst, const Operand& src);
747 void movsxlq(Register dst, Register src);
748 void movsxlq(Register dst, const Operand& src);
754 void repmovsp() { emit_repmovs(kPointerSize); }
755 void repmovsl() { emit_repmovs(kInt32Size); }
756 void repmovsq() { emit_repmovs(kInt64Size); }
758 // Instruction to load from an immediate 64-bit pointer into RAX.
759 void load_rax(void* ptr, RelocInfo::Mode rmode);
760 void load_rax(ExternalReference ext);
762 // Conditional moves.
763 void cmovq(Condition cc, Register dst, Register src);
764 void cmovq(Condition cc, Register dst, const Operand& src);
765 void cmovl(Condition cc, Register dst, Register src);
766 void cmovl(Condition cc, Register dst, const Operand& src);
768 void cmpb(Register dst, Immediate src) {
769 immediate_arithmetic_op_8(0x7, dst, src);
772 void cmpb_al(Immediate src);
774 void cmpb(Register dst, Register src) {
775 arithmetic_op_8(0x3A, dst, src);
778 void cmpb(Register dst, const Operand& src) {
779 arithmetic_op_8(0x3A, dst, src);
782 void cmpb(const Operand& dst, Register src) {
783 arithmetic_op_8(0x38, src, dst);
786 void cmpb(const Operand& dst, Immediate src) {
787 immediate_arithmetic_op_8(0x7, dst, src);
790 void cmpw(const Operand& dst, Immediate src) {
791 immediate_arithmetic_op_16(0x7, dst, src);
794 void cmpw(Register dst, Immediate src) {
795 immediate_arithmetic_op_16(0x7, dst, src);
798 void cmpw(Register dst, const Operand& src) {
799 arithmetic_op_16(0x3B, dst, src);
802 void cmpw(Register dst, Register src) {
803 arithmetic_op_16(0x3B, dst, src);
806 void cmpw(const Operand& dst, Register src) {
807 arithmetic_op_16(0x39, src, dst);
810 void andb(Register dst, Immediate src) {
811 immediate_arithmetic_op_8(0x4, dst, src);
814 void decb(Register dst);
815 void decb(const Operand& dst);
817 // Sign-extends rax into rdx:rax.
819 // Sign-extends eax into edx:eax.
822 // Multiply eax by src, put the result in edx:eax.
823 void mull(Register src);
824 void mull(const Operand& src);
825 // Multiply rax by src, put the result in rdx:rax.
826 void mulq(Register src);
828 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
829 void instruction##p(Register dst, Immediate imm8) { \
830 shift(dst, imm8, subcode, kPointerSize); \
833 void instruction##l(Register dst, Immediate imm8) { \
834 shift(dst, imm8, subcode, kInt32Size); \
837 void instruction##q(Register dst, Immediate imm8) { \
838 shift(dst, imm8, subcode, kInt64Size); \
841 void instruction##p(Operand dst, Immediate imm8) { \
842 shift(dst, imm8, subcode, kPointerSize); \
845 void instruction##l(Operand dst, Immediate imm8) { \
846 shift(dst, imm8, subcode, kInt32Size); \
849 void instruction##q(Operand dst, Immediate imm8) { \
850 shift(dst, imm8, subcode, kInt64Size); \
853 void instruction##p_cl(Register dst) { shift(dst, subcode, kPointerSize); } \
855 void instruction##l_cl(Register dst) { shift(dst, subcode, kInt32Size); } \
857 void instruction##q_cl(Register dst) { shift(dst, subcode, kInt64Size); } \
859 void instruction##p_cl(Operand dst) { shift(dst, subcode, kPointerSize); } \
861 void instruction##l_cl(Operand dst) { shift(dst, subcode, kInt32Size); } \
863 void instruction##q_cl(Operand dst) { shift(dst, subcode, kInt64Size); }
864 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
865 #undef DECLARE_SHIFT_INSTRUCTION
867 // Shifts dst:src left by cl bits, affecting only dst.
868 void shld(Register dst, Register src);
870 // Shifts src:dst right by cl bits, affecting only dst.
871 void shrd(Register dst, Register src);
873 void store_rax(void* dst, RelocInfo::Mode mode);
874 void store_rax(ExternalReference ref);
876 void subb(Register dst, Immediate src) {
877 immediate_arithmetic_op_8(0x5, dst, src);
880 void testb(Register dst, Register src);
881 void testb(Register reg, Immediate mask);
882 void testb(const Operand& op, Immediate mask);
883 void testb(const Operand& op, Register reg);
886 void bt(const Operand& dst, Register src);
887 void bts(const Operand& dst, Register src);
888 void bsrl(Register dst, Register src);
899 void setcc(Condition cc, Register reg);
901 // Label operations & relative jumps (PPUM Appendix D)
903 // Takes a branch opcode (cc) and a label (L) and generates
904 // either a backward branch or a forward branch and links it
905 // to the label fixup chain. Usage:
907 // Label L; // unbound label
908 // j(cc, &L); // forward branch to unbound label
909 // bind(&L); // bind label to the current pc
910 // j(cc, &L); // backward branch to bound label
911 // bind(&L); // illegal: a label may be bound only once
913 // Note: The same Label can be used for forward and backward branches
914 // but it may be bound only once.
916 void bind(Label* L); // binds an unbound label L to the current code position
919 // Call near relative 32-bit displacement, relative to next instruction.
921 void call(Address entry, RelocInfo::Mode rmode);
922 void call(Handle<Code> target,
923 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
924 TypeFeedbackId ast_id = TypeFeedbackId::None());
926 // Calls directly to the given address using a relative offset.
927 // Should only ever be used in Code objects for calls within the
928 // same Code object. Should not be used when generating new code (use labels),
929 // but only when patching existing code.
930 void call(Address target);
932 // Call near absolute indirect, address in register
933 void call(Register adr);
936 // Jump short or near relative.
937 // Use a 32-bit signed displacement.
938 // Unconditional jump to L
939 void jmp(Label* L, Label::Distance distance = Label::kFar);
940 void jmp(Address entry, RelocInfo::Mode rmode);
941 void jmp(Handle<Code> target, RelocInfo::Mode rmode);
943 // Jump near absolute indirect (r64)
944 void jmp(Register adr);
945 void jmp(const Operand& src);
950 Label::Distance distance = Label::kFar);
951 void j(Condition cc, Address entry, RelocInfo::Mode rmode);
952 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
954 // Floating-point operations
962 void fld_s(const Operand& adr);
963 void fld_d(const Operand& adr);
965 void fstp_s(const Operand& adr);
966 void fstp_d(const Operand& adr);
967 void fstp(int index);
969 void fild_s(const Operand& adr);
970 void fild_d(const Operand& adr);
972 void fist_s(const Operand& adr);
974 void fistp_s(const Operand& adr);
975 void fistp_d(const Operand& adr);
977 void fisttp_s(const Operand& adr);
978 void fisttp_d(const Operand& adr);
988 void fisub_s(const Operand& adr);
990 void faddp(int i = 1);
991 void fsubp(int i = 1);
992 void fsubrp(int i = 1);
993 void fmulp(int i = 1);
994 void fdivp(int i = 1);
998 void fxch(int i = 1);
1000 void ffree(int i = 0);
1026 void addss(XMMRegister dst, XMMRegister src);
1027 void addss(XMMRegister dst, const Operand& src);
1028 void subss(XMMRegister dst, XMMRegister src);
1029 void subss(XMMRegister dst, const Operand& src);
1030 void mulss(XMMRegister dst, XMMRegister src);
1031 void mulss(XMMRegister dst, const Operand& src);
1032 void divss(XMMRegister dst, XMMRegister src);
1033 void divss(XMMRegister dst, const Operand& src);
1035 void ucomiss(XMMRegister dst, XMMRegister src);
1036 void ucomiss(XMMRegister dst, const Operand& src);
1037 void movaps(XMMRegister dst, XMMRegister src);
1038 void movss(XMMRegister dst, const Operand& src);
1039 void movss(const Operand& dst, XMMRegister src);
1040 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
1042 void cvttss2si(Register dst, const Operand& src);
1043 void cvttss2si(Register dst, XMMRegister src);
1044 void cvtlsi2ss(XMMRegister dst, Register src);
1046 void andps(XMMRegister dst, XMMRegister src);
1047 void andps(XMMRegister dst, const Operand& src);
1048 void orps(XMMRegister dst, XMMRegister src);
1049 void orps(XMMRegister dst, const Operand& src);
1050 void xorps(XMMRegister dst, XMMRegister src);
1051 void xorps(XMMRegister dst, const Operand& src);
1053 void addps(XMMRegister dst, XMMRegister src);
1054 void addps(XMMRegister dst, const Operand& src);
1055 void subps(XMMRegister dst, XMMRegister src);
1056 void subps(XMMRegister dst, const Operand& src);
1057 void mulps(XMMRegister dst, XMMRegister src);
1058 void mulps(XMMRegister dst, const Operand& src);
1059 void divps(XMMRegister dst, XMMRegister src);
1060 void divps(XMMRegister dst, const Operand& src);
1062 void movmskps(Register dst, XMMRegister src);
1064 // SSE2 instructions
1065 void movd(XMMRegister dst, Register src);
1066 void movd(Register dst, XMMRegister src);
1067 void movq(XMMRegister dst, Register src);
1068 void movq(Register dst, XMMRegister src);
1069 void movq(XMMRegister dst, XMMRegister src);
1071 // Don't use this unless it's important to keep the
1072 // top half of the destination register unchanged.
1073 // Used movaps when moving double values and movq for integer
1074 // values in xmm registers.
1075 void movsd(XMMRegister dst, XMMRegister src);
1077 void movsd(const Operand& dst, XMMRegister src);
1078 void movsd(XMMRegister dst, const Operand& src);
1080 void movdqa(const Operand& dst, XMMRegister src);
1081 void movdqa(XMMRegister dst, const Operand& src);
1083 void movdqu(const Operand& dst, XMMRegister src);
1084 void movdqu(XMMRegister dst, const Operand& src);
1086 void movapd(XMMRegister dst, XMMRegister src);
1088 void psllq(XMMRegister reg, byte imm8);
1089 void psrlq(XMMRegister reg, byte imm8);
1090 void pslld(XMMRegister reg, byte imm8);
1091 void psrld(XMMRegister reg, byte imm8);
1093 void cvttsd2si(Register dst, const Operand& src);
1094 void cvttsd2si(Register dst, XMMRegister src);
1095 void cvttsd2siq(Register dst, XMMRegister src);
1096 void cvttsd2siq(Register dst, const Operand& src);
1098 void cvtlsi2sd(XMMRegister dst, const Operand& src);
1099 void cvtlsi2sd(XMMRegister dst, Register src);
1100 void cvtqsi2sd(XMMRegister dst, const Operand& src);
1101 void cvtqsi2sd(XMMRegister dst, Register src);
1104 void cvtss2sd(XMMRegister dst, XMMRegister src);
1105 void cvtss2sd(XMMRegister dst, const Operand& src);
1106 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1107 void cvtsd2ss(XMMRegister dst, const Operand& src);
1109 void cvtsd2si(Register dst, XMMRegister src);
1110 void cvtsd2siq(Register dst, XMMRegister src);
1112 void addsd(XMMRegister dst, XMMRegister src);
1113 void addsd(XMMRegister dst, const Operand& src);
1114 void subsd(XMMRegister dst, XMMRegister src);
1115 void subsd(XMMRegister dst, const Operand& src);
1116 void mulsd(XMMRegister dst, XMMRegister src);
1117 void mulsd(XMMRegister dst, const Operand& src);
1118 void divsd(XMMRegister dst, XMMRegister src);
1119 void divsd(XMMRegister dst, const Operand& src);
1121 void andpd(XMMRegister dst, XMMRegister src);
1122 void orpd(XMMRegister dst, XMMRegister src);
1123 void xorpd(XMMRegister dst, XMMRegister src);
1124 void sqrtsd(XMMRegister dst, XMMRegister src);
1125 void sqrtsd(XMMRegister dst, const Operand& src);
1127 void ucomisd(XMMRegister dst, XMMRegister src);
1128 void ucomisd(XMMRegister dst, const Operand& src);
1129 void cmpltsd(XMMRegister dst, XMMRegister src);
1130 void pcmpeqd(XMMRegister dst, XMMRegister src);
1132 void movmskpd(Register dst, XMMRegister src);
1134 // SSE 4.1 instruction
1135 void extractps(Register dst, XMMRegister src, byte imm8);
1138 kRoundToNearest = 0x0,
1144 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1147 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1148 vfmasd(0x99, dst, src1, src2);
1150 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1151 vfmasd(0xa9, dst, src1, src2);
1153 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1154 vfmasd(0xb9, dst, src1, src2);
1156 void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1157 vfmasd(0x99, dst, src1, src2);
1159 void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1160 vfmasd(0xa9, dst, src1, src2);
1162 void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1163 vfmasd(0xb9, dst, src1, src2);
1165 void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1166 vfmasd(0x9b, dst, src1, src2);
1168 void vfmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1169 vfmasd(0xab, dst, src1, src2);
1171 void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1172 vfmasd(0xbb, dst, src1, src2);
1174 void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1175 vfmasd(0x9b, dst, src1, src2);
1177 void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1178 vfmasd(0xab, dst, src1, src2);
1180 void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1181 vfmasd(0xbb, dst, src1, src2);
1183 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1184 vfmasd(0x9d, dst, src1, src2);
1186 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1187 vfmasd(0xad, dst, src1, src2);
1189 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1190 vfmasd(0xbd, dst, src1, src2);
1192 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1193 vfmasd(0x9d, dst, src1, src2);
1195 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1196 vfmasd(0xad, dst, src1, src2);
1198 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1199 vfmasd(0xbd, dst, src1, src2);
1201 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1202 vfmasd(0x9f, dst, src1, src2);
1204 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1205 vfmasd(0xaf, dst, src1, src2);
1207 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1208 vfmasd(0xbf, dst, src1, src2);
1210 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1211 vfmasd(0x9f, dst, src1, src2);
1213 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1214 vfmasd(0xaf, dst, src1, src2);
1216 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1217 vfmasd(0xbf, dst, src1, src2);
1219 void vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1220 void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1222 void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1223 vfmass(0x99, dst, src1, src2);
1225 void vfmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1226 vfmass(0xa9, dst, src1, src2);
1228 void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1229 vfmass(0xb9, dst, src1, src2);
1231 void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1232 vfmass(0x99, dst, src1, src2);
1234 void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1235 vfmass(0xa9, dst, src1, src2);
1237 void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1238 vfmass(0xb9, dst, src1, src2);
1240 void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1241 vfmass(0x9b, dst, src1, src2);
1243 void vfmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1244 vfmass(0xab, dst, src1, src2);
1246 void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1247 vfmass(0xbb, dst, src1, src2);
1249 void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1250 vfmass(0x9b, dst, src1, src2);
1252 void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1253 vfmass(0xab, dst, src1, src2);
1255 void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1256 vfmass(0xbb, dst, src1, src2);
1258 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1259 vfmass(0x9d, dst, src1, src2);
1261 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1262 vfmass(0xad, dst, src1, src2);
1264 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1265 vfmass(0xbd, dst, src1, src2);
1267 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1268 vfmass(0x9d, dst, src1, src2);
1270 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1271 vfmass(0xad, dst, src1, src2);
1273 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1274 vfmass(0xbd, dst, src1, src2);
1276 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1277 vfmass(0x9f, dst, src1, src2);
1279 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1280 vfmass(0xaf, dst, src1, src2);
1282 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1283 vfmass(0xbf, dst, src1, src2);
1285 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1286 vfmass(0x9f, dst, src1, src2);
1288 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1289 vfmass(0xaf, dst, src1, src2);
1291 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1292 vfmass(0xbf, dst, src1, src2);
1294 void vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1295 void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1297 void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1298 vsd(0x58, dst, src1, src2);
1300 void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1301 vsd(0x58, dst, src1, src2);
1303 void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1304 vsd(0x5c, dst, src1, src2);
1306 void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1307 vsd(0x5c, dst, src1, src2);
1309 void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1310 vsd(0x59, dst, src1, src2);
1312 void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1313 vsd(0x59, dst, src1, src2);
1315 void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1316 vsd(0x5e, dst, src1, src2);
1318 void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1319 vsd(0x5e, dst, src1, src2);
1321 void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1322 void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1327 // Check the code size generated from label to here.
1328 int SizeOfCodeGeneratedSince(Label* label) {
1329 return pc_offset() - label->pos();
1332 // Mark address of the ExitJSFrame code.
1333 void RecordJSReturn();
1335 // Mark address of a debug break slot.
1336 void RecordDebugBreakSlot();
1338 // Record a comment relocation entry that can be used by a disassembler.
1339 // Use --code-comments to enable.
1340 void RecordComment(const char* msg);
1342 // Record a deoptimization reason that can be used by a log or cpu profiler.
1343 // Use --trace-deopt to enable.
1344 void RecordDeoptReason(const int reason, const int raw_position);
1346 // Allocate a constant pool of the correct size for the generated code.
1347 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1349 // Generate the constant pool for the generated code.
1350 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1352 // Writes a single word of data in the code stream.
1353 // Used for inline tables, e.g., jump-tables.
1354 void db(uint8_t data);
1355 void dd(uint32_t data);
1356 void dq(Label* label);
1358 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1360 // Check if there is less than kGap bytes available in the buffer.
1361 // If this is the case, we need to grow the buffer before emitting
1362 // an instruction or relocation information.
1363 inline bool buffer_overflow() const {
1364 return pc_ >= reloc_info_writer.pos() - kGap;
1367 // Get the number of bytes available in the buffer.
1368 inline int available_space() const {
1369 return static_cast<int>(reloc_info_writer.pos() - pc_);
1372 static bool IsNop(Address addr);
1374 // Avoid overflows for displacements etc.
1375 static const int kMaximalBufferSize = 512*MB;
1377 byte byte_at(int pos) { return buffer_[pos]; }
1378 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1381 // Call near indirect
1382 void call(const Operand& operand);
1385 byte* addr_at(int pos) { return buffer_ + pos; }
1386 uint32_t long_at(int pos) {
1387 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1389 void long_at_put(int pos, uint32_t x) {
1390 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1396 void emit(byte x) { *pc_++ = x; }
1397 inline void emitl(uint32_t x);
1398 inline void emitp(void* x, RelocInfo::Mode rmode);
1399 inline void emitq(uint64_t x);
1400 inline void emitw(uint16_t x);
1401 inline void emit_code_target(Handle<Code> target,
1402 RelocInfo::Mode rmode,
1403 TypeFeedbackId ast_id = TypeFeedbackId::None());
1404 inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
1405 void emit(Immediate x) { emitl(x.value_); }
1407 // Emits a REX prefix that encodes a 64-bit operand size and
1408 // the top bit of both register codes.
1409 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1411 inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1412 inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1413 inline void emit_rex_64(Register reg, Register rm_reg);
1415 // Emits a REX prefix that encodes a 64-bit operand size and
1416 // the top bit of the destination, index, and base register codes.
1417 // The high bit of reg is used for REX.R, the high bit of op's base
1418 // register is used for REX.B, and the high bit of op's index register
1419 // is used for REX.X. REX.W is set.
1420 inline void emit_rex_64(Register reg, const Operand& op);
1421 inline void emit_rex_64(XMMRegister reg, const Operand& op);
1423 // Emits a REX prefix that encodes a 64-bit operand size and
1424 // the top bit of the register code.
1425 // The high bit of register is used for REX.B.
1426 // REX.W is set and REX.R and REX.X are clear.
1427 inline void emit_rex_64(Register rm_reg);
1429 // Emits a REX prefix that encodes a 64-bit operand size and
1430 // the top bit of the index and base register codes.
1431 // The high bit of op's base register is used for REX.B, and the high
1432 // bit of op's index register is used for REX.X.
1433 // REX.W is set and REX.R clear.
1434 inline void emit_rex_64(const Operand& op);
1436 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1437 void emit_rex_64() { emit(0x48); }
1439 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1441 inline void emit_rex_32(Register reg, Register rm_reg);
1443 // The high bit of reg is used for REX.R, the high bit of op's base
1444 // register is used for REX.B, and the high bit of op's index register
1445 // is used for REX.X. REX.W is cleared.
1446 inline void emit_rex_32(Register reg, const Operand& op);
1448 // High bit of rm_reg goes to REX.B.
1449 // REX.W, REX.R and REX.X are clear.
1450 inline void emit_rex_32(Register rm_reg);
1452 // High bit of base goes to REX.B and high bit of index to REX.X.
1453 // REX.W and REX.R are clear.
1454 inline void emit_rex_32(const Operand& op);
1456 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1457 // REX.W is cleared. If no REX bits are set, no byte is emitted.
1458 inline void emit_optional_rex_32(Register reg, Register rm_reg);
1460 // The high bit of reg is used for REX.R, the high bit of op's base
1461 // register is used for REX.B, and the high bit of op's index register
1462 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1464 inline void emit_optional_rex_32(Register reg, const Operand& op);
1466 // As for emit_optional_rex_32(Register, Register), except that
1467 // the registers are XMM registers.
1468 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1470 // As for emit_optional_rex_32(Register, Register), except that
1471 // one of the registers is an XMM registers.
1472 inline void emit_optional_rex_32(XMMRegister reg, Register base);
1474 // As for emit_optional_rex_32(Register, Register), except that
1475 // one of the registers is an XMM registers.
1476 inline void emit_optional_rex_32(Register reg, XMMRegister base);
1478 // As for emit_optional_rex_32(Register, const Operand&), except that
1479 // the register is an XMM register.
1480 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
1482 // Optionally do as emit_rex_32(Register) if the register number has
1483 // the high bit set.
1484 inline void emit_optional_rex_32(Register rm_reg);
1485 inline void emit_optional_rex_32(XMMRegister rm_reg);
1487 // Optionally do as emit_rex_32(const Operand&) if the operand register
1488 // numbers have a high bit set.
1489 inline void emit_optional_rex_32(const Operand& op);
1491 void emit_rex(int size) {
1492 if (size == kInt64Size) {
1495 DCHECK(size == kInt32Size);
1500 void emit_rex(P1 p1, int size) {
1501 if (size == kInt64Size) {
1504 DCHECK(size == kInt32Size);
1505 emit_optional_rex_32(p1);
1509 template<class P1, class P2>
1510 void emit_rex(P1 p1, P2 p2, int size) {
1511 if (size == kInt64Size) {
1512 emit_rex_64(p1, p2);
1514 DCHECK(size == kInt32Size);
1515 emit_optional_rex_32(p1, p2);
1520 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 };
1521 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128 };
1522 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 };
1523 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x2 };
1525 void emit_vex2_byte0() { emit(0xc5); }
1526 inline void emit_vex2_byte1(XMMRegister reg, XMMRegister v, VectorLength l,
1528 void emit_vex3_byte0() { emit(0xc4); }
1529 inline void emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m);
1530 inline void emit_vex3_byte1(XMMRegister reg, const Operand& rm,
1532 inline void emit_vex3_byte2(VexW w, XMMRegister v, VectorLength l,
1534 inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, XMMRegister rm,
1535 VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1537 inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, const Operand& rm,
1538 VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1541 // Emit the ModR/M byte, and optionally the SIB byte and
1542 // 1- or 4-byte offset for a memory operand. Also encodes
1543 // the second operand of the operation, a register or operation
1544 // subcode, into the reg field of the ModR/M byte.
1545 void emit_operand(Register reg, const Operand& adr) {
1546 emit_operand(reg.low_bits(), adr);
1549 // Emit the ModR/M byte, and optionally the SIB byte and
1550 // 1- or 4-byte offset for a memory operand. Also used to encode
1551 // a three-bit opcode extension into the ModR/M byte.
1552 void emit_operand(int rm, const Operand& adr);
1554 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1555 void emit_modrm(Register reg, Register rm_reg) {
1556 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1559 // Emit a ModR/M byte with an operation subcode in the reg field and
1560 // a register in the rm_reg field.
1561 void emit_modrm(int code, Register rm_reg) {
1562 DCHECK(is_uint3(code));
1563 emit(0xC0 | code << 3 | rm_reg.low_bits());
1566 // Emit the code-object-relative offset of the label's position
1567 inline void emit_code_relative_offset(Label* label);
1569 // The first argument is the reg field, the second argument is the r/m field.
1570 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1571 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1572 void emit_sse_operand(Register reg, const Operand& adr);
1573 void emit_sse_operand(XMMRegister dst, Register src);
1574 void emit_sse_operand(Register dst, XMMRegister src);
1576 // Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1577 // AND, OR, XOR, or CMP. The encodings of these operations are all
1578 // similar, differing just in the opcode or in the reg field of the
1580 void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
1581 void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg);
1582 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1583 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
1584 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1585 void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
1586 void arithmetic_op(byte opcode,
1588 const Operand& rm_reg,
1590 // Operate on a byte in memory or register.
1591 void immediate_arithmetic_op_8(byte subcode,
1594 void immediate_arithmetic_op_8(byte subcode,
1597 // Operate on a word in memory or register.
1598 void immediate_arithmetic_op_16(byte subcode,
1601 void immediate_arithmetic_op_16(byte subcode,
1604 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1605 void immediate_arithmetic_op(byte subcode,
1609 void immediate_arithmetic_op(byte subcode,
1614 // Emit machine code for a shift operation.
1615 void shift(Operand dst, Immediate shift_amount, int subcode, int size);
1616 void shift(Register dst, Immediate shift_amount, int subcode, int size);
1617 // Shift dst by cl % 64 bits.
1618 void shift(Register dst, int subcode, int size);
1619 void shift(Operand dst, int subcode, int size);
1621 void emit_farith(int b1, int b2, int i);
1624 // void print(Label* L);
1625 void bind_to(Label* L, int pos);
1627 // record reloc info for current pc_
1628 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1631 void emit_add(Register dst, Register src, int size) {
1632 arithmetic_op(0x03, dst, src, size);
1635 void emit_add(Register dst, Immediate src, int size) {
1636 immediate_arithmetic_op(0x0, dst, src, size);
1639 void emit_add(Register dst, const Operand& src, int size) {
1640 arithmetic_op(0x03, dst, src, size);
1643 void emit_add(const Operand& dst, Register src, int size) {
1644 arithmetic_op(0x1, src, dst, size);
1647 void emit_add(const Operand& dst, Immediate src, int size) {
1648 immediate_arithmetic_op(0x0, dst, src, size);
1651 void emit_and(Register dst, Register src, int size) {
1652 arithmetic_op(0x23, dst, src, size);
1655 void emit_and(Register dst, const Operand& src, int size) {
1656 arithmetic_op(0x23, dst, src, size);
1659 void emit_and(const Operand& dst, Register src, int size) {
1660 arithmetic_op(0x21, src, dst, size);
1663 void emit_and(Register dst, Immediate src, int size) {
1664 immediate_arithmetic_op(0x4, dst, src, size);
1667 void emit_and(const Operand& dst, Immediate src, int size) {
1668 immediate_arithmetic_op(0x4, dst, src, size);
1671 void emit_cmp(Register dst, Register src, int size) {
1672 arithmetic_op(0x3B, dst, src, size);
1675 void emit_cmp(Register dst, const Operand& src, int size) {
1676 arithmetic_op(0x3B, dst, src, size);
1679 void emit_cmp(const Operand& dst, Register src, int size) {
1680 arithmetic_op(0x39, src, dst, size);
1683 void emit_cmp(Register dst, Immediate src, int size) {
1684 immediate_arithmetic_op(0x7, dst, src, size);
1687 void emit_cmp(const Operand& dst, Immediate src, int size) {
1688 immediate_arithmetic_op(0x7, dst, src, size);
1691 void emit_dec(Register dst, int size);
1692 void emit_dec(const Operand& dst, int size);
1694 // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
1695 // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
1697 void emit_idiv(Register src, int size);
1698 void emit_div(Register src, int size);
1700 // Signed multiply instructions.
1701 // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
1702 void emit_imul(Register src, int size);
1703 void emit_imul(const Operand& src, int size);
1704 void emit_imul(Register dst, Register src, int size);
1705 void emit_imul(Register dst, const Operand& src, int size);
1706 void emit_imul(Register dst, Register src, Immediate imm, int size);
1707 void emit_imul(Register dst, const Operand& src, Immediate imm, int size);
1709 void emit_inc(Register dst, int size);
1710 void emit_inc(const Operand& dst, int size);
1712 void emit_lea(Register dst, const Operand& src, int size);
1714 void emit_mov(Register dst, const Operand& src, int size);
1715 void emit_mov(Register dst, Register src, int size);
1716 void emit_mov(const Operand& dst, Register src, int size);
1717 void emit_mov(Register dst, Immediate value, int size);
1718 void emit_mov(const Operand& dst, Immediate value, int size);
1720 void emit_movzxb(Register dst, const Operand& src, int size);
1721 void emit_movzxb(Register dst, Register src, int size);
1722 void emit_movzxw(Register dst, const Operand& src, int size);
1723 void emit_movzxw(Register dst, Register src, int size);
1725 void emit_neg(Register dst, int size);
1726 void emit_neg(const Operand& dst, int size);
1728 void emit_not(Register dst, int size);
1729 void emit_not(const Operand& dst, int size);
1731 void emit_or(Register dst, Register src, int size) {
1732 arithmetic_op(0x0B, dst, src, size);
1735 void emit_or(Register dst, const Operand& src, int size) {
1736 arithmetic_op(0x0B, dst, src, size);
1739 void emit_or(const Operand& dst, Register src, int size) {
1740 arithmetic_op(0x9, src, dst, size);
1743 void emit_or(Register dst, Immediate src, int size) {
1744 immediate_arithmetic_op(0x1, dst, src, size);
1747 void emit_or(const Operand& dst, Immediate src, int size) {
1748 immediate_arithmetic_op(0x1, dst, src, size);
1751 void emit_repmovs(int size);
1753 void emit_sbb(Register dst, Register src, int size) {
1754 arithmetic_op(0x1b, dst, src, size);
1757 void emit_sub(Register dst, Register src, int size) {
1758 arithmetic_op(0x2B, dst, src, size);
1761 void emit_sub(Register dst, Immediate src, int size) {
1762 immediate_arithmetic_op(0x5, dst, src, size);
1765 void emit_sub(Register dst, const Operand& src, int size) {
1766 arithmetic_op(0x2B, dst, src, size);
1769 void emit_sub(const Operand& dst, Register src, int size) {
1770 arithmetic_op(0x29, src, dst, size);
1773 void emit_sub(const Operand& dst, Immediate src, int size) {
1774 immediate_arithmetic_op(0x5, dst, src, size);
1777 void emit_test(Register dst, Register src, int size);
1778 void emit_test(Register reg, Immediate mask, int size);
1779 void emit_test(const Operand& op, Register reg, int size);
1780 void emit_test(const Operand& op, Immediate mask, int size);
1781 void emit_test(Register reg, const Operand& op, int size) {
1782 return emit_test(op, reg, size);
1785 void emit_xchg(Register dst, Register src, int size);
1786 void emit_xchg(Register dst, const Operand& src, int size);
1788 void emit_xor(Register dst, Register src, int size) {
1789 if (size == kInt64Size && dst.code() == src.code()) {
1790 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1791 // there is no need to make this a 64 bit operation.
1792 arithmetic_op(0x33, dst, src, kInt32Size);
1794 arithmetic_op(0x33, dst, src, size);
1798 void emit_xor(Register dst, const Operand& src, int size) {
1799 arithmetic_op(0x33, dst, src, size);
1802 void emit_xor(Register dst, Immediate src, int size) {
1803 immediate_arithmetic_op(0x6, dst, src, size);
1806 void emit_xor(const Operand& dst, Immediate src, int size) {
1807 immediate_arithmetic_op(0x6, dst, src, size);
1810 void emit_xor(const Operand& dst, Register src, int size) {
1811 arithmetic_op(0x31, src, dst, size);
1814 friend class CodePatcher;
1815 friend class EnsureSpace;
1816 friend class RegExpMacroAssemblerX64;
1819 RelocInfoWriter reloc_info_writer;
1821 // Internal reference positions, required for (potential) patching in
1822 // GrowBuffer(); contains only those internal references whose labels
1823 // are already bound.
1824 std::deque<int> internal_reference_positions_;
1826 List< Handle<Code> > code_targets_;
1828 PositionsRecorder positions_recorder_;
1829 friend class PositionsRecorder;
1833 // Helper class that ensures that there is enough space for generating
1834 // instructions and relocation information. The constructor makes
1835 // sure that there is enough space and (in debug mode) the destructor
1836 // checks that we did not generate too much.
1837 class EnsureSpace BASE_EMBEDDED {
1839 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1840 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1842 space_before_ = assembler_->available_space();
1848 int bytes_generated = space_before_ - assembler_->available_space();
1849 DCHECK(bytes_generated < assembler_->kGap);
1854 Assembler* assembler_;
1860 } } // namespace v8::internal
1862 #endif // V8_X64_ASSEMBLER_X64_H_