1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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9 // this list of conditions and the following disclaimer.
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_
43 #include "src/assembler.h"
44 #include "src/compiler.h"
45 #include "src/mips64/constants-mips64.h"
52 // 1) We would prefer to use an enum, but enum values are assignment-
53 // compatible with int, which has caused code-generation bugs.
55 // 2) We would prefer to use a class instead of a struct but we don't like
56 // the register initialization to depend on the particular initialization
57 // order (which appears to be different on OS X, Linux, and Windows for the
58 // installed versions of C++ we tried). Using a struct permits C-style
59 // "initialization". Also, the Register objects cannot be const as this
60 // forces initialization stubs in MSVC, making us dependent on initialization
63 // 3) By not using an enum, we are possibly preventing the compiler from
64 // doing certain constant folds, which may significantly reduce the
65 // code generated for some assembly instructions (because they boil down
66 // to a few constants). If this is a problem, we could change the code
67 // such that we use an enum in optimized mode, and the struct in debug
68 // mode. This way we get the compile-time error checking in debug mode
69 // and best performance in optimized code.
72 // -----------------------------------------------------------------------------
73 // Implementation of Register and FPURegister.
77 static const int kNumRegisters = v8::internal::kNumRegisters;
78 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
79 static const int kSizeInBytes = 8;
80 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
82 inline static int NumAllocatableRegisters();
84 static int ToAllocationIndex(Register reg) {
85 DCHECK((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
86 reg.is(from_code(kCpRegister)));
87 return reg.is(from_code(kCpRegister)) ?
88 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
89 reg.code() - 2; // zero_reg and 'at' are skipped.
92 static Register FromAllocationIndex(int index) {
93 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
94 return index == kMaxNumAllocatableRegisters - 1 ?
95 from_code(kCpRegister) : // Last index is always the 'cp' register.
96 from_code(index + 2); // zero_reg and 'at' are skipped.
99 static const char* AllocationIndexToString(int index) {
100 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
101 const char* const names[] = {
120 static Register from_code(int code) {
121 Register r = { code };
125 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
126 bool is(Register reg) const { return code_ == reg.code_; }
136 // Unfortunately we can't make this private in a struct.
140 #define REGISTER(N, C) \
141 const int kRegister_ ## N ## _Code = C; \
142 const Register N = { C }
144 REGISTER(no_reg, -1);
146 REGISTER(zero_reg, 0);
147 // at: Reserved for synthetic instructions.
149 // v0, v1: Used when returning multiple values from subroutines.
152 // a0 - a4: Used to pass non-FP parameters.
157 // a4 - a7 t0 - t3: Can be used without reservation, act as temporary registers
158 // and are allowed to be destroyed by subroutines.
167 // s0 - s7: Subroutine register variables. Subroutines that write to these
168 // registers must restore their values before exiting so that the caller can
169 // expect the values to be preserved.
180 // k0, k1: Reserved for system calls and interrupt handlers.
185 // sp: Stack pointer.
187 // fp: Frame pointer.
189 // ra: Return address pointer.
195 int ToNumber(Register reg);
197 Register ToRegister(int num);
199 // Coprocessor register.
201 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters;
203 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
204 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
205 // number of Double regs (64-bit regs, or FPU-reg-pairs).
207 // A few double registers are reserved: one as a scratch register and one to
210 // f30: scratch register.
211 static const int kNumReservedRegisters = 2;
212 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 -
213 kNumReservedRegisters;
215 inline static int NumRegisters();
216 inline static int NumAllocatableRegisters();
218 // TODO(turbofan): Proper support for float32.
219 inline static int NumAllocatableAliasedRegisters();
221 inline static int ToAllocationIndex(FPURegister reg);
222 static const char* AllocationIndexToString(int index);
224 static FPURegister FromAllocationIndex(int index) {
225 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
226 return from_code(index * 2);
229 static FPURegister from_code(int code) {
230 FPURegister r = { code };
234 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; }
235 bool is(FPURegister creg) const { return code_ == creg.code_; }
236 FPURegister low() const {
237 // TODO(plind): Create DCHECK for FR=0 mode. This usage suspect for FR=1.
238 // Find low reg of a Double-reg pair, which is the reg itself.
239 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
242 DCHECK(reg.is_valid());
245 FPURegister high() const {
246 // TODO(plind): Create DCHECK for FR=0 mode. This usage illegal in FR=1.
247 // Find high reg of a Doubel-reg pair, which is reg + 1.
248 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
250 reg.code_ = code_ + 1;
251 DCHECK(reg.is_valid());
263 void setcode(int f) {
267 // Unfortunately we can't make this private in a struct.
271 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32
272 // 32-bit registers, f0 through f31. When used as 'double' they are used
273 // in pairs, starting with the even numbered register. So a double operation
274 // on f0 really uses f0 and f1.
275 // (Modern mips hardware also supports 32 64-bit registers, via setting
276 // (privileged) Status Register FR bit to 1. This is used by the N32 ABI,
277 // but it is not in common use. Someday we will want to support this in v8.)
279 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
280 typedef FPURegister DoubleRegister;
281 typedef FPURegister FloatRegister;
283 const FPURegister no_freg = { -1 };
285 const FPURegister f0 = { 0 }; // Return value in hard float mode.
286 const FPURegister f1 = { 1 };
287 const FPURegister f2 = { 2 };
288 const FPURegister f3 = { 3 };
289 const FPURegister f4 = { 4 };
290 const FPURegister f5 = { 5 };
291 const FPURegister f6 = { 6 };
292 const FPURegister f7 = { 7 };
293 const FPURegister f8 = { 8 };
294 const FPURegister f9 = { 9 };
295 const FPURegister f10 = { 10 };
296 const FPURegister f11 = { 11 };
297 const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
298 const FPURegister f13 = { 13 };
299 const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
300 const FPURegister f15 = { 15 };
301 const FPURegister f16 = { 16 };
302 const FPURegister f17 = { 17 };
303 const FPURegister f18 = { 18 };
304 const FPURegister f19 = { 19 };
305 const FPURegister f20 = { 20 };
306 const FPURegister f21 = { 21 };
307 const FPURegister f22 = { 22 };
308 const FPURegister f23 = { 23 };
309 const FPURegister f24 = { 24 };
310 const FPURegister f25 = { 25 };
311 const FPURegister f26 = { 26 };
312 const FPURegister f27 = { 27 };
313 const FPURegister f28 = { 28 };
314 const FPURegister f29 = { 29 };
315 const FPURegister f30 = { 30 };
316 const FPURegister f31 = { 31 };
319 // cp is assumed to be a callee saved register.
320 // Defined using #define instead of "static const Register&" because Clang
321 // complains otherwise when a compilation unit that includes this header
322 // doesn't use the variables.
323 #define kRootRegister s6
325 #define kLithiumScratchReg s3
326 #define kLithiumScratchReg2 s4
327 #define kLithiumScratchDouble f30
328 #define kDoubleRegZero f28
329 // Used on mips64r6 for compare operations.
330 #define kDoubleCompareReg f31
332 // FPU (coprocessor 1) control registers.
333 // Currently only FCSR (#31) is implemented.
334 struct FPUControlRegister {
335 bool is_valid() const { return code_ == kFCSRRegister; }
336 bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
345 void setcode(int f) {
349 // Unfortunately we can't make this private in a struct.
353 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
354 const FPUControlRegister FCSR = { kFCSRRegister };
357 // -----------------------------------------------------------------------------
358 // Machine instruction Operands.
359 const int kSmiShift = kSmiTagSize + kSmiShiftSize;
360 const uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1;
361 // Class Operand represents a shifter operand in data processing instructions.
362 class Operand BASE_EMBEDDED {
365 INLINE(explicit Operand(int64_t immediate,
366 RelocInfo::Mode rmode = RelocInfo::NONE64));
367 INLINE(explicit Operand(const ExternalReference& f));
368 INLINE(explicit Operand(const char* s));
369 INLINE(explicit Operand(Object** opp));
370 INLINE(explicit Operand(Context** cpp));
371 explicit Operand(Handle<Object> handle);
372 INLINE(explicit Operand(Smi* value));
375 INLINE(explicit Operand(Register rm));
377 // Return true if this is a register operand.
378 INLINE(bool is_reg() const);
380 inline int64_t immediate() const {
385 Register rm() const { return rm_; }
389 int64_t imm64_; // Valid if rm_ == no_reg.
390 RelocInfo::Mode rmode_;
392 friend class Assembler;
393 friend class MacroAssembler;
397 // On MIPS we have only one adressing mode with base_reg + offset.
398 // Class MemOperand represents a memory operand in load and store instructions.
399 class MemOperand : public Operand {
401 // Immediate value attached to offset.
403 offset_minus_one = -1,
407 explicit MemOperand(Register rn, int64_t offset = 0);
408 explicit MemOperand(Register rn, int64_t unit, int64_t multiplier,
409 OffsetAddend offset_addend = offset_zero);
410 int32_t offset() const { return offset_; }
412 bool OffsetIsInt16Encodable() const {
413 return is_int16(offset_);
419 friend class Assembler;
423 class Assembler : public AssemblerBase {
425 // Create an assembler. Instructions and relocation information are emitted
426 // into a buffer, with the instructions starting from the beginning and the
427 // relocation information starting from the end of the buffer. See CodeDesc
428 // for a detailed comment on the layout (globals.h).
430 // If the provided buffer is NULL, the assembler allocates and grows its own
431 // buffer, and buffer_size determines the initial buffer size. The buffer is
432 // owned by the assembler and deallocated upon destruction of the assembler.
434 // If the provided buffer is not NULL, the assembler uses the provided buffer
435 // for code generation and assumes its size to be buffer_size. If the buffer
436 // is too small, a fatal error occurs. No deallocation of the buffer is done
437 // upon destruction of the assembler.
438 Assembler(Isolate* isolate, void* buffer, int buffer_size);
439 virtual ~Assembler() { }
441 // GetCode emits any pending (non-emitted) code and fills the descriptor
442 // desc. GetCode() is idempotent; it returns the same result if no other
443 // Assembler functions are invoked in between GetCode() calls.
444 void GetCode(CodeDesc* desc);
446 // Label operations & relative jumps (PPUM Appendix D).
448 // Takes a branch opcode (cc) and a label (L) and generates
449 // either a backward branch or a forward branch and links it
450 // to the label fixup chain. Usage:
452 // Label L; // unbound label
453 // j(cc, &L); // forward branch to unbound label
454 // bind(&L); // bind label to the current pc
455 // j(cc, &L); // backward branch to bound label
456 // bind(&L); // illegal: a label may be bound only once
458 // Note: The same Label can be used for forward and backward branches
459 // but it may be bound only once.
460 void bind(Label* L); // Binds an unbound label L to current code position.
461 // Determines if Label is bound and near enough so that branch instruction
462 // can be used to reach it, instead of jump instruction.
463 bool is_near(Label* L);
465 // Returns the branch offset to the given label from the current code
466 // position. Links the label to the current position if it is still unbound.
467 // Manages the jump elimination optimization if the second parameter is true.
468 int32_t branch_offset(Label* L, bool jump_elimination_allowed);
469 int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed);
470 int32_t branch_offset21(Label* L, bool jump_elimination_allowed);
471 int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed);
472 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
473 int32_t o = branch_offset(L, jump_elimination_allowed);
474 DCHECK((o & 3) == 0); // Assert the offset is aligned.
477 int32_t shifted_branch_offset_compact(Label* L,
478 bool jump_elimination_allowed) {
479 int32_t o = branch_offset_compact(L, jump_elimination_allowed);
480 DCHECK((o & 3) == 0); // Assert the offset is aligned.
483 uint64_t jump_address(Label* L);
485 // Puts a labels target address at the given position.
486 // The high 8 bits are set to zero.
487 void label_at_put(Label* L, int at_offset);
489 // Read/Modify the code target address in the branch/call instruction at pc.
490 static Address target_address_at(Address pc);
491 static void set_target_address_at(Address pc,
493 ICacheFlushMode icache_flush_mode =
494 FLUSH_ICACHE_IF_NEEDED);
495 // On MIPS there is no Constant Pool so we skip that parameter.
496 INLINE(static Address target_address_at(Address pc,
497 ConstantPoolArray* constant_pool)) {
498 return target_address_at(pc);
500 INLINE(static void set_target_address_at(Address pc,
501 ConstantPoolArray* constant_pool,
503 ICacheFlushMode icache_flush_mode =
504 FLUSH_ICACHE_IF_NEEDED)) {
505 set_target_address_at(pc, target, icache_flush_mode);
507 INLINE(static Address target_address_at(Address pc, Code* code)) {
508 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
509 return target_address_at(pc, constant_pool);
511 INLINE(static void set_target_address_at(Address pc,
514 ICacheFlushMode icache_flush_mode =
515 FLUSH_ICACHE_IF_NEEDED)) {
516 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
517 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
520 // Return the code target address at a call site from the return address
521 // of that call in the instruction stream.
522 inline static Address target_address_from_return_address(Address pc);
524 // Return the code target address of the patch debug break slot
525 inline static Address break_address_from_return_address(Address pc);
527 static void JumpLabelToJumpRegister(Address pc);
529 static void QuietNaN(HeapObject* nan);
531 // This sets the branch destination (which gets loaded at the call address).
532 // This is for calls and branches within generated code. The serializer
533 // has already deserialized the lui/ori instructions etc.
534 inline static void deserialization_set_special_target_at(
535 Address instruction_payload, Code* code, Address target) {
536 set_target_address_at(
537 instruction_payload - kInstructionsFor64BitConstant * kInstrSize,
542 // This sets the internal reference at the pc.
543 inline static void deserialization_set_target_internal_reference_at(
544 Address pc, Address target,
545 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
547 // Size of an instruction.
548 static const int kInstrSize = sizeof(Instr);
550 // Difference between address of current opcode and target address offset.
551 static const int kBranchPCOffset = 4;
553 // Here we are patching the address in the LUI/ORI instruction pair.
554 // These values are used in the serialization process and must be zero for
555 // MIPS platform, as Code, Embedded Object or External-reference pointers
556 // are split across two consecutive instructions and don't exist separately
557 // in the code, so the serializer should not step forwards in memory after
558 // a target is resolved and written.
559 static const int kSpecialTargetSize = 0;
561 // Number of consecutive instructions used to store 32bit/64bit constant.
562 // This constant was used in RelocInfo::target_address_address() function
563 // to tell serializer address of the instruction that follows
564 // LUI/ORI instruction pair.
565 static const int kInstructionsFor32BitConstant = 2;
566 static const int kInstructionsFor64BitConstant = 4;
568 // Distance between the instruction referring to the address of the call
569 // target and the return address.
570 static const int kCallTargetAddressOffset = 6 * kInstrSize;
572 // Distance between start of patched return sequence and the emitted address
574 static const int kPatchReturnSequenceAddressOffset = 0;
576 // Distance between start of patched debug break slot and the emitted address
578 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
580 // Difference between address of current opcode and value read from pc
582 static const int kPcLoadDelta = 4;
584 static const int kPatchDebugBreakSlotReturnOffset = 6 * kInstrSize;
586 // Number of instructions used for the JS return sequence. The constant is
587 // used by the debugger to patch the JS return sequence.
588 static const int kJSReturnSequenceInstructions = 7;
589 static const int kJSReturnSequenceLength =
590 kJSReturnSequenceInstructions * kInstrSize;
591 static const int kDebugBreakSlotInstructions = 6;
592 static const int kDebugBreakSlotLength =
593 kDebugBreakSlotInstructions * kInstrSize;
596 // ---------------------------------------------------------------------------
599 // Insert the smallest number of nop instructions
600 // possible to align the pc offset to a multiple
601 // of m. m must be a power of 2 (>= 4).
603 // Aligns code to something that's optimal for a jump target for the platform.
604 void CodeTargetAlign();
606 // Different nop operations are used by the code generator to detect certain
607 // states of the generated code.
608 enum NopMarkerTypes {
612 PROPERTY_ACCESS_INLINED,
613 PROPERTY_ACCESS_INLINED_CONTEXT,
614 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
617 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
619 CODE_AGE_MARKER_NOP = 6,
620 CODE_AGE_SEQUENCE_NOP
623 // Type == 0 is the default non-marking nop. For mips this is a
624 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
625 // marking, to avoid conflict with ssnop and ehb instructions.
626 void nop(unsigned int type = 0) {
628 Register nop_rt_reg = (type == 0) ? zero_reg : at;
629 sll(zero_reg, nop_rt_reg, type, true);
633 // --------Branch-and-jump-instructions----------
634 // We don't use likely variant of instructions.
635 void b(int16_t offset);
636 void b(Label* L) { b(branch_offset(L, false)>>2); }
637 void bal(int16_t offset);
638 void bal(Label* L) { bal(branch_offset(L, false)>>2); }
640 void beq(Register rs, Register rt, int16_t offset);
641 void beq(Register rs, Register rt, Label* L) {
642 beq(rs, rt, branch_offset(L, false) >> 2);
644 void bgez(Register rs, int16_t offset);
645 void bgezc(Register rt, int16_t offset);
646 void bgezc(Register rt, Label* L) {
647 bgezc(rt, branch_offset_compact(L, false)>>2);
649 void bgeuc(Register rs, Register rt, int16_t offset);
650 void bgeuc(Register rs, Register rt, Label* L) {
651 bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
653 void bgec(Register rs, Register rt, int16_t offset);
654 void bgec(Register rs, Register rt, Label* L) {
655 bgec(rs, rt, branch_offset_compact(L, false)>>2);
657 void bgezal(Register rs, int16_t offset);
658 void bgezalc(Register rt, int16_t offset);
659 void bgezalc(Register rt, Label* L) {
660 bgezalc(rt, branch_offset_compact(L, false)>>2);
662 void bgezall(Register rs, int16_t offset);
663 void bgezall(Register rs, Label* L) {
664 bgezall(rs, branch_offset(L, false)>>2);
666 void bgtz(Register rs, int16_t offset);
667 void bgtzc(Register rt, int16_t offset);
668 void bgtzc(Register rt, Label* L) {
669 bgtzc(rt, branch_offset_compact(L, false)>>2);
671 void blez(Register rs, int16_t offset);
672 void blezc(Register rt, int16_t offset);
673 void blezc(Register rt, Label* L) {
674 blezc(rt, branch_offset_compact(L, false)>>2);
676 void bltz(Register rs, int16_t offset);
677 void bltzc(Register rt, int16_t offset);
678 void bltzc(Register rt, Label* L) {
679 bltzc(rt, branch_offset_compact(L, false)>>2);
681 void bltuc(Register rs, Register rt, int16_t offset);
682 void bltuc(Register rs, Register rt, Label* L) {
683 bltuc(rs, rt, branch_offset_compact(L, false)>>2);
685 void bltc(Register rs, Register rt, int16_t offset);
686 void bltc(Register rs, Register rt, Label* L) {
687 bltc(rs, rt, branch_offset_compact(L, false)>>2);
690 void bltzal(Register rs, int16_t offset);
691 void blezalc(Register rt, int16_t offset);
692 void blezalc(Register rt, Label* L) {
693 blezalc(rt, branch_offset_compact(L, false)>>2);
695 void bltzalc(Register rt, int16_t offset);
696 void bltzalc(Register rt, Label* L) {
697 bltzalc(rt, branch_offset_compact(L, false)>>2);
699 void bgtzalc(Register rt, int16_t offset);
700 void bgtzalc(Register rt, Label* L) {
701 bgtzalc(rt, branch_offset_compact(L, false)>>2);
703 void beqzalc(Register rt, int16_t offset);
704 void beqzalc(Register rt, Label* L) {
705 beqzalc(rt, branch_offset_compact(L, false)>>2);
707 void beqc(Register rs, Register rt, int16_t offset);
708 void beqc(Register rs, Register rt, Label* L) {
709 beqc(rs, rt, branch_offset_compact(L, false)>>2);
711 void beqzc(Register rs, int32_t offset);
712 void beqzc(Register rs, Label* L) {
713 beqzc(rs, branch_offset21_compact(L, false)>>2);
715 void bnezalc(Register rt, int16_t offset);
716 void bnezalc(Register rt, Label* L) {
717 bnezalc(rt, branch_offset_compact(L, false)>>2);
719 void bnec(Register rs, Register rt, int16_t offset);
720 void bnec(Register rs, Register rt, Label* L) {
721 bnec(rs, rt, branch_offset_compact(L, false)>>2);
723 void bnezc(Register rt, int32_t offset);
724 void bnezc(Register rt, Label* L) {
725 bnezc(rt, branch_offset21_compact(L, false)>>2);
727 void bne(Register rs, Register rt, int16_t offset);
728 void bne(Register rs, Register rt, Label* L) {
729 bne(rs, rt, branch_offset(L, false)>>2);
731 void bovc(Register rs, Register rt, int16_t offset);
732 void bovc(Register rs, Register rt, Label* L) {
733 bovc(rs, rt, branch_offset_compact(L, false)>>2);
735 void bnvc(Register rs, Register rt, int16_t offset);
736 void bnvc(Register rs, Register rt, Label* L) {
737 bnvc(rs, rt, branch_offset_compact(L, false)>>2);
740 // Never use the int16_t b(l)cond version with a branch offset
741 // instead of using the Label* version.
743 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
744 void j(int64_t target);
745 void jal(int64_t target);
746 void jalr(Register rs, Register rd = ra);
747 void jr(Register target);
748 void j_or_jr(int64_t target, Register rs);
749 void jal_or_jalr(int64_t target, Register rs);
752 // -------Data-processing-instructions---------
755 void addu(Register rd, Register rs, Register rt);
756 void subu(Register rd, Register rs, Register rt);
758 void div(Register rs, Register rt);
759 void divu(Register rs, Register rt);
760 void ddiv(Register rs, Register rt);
761 void ddivu(Register rs, Register rt);
762 void div(Register rd, Register rs, Register rt);
763 void divu(Register rd, Register rs, Register rt);
764 void ddiv(Register rd, Register rs, Register rt);
765 void ddivu(Register rd, Register rs, Register rt);
766 void mod(Register rd, Register rs, Register rt);
767 void modu(Register rd, Register rs, Register rt);
768 void dmod(Register rd, Register rs, Register rt);
769 void dmodu(Register rd, Register rs, Register rt);
771 void mul(Register rd, Register rs, Register rt);
772 void muh(Register rd, Register rs, Register rt);
773 void mulu(Register rd, Register rs, Register rt);
774 void muhu(Register rd, Register rs, Register rt);
775 void mult(Register rs, Register rt);
776 void multu(Register rs, Register rt);
777 void dmul(Register rd, Register rs, Register rt);
778 void dmuh(Register rd, Register rs, Register rt);
779 void dmulu(Register rd, Register rs, Register rt);
780 void dmuhu(Register rd, Register rs, Register rt);
781 void daddu(Register rd, Register rs, Register rt);
782 void dsubu(Register rd, Register rs, Register rt);
783 void dmult(Register rs, Register rt);
784 void dmultu(Register rs, Register rt);
786 void addiu(Register rd, Register rs, int32_t j);
787 void daddiu(Register rd, Register rs, int32_t j);
790 void and_(Register rd, Register rs, Register rt);
791 void or_(Register rd, Register rs, Register rt);
792 void xor_(Register rd, Register rs, Register rt);
793 void nor(Register rd, Register rs, Register rt);
795 void andi(Register rd, Register rs, int32_t j);
796 void ori(Register rd, Register rs, int32_t j);
797 void xori(Register rd, Register rs, int32_t j);
798 void lui(Register rd, int32_t j);
799 void aui(Register rs, Register rt, int32_t j);
800 void daui(Register rs, Register rt, int32_t j);
801 void dahi(Register rs, int32_t j);
802 void dati(Register rs, int32_t j);
805 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
806 // and may cause problems in normal code. coming_from_nop makes sure this
808 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
809 void sllv(Register rd, Register rt, Register rs);
810 void srl(Register rd, Register rt, uint16_t sa);
811 void srlv(Register rd, Register rt, Register rs);
812 void sra(Register rt, Register rd, uint16_t sa);
813 void srav(Register rt, Register rd, Register rs);
814 void rotr(Register rd, Register rt, uint16_t sa);
815 void rotrv(Register rd, Register rt, Register rs);
816 void dsll(Register rd, Register rt, uint16_t sa);
817 void dsllv(Register rd, Register rt, Register rs);
818 void dsrl(Register rd, Register rt, uint16_t sa);
819 void dsrlv(Register rd, Register rt, Register rs);
820 void drotr(Register rd, Register rt, uint16_t sa);
821 void drotrv(Register rd, Register rt, Register rs);
822 void dsra(Register rt, Register rd, uint16_t sa);
823 void dsrav(Register rd, Register rt, Register rs);
824 void dsll32(Register rt, Register rd, uint16_t sa);
825 void dsrl32(Register rt, Register rd, uint16_t sa);
826 void dsra32(Register rt, Register rd, uint16_t sa);
829 // ------------Memory-instructions-------------
831 void lb(Register rd, const MemOperand& rs);
832 void lbu(Register rd, const MemOperand& rs);
833 void lh(Register rd, const MemOperand& rs);
834 void lhu(Register rd, const MemOperand& rs);
835 void lw(Register rd, const MemOperand& rs);
836 void lwu(Register rd, const MemOperand& rs);
837 void lwl(Register rd, const MemOperand& rs);
838 void lwr(Register rd, const MemOperand& rs);
839 void sb(Register rd, const MemOperand& rs);
840 void sh(Register rd, const MemOperand& rs);
841 void sw(Register rd, const MemOperand& rs);
842 void swl(Register rd, const MemOperand& rs);
843 void swr(Register rd, const MemOperand& rs);
844 void ldl(Register rd, const MemOperand& rs);
845 void ldr(Register rd, const MemOperand& rs);
846 void sdl(Register rd, const MemOperand& rs);
847 void sdr(Register rd, const MemOperand& rs);
848 void ld(Register rd, const MemOperand& rs);
849 void sd(Register rd, const MemOperand& rs);
852 // ----------------Prefetch--------------------
854 void pref(int32_t hint, const MemOperand& rs);
857 // -------------Misc-instructions--------------
859 // Break / Trap instructions.
860 void break_(uint32_t code, bool break_as_stop = false);
861 void stop(const char* msg, uint32_t code = kMaxStopCode);
862 void tge(Register rs, Register rt, uint16_t code);
863 void tgeu(Register rs, Register rt, uint16_t code);
864 void tlt(Register rs, Register rt, uint16_t code);
865 void tltu(Register rs, Register rt, uint16_t code);
866 void teq(Register rs, Register rt, uint16_t code);
867 void tne(Register rs, Register rt, uint16_t code);
869 // Move from HI/LO register.
870 void mfhi(Register rd);
871 void mflo(Register rd);
874 void slt(Register rd, Register rs, Register rt);
875 void sltu(Register rd, Register rs, Register rt);
876 void slti(Register rd, Register rs, int32_t j);
877 void sltiu(Register rd, Register rs, int32_t j);
880 void movz(Register rd, Register rs, Register rt);
881 void movn(Register rd, Register rs, Register rt);
882 void movt(Register rd, Register rs, uint16_t cc = 0);
883 void movf(Register rd, Register rs, uint16_t cc = 0);
885 void sel(SecondaryField fmt, FPURegister fd, FPURegister ft,
886 FPURegister fs, uint8_t sel);
887 void seleqz(Register rs, Register rt, Register rd);
888 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister ft,
890 void selnez(Register rs, Register rt, Register rd);
891 void selnez(SecondaryField fmt, FPURegister fd, FPURegister ft,
895 void clz(Register rd, Register rs);
896 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
897 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
898 void dext_(Register rt, Register rs, uint16_t pos, uint16_t size);
900 // --------Coprocessor-instructions----------------
902 // Load, store, and move.
903 void lwc1(FPURegister fd, const MemOperand& src);
904 void ldc1(FPURegister fd, const MemOperand& src);
906 void swc1(FPURegister fs, const MemOperand& dst);
907 void sdc1(FPURegister fs, const MemOperand& dst);
909 void mtc1(Register rt, FPURegister fs);
910 void mthc1(Register rt, FPURegister fs);
911 void dmtc1(Register rt, FPURegister fs);
913 void mfc1(Register rt, FPURegister fs);
914 void mfhc1(Register rt, FPURegister fs);
915 void dmfc1(Register rt, FPURegister fs);
917 void ctc1(Register rt, FPUControlRegister fs);
918 void cfc1(Register rt, FPUControlRegister fs);
921 void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
922 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
923 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
924 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
925 void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
926 void abs_d(FPURegister fd, FPURegister fs);
927 void mov_d(FPURegister fd, FPURegister fs);
928 void neg_d(FPURegister fd, FPURegister fs);
929 void sqrt_d(FPURegister fd, FPURegister fs);
932 void cvt_w_s(FPURegister fd, FPURegister fs);
933 void cvt_w_d(FPURegister fd, FPURegister fs);
934 void trunc_w_s(FPURegister fd, FPURegister fs);
935 void trunc_w_d(FPURegister fd, FPURegister fs);
936 void round_w_s(FPURegister fd, FPURegister fs);
937 void round_w_d(FPURegister fd, FPURegister fs);
938 void floor_w_s(FPURegister fd, FPURegister fs);
939 void floor_w_d(FPURegister fd, FPURegister fs);
940 void ceil_w_s(FPURegister fd, FPURegister fs);
941 void ceil_w_d(FPURegister fd, FPURegister fs);
943 void cvt_l_s(FPURegister fd, FPURegister fs);
944 void cvt_l_d(FPURegister fd, FPURegister fs);
945 void trunc_l_s(FPURegister fd, FPURegister fs);
946 void trunc_l_d(FPURegister fd, FPURegister fs);
947 void round_l_s(FPURegister fd, FPURegister fs);
948 void round_l_d(FPURegister fd, FPURegister fs);
949 void floor_l_s(FPURegister fd, FPURegister fs);
950 void floor_l_d(FPURegister fd, FPURegister fs);
951 void ceil_l_s(FPURegister fd, FPURegister fs);
952 void ceil_l_d(FPURegister fd, FPURegister fs);
954 void min(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
955 void mina(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
956 void max(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
957 void maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
959 void cvt_s_w(FPURegister fd, FPURegister fs);
960 void cvt_s_l(FPURegister fd, FPURegister fs);
961 void cvt_s_d(FPURegister fd, FPURegister fs);
963 void cvt_d_w(FPURegister fd, FPURegister fs);
964 void cvt_d_l(FPURegister fd, FPURegister fs);
965 void cvt_d_s(FPURegister fd, FPURegister fs);
967 // Conditions and branches for MIPSr6.
968 void cmp(FPUCondition cond, SecondaryField fmt,
969 FPURegister fd, FPURegister ft, FPURegister fs);
971 void bc1eqz(int16_t offset, FPURegister ft);
972 void bc1eqz(Label* L, FPURegister ft) {
973 bc1eqz(branch_offset(L, false)>>2, ft);
975 void bc1nez(int16_t offset, FPURegister ft);
976 void bc1nez(Label* L, FPURegister ft) {
977 bc1nez(branch_offset(L, false)>>2, ft);
980 // Conditions and branches for non MIPSr6.
981 void c(FPUCondition cond, SecondaryField fmt,
982 FPURegister ft, FPURegister fs, uint16_t cc = 0);
984 void bc1f(int16_t offset, uint16_t cc = 0);
985 void bc1f(Label* L, uint16_t cc = 0) {
986 bc1f(branch_offset(L, false)>>2, cc);
988 void bc1t(int16_t offset, uint16_t cc = 0);
989 void bc1t(Label* L, uint16_t cc = 0) {
990 bc1t(branch_offset(L, false)>>2, cc);
992 void fcmp(FPURegister src1, const double src2, FPUCondition cond);
994 // Check the code size generated from label to here.
995 int SizeOfCodeGeneratedSince(Label* label) {
996 return pc_offset() - label->pos();
999 // Check the number of instructions generated from label to here.
1000 int InstructionsGeneratedSince(Label* label) {
1001 return SizeOfCodeGeneratedSince(label) / kInstrSize;
1004 // Class for scoping postponing the trampoline pool generation.
1005 class BlockTrampolinePoolScope {
1007 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
1008 assem_->StartBlockTrampolinePool();
1010 ~BlockTrampolinePoolScope() {
1011 assem_->EndBlockTrampolinePool();
1017 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
1020 // Class for postponing the assembly buffer growth. Typically used for
1021 // sequences of instructions that must be emitted as a unit, before
1022 // buffer growth (and relocation) can occur.
1023 // This blocking scope is not nestable.
1024 class BlockGrowBufferScope {
1026 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) {
1027 assem_->StartBlockGrowBuffer();
1029 ~BlockGrowBufferScope() {
1030 assem_->EndBlockGrowBuffer();
1036 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope);
1041 // Mark address of the ExitJSFrame code.
1042 void RecordJSReturn();
1044 // Mark address of a debug break slot.
1045 void RecordDebugBreakSlot();
1047 // Record the AST id of the CallIC being compiled, so that it can be placed
1048 // in the relocation information.
1049 void SetRecordedAstId(TypeFeedbackId ast_id) {
1050 DCHECK(recorded_ast_id_.IsNone());
1051 recorded_ast_id_ = ast_id;
1054 TypeFeedbackId RecordedAstId() {
1055 DCHECK(!recorded_ast_id_.IsNone());
1056 return recorded_ast_id_;
1059 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
1061 // Record a comment relocation entry that can be used by a disassembler.
1062 // Use --code-comments to enable.
1063 void RecordComment(const char* msg);
1065 // Record a deoptimization reason that can be used by a log or cpu profiler.
1066 // Use --trace-deopt to enable.
1067 void RecordDeoptReason(const int reason, const SourcePosition position);
1069 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
1072 // Writes a single byte or word of data in the code stream. Used for
1073 // inline tables, e.g., jump-tables.
1074 void db(uint8_t data);
1075 void dd(uint32_t data);
1076 void dd(Label* label);
1078 // Emits the address of the code stub's first instruction.
1079 void emit_code_stub_address(Code* stub);
1081 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1083 // Postpone the generation of the trampoline pool for the specified number of
1085 void BlockTrampolinePoolFor(int instructions);
1087 // Check if there is less than kGap bytes available in the buffer.
1088 // If this is the case, we need to grow the buffer before emitting
1089 // an instruction or relocation information.
1090 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
1092 // Get the number of bytes available in the buffer.
1093 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1095 // Read/patch instructions.
1096 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
1097 static void instr_at_put(byte* pc, Instr instr) {
1098 *reinterpret_cast<Instr*>(pc) = instr;
1100 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
1101 void instr_at_put(int pos, Instr instr) {
1102 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
1105 // Check if an instruction is a branch of some kind.
1106 static bool IsBranch(Instr instr);
1107 static bool IsBeq(Instr instr);
1108 static bool IsBne(Instr instr);
1110 static bool IsJump(Instr instr);
1111 static bool IsJ(Instr instr);
1112 static bool IsLui(Instr instr);
1113 static bool IsOri(Instr instr);
1115 static bool IsJal(Instr instr);
1116 static bool IsJr(Instr instr);
1117 static bool IsJalr(Instr instr);
1119 static bool IsNop(Instr instr, unsigned int type);
1120 static bool IsPop(Instr instr);
1121 static bool IsPush(Instr instr);
1122 static bool IsLwRegFpOffset(Instr instr);
1123 static bool IsSwRegFpOffset(Instr instr);
1124 static bool IsLwRegFpNegOffset(Instr instr);
1125 static bool IsSwRegFpNegOffset(Instr instr);
1127 static Register GetRtReg(Instr instr);
1128 static Register GetRsReg(Instr instr);
1129 static Register GetRdReg(Instr instr);
1131 static uint32_t GetRt(Instr instr);
1132 static uint32_t GetRtField(Instr instr);
1133 static uint32_t GetRs(Instr instr);
1134 static uint32_t GetRsField(Instr instr);
1135 static uint32_t GetRd(Instr instr);
1136 static uint32_t GetRdField(Instr instr);
1137 static uint32_t GetSa(Instr instr);
1138 static uint32_t GetSaField(Instr instr);
1139 static uint32_t GetOpcodeField(Instr instr);
1140 static uint32_t GetFunction(Instr instr);
1141 static uint32_t GetFunctionField(Instr instr);
1142 static uint32_t GetImmediate16(Instr instr);
1143 static uint32_t GetLabelConst(Instr instr);
1145 static int32_t GetBranchOffset(Instr instr);
1146 static bool IsLw(Instr instr);
1147 static int16_t GetLwOffset(Instr instr);
1148 static Instr SetLwOffset(Instr instr, int16_t offset);
1150 static bool IsSw(Instr instr);
1151 static Instr SetSwOffset(Instr instr, int16_t offset);
1152 static bool IsAddImmediate(Instr instr);
1153 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1155 static bool IsAndImmediate(Instr instr);
1156 static bool IsEmittedConstant(Instr instr);
1158 void CheckTrampolinePool();
1160 // Allocate a constant pool of the correct size for the generated code.
1161 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1163 // Generate the constant pool for the generated code.
1164 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1167 // Relocation for a type-recording IC has the AST id added to it. This
1168 // member variable is a way to pass the information from the call site to
1169 // the relocation info.
1170 TypeFeedbackId recorded_ast_id_;
1172 inline static void set_target_internal_reference_encoded_at(Address pc,
1175 int64_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1177 // Decode branch instruction at pos and return branch target pos.
1178 int target_at(int pos, bool is_internal);
1180 // Patch branch instruction at pos to branch to given branch target pos.
1181 void target_at_put(int pos, int target_pos, bool is_internal);
1183 // Say if we need to relocate with this mode.
1184 bool MustUseReg(RelocInfo::Mode rmode);
1186 // Record reloc info for current pc_.
1187 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1189 // Block the emission of the trampoline pool before pc_offset.
1190 void BlockTrampolinePoolBefore(int pc_offset) {
1191 if (no_trampoline_pool_before_ < pc_offset)
1192 no_trampoline_pool_before_ = pc_offset;
1195 void StartBlockTrampolinePool() {
1196 trampoline_pool_blocked_nesting_++;
1199 void EndBlockTrampolinePool() {
1200 trampoline_pool_blocked_nesting_--;
1203 bool is_trampoline_pool_blocked() const {
1204 return trampoline_pool_blocked_nesting_ > 0;
1207 bool has_exception() const {
1208 return internal_trampoline_exception_;
1211 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi);
1213 bool is_trampoline_emitted() const {
1214 return trampoline_emitted_;
1217 // Temporarily block automatic assembly buffer growth.
1218 void StartBlockGrowBuffer() {
1219 DCHECK(!block_buffer_growth_);
1220 block_buffer_growth_ = true;
1223 void EndBlockGrowBuffer() {
1224 DCHECK(block_buffer_growth_);
1225 block_buffer_growth_ = false;
1228 bool is_buffer_growth_blocked() const {
1229 return block_buffer_growth_;
1233 // Buffer size and constant pool distance are checked together at regular
1234 // intervals of kBufferCheckInterval emitted bytes.
1235 static const int kBufferCheckInterval = 1*KB/2;
1238 // The relocation writer's position is at least kGap bytes below the end of
1239 // the generated instructions. This is so that multi-instruction sequences do
1240 // not have to check for overflow. The same is true for writes of large
1241 // relocation info entries.
1242 static const int kGap = 32;
1245 // Repeated checking whether the trampoline pool should be emitted is rather
1246 // expensive. By default we only check again once a number of instructions
1247 // has been generated.
1248 static const int kCheckConstIntervalInst = 32;
1249 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1251 int next_buffer_check_; // pc offset of next buffer check.
1253 // Emission of the trampoline pool may be blocked in some code sequences.
1254 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
1255 int no_trampoline_pool_before_; // Block emission before this pc offset.
1257 // Keep track of the last emitted pool to guarantee a maximal distance.
1258 int last_trampoline_pool_end_; // pc offset of the end of the last pool.
1260 // Automatic growth of the assembly buffer may be blocked for some sequences.
1261 bool block_buffer_growth_; // Block growth when true.
1263 // Relocation information generation.
1264 // Each relocation is encoded as a variable size value.
1265 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1266 RelocInfoWriter reloc_info_writer;
1268 // The bound position, before this we cannot do instruction elimination.
1269 int last_bound_pos_;
1272 inline void CheckBuffer();
1274 inline void emit(Instr x);
1275 inline void emit(uint64_t x);
1276 inline void CheckTrampolinePoolQuick();
1278 // Instruction generation.
1279 // We have 3 different kind of encoding layout on MIPS.
1280 // However due to many different types of objects encoded in the same fields
1281 // we have quite a few aliases for each mode.
1282 // Using the same structure to refer to Register and FPURegister would spare a
1283 // few aliases, but mixing both does not look clean to me.
1284 // Anyway we could surely implement this differently.
1286 void GenInstrRegister(Opcode opcode,
1291 SecondaryField func = NULLSF);
1293 void GenInstrRegister(Opcode opcode,
1298 SecondaryField func);
1300 void GenInstrRegister(Opcode opcode,
1305 SecondaryField func = NULLSF);
1307 void GenInstrRegister(Opcode opcode,
1312 SecondaryField func = NULLSF);
1314 void GenInstrRegister(Opcode opcode,
1319 SecondaryField func = NULLSF);
1321 void GenInstrRegister(Opcode opcode,
1324 FPUControlRegister fs,
1325 SecondaryField func = NULLSF);
1328 void GenInstrImmediate(Opcode opcode,
1332 void GenInstrImmediate(Opcode opcode,
1336 void GenInstrImmediate(Opcode opcode,
1342 void GenInstrJump(Opcode opcode,
1346 void LoadRegPlusOffsetToAt(const MemOperand& src);
1349 void print(Label* L);
1350 void bind_to(Label* L, int pos);
1351 void next(Label* L, bool is_internal);
1353 // One trampoline consists of:
1354 // - space for trampoline slots,
1355 // - space for labels.
1357 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1358 // Space for trampoline slots preceeds space for labels. Each label is of one
1359 // instruction size, so total amount for labels is equal to
1360 // label_count * kInstrSize.
1366 free_slot_count_ = 0;
1369 Trampoline(int start, int slot_count) {
1372 free_slot_count_ = slot_count;
1373 end_ = start + slot_count * kTrampolineSlotsSize;
1382 int trampoline_slot = kInvalidSlotPos;
1383 if (free_slot_count_ <= 0) {
1384 // We have run out of space on trampolines.
1385 // Make sure we fail in debug mode, so we become aware of each case
1386 // when this happens.
1388 // Internal exception will be caught.
1390 trampoline_slot = next_slot_;
1392 next_slot_ += kTrampolineSlotsSize;
1394 return trampoline_slot;
1401 int free_slot_count_;
1404 int32_t get_trampoline_entry(int32_t pos);
1405 int unbound_labels_count_;
1406 // If trampoline is emitted, generated code is becoming large. As this is
1407 // already a slow case which can possibly break our code generation for the
1408 // extreme case, we use this information to trigger different mode of
1409 // branch instruction generation, where we use jump instructions rather
1410 // than regular branch instructions.
1411 bool trampoline_emitted_;
1412 static const int kTrampolineSlotsSize = 6 * kInstrSize;
1413 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1414 static const int kInvalidSlotPos = -1;
1416 // Internal reference positions, required for unbounded internal reference
1418 std::set<int64_t> internal_reference_positions_;
1420 Trampoline trampoline_;
1421 bool internal_trampoline_exception_;
1423 friend class RegExpMacroAssemblerMIPS;
1424 friend class RelocInfo;
1425 friend class CodePatcher;
1426 friend class BlockTrampolinePoolScope;
1428 PositionsRecorder positions_recorder_;
1429 friend class PositionsRecorder;
1430 friend class EnsureSpace;
1434 class EnsureSpace BASE_EMBEDDED {
1436 explicit EnsureSpace(Assembler* assembler) {
1437 assembler->CheckBuffer();
1441 } } // namespace v8::internal
1443 #endif // V8_ARM_ASSEMBLER_MIPS_H_