1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
38 #if V8_TARGET_ARCH_MIPS64
40 #include "src/base/cpu.h"
41 #include "src/mips64/assembler-mips64-inl.h"
42 #include "src/serialize.h"
48 // Get the CPU features enabled by the build. For cross compilation the
49 // preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
50 // can be defined to enable FPU instructions when building the
52 static unsigned CpuFeaturesImpliedByCompiler() {
54 #ifdef CAN_USE_FPU_INSTRUCTIONS
56 #endif // def CAN_USE_FPU_INSTRUCTIONS
58 // If the compiler is allowed to use FPU then we can use FPU too in our code
59 // generation even when generating snapshots. This won't work for cross
61 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
69 const char* DoubleRegister::AllocationIndexToString(int index) {
70 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
71 const char* const names[] = {
91 void CpuFeatures::ProbeImpl(bool cross_compile) {
92 supported_ |= CpuFeaturesImpliedByCompiler();
94 // Only use statically determined features for cross compile (snapshot).
95 if (cross_compile) return;
97 // If the compiler is allowed to use fpu then we can use fpu too in our
100 // For the simulator build, use FPU.
101 supported_ |= 1u << FPU;
103 // Probe for additional features at runtime.
105 if (cpu.has_fpu()) supported_ |= 1u << FPU;
110 void CpuFeatures::PrintTarget() { }
111 void CpuFeatures::PrintFeatures() { }
114 int ToNumber(Register reg) {
115 DCHECK(reg.is_valid());
116 const int kNumbers[] = {
150 return kNumbers[reg.code()];
154 Register ToRegister(int num) {
155 DCHECK(num >= 0 && num < kNumRegisters);
156 const Register kRegisters[] = {
160 a0, a1, a2, a3, a4, a5, a6, a7,
162 s0, s1, s2, s3, s4, s5, s6, s7,
170 return kRegisters[num];
174 // -----------------------------------------------------------------------------
175 // Implementation of RelocInfo.
177 const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
178 1 << RelocInfo::INTERNAL_REFERENCE |
179 1 << RelocInfo::INTERNAL_REFERENCE_ENCODED;
182 bool RelocInfo::IsCodedSpecially() {
183 // The deserializer needs to know whether a pointer is specially coded. Being
184 // specially coded on MIPS means that it is a lui/ori instruction, and that is
185 // always the case inside code objects.
190 bool RelocInfo::IsInConstantPool() {
195 // Patch the code at the current address with the supplied instructions.
196 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
197 Instr* pc = reinterpret_cast<Instr*>(pc_);
198 Instr* instr = reinterpret_cast<Instr*>(instructions);
199 for (int i = 0; i < instruction_count; i++) {
200 *(pc + i) = *(instr + i);
203 // Indicate that code has changed.
204 CpuFeatures::FlushICache(pc_, instruction_count * Assembler::kInstrSize);
208 // Patch the code at the current PC with a call to the target address.
209 // Additional guard instructions can be added if required.
210 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
211 // Patch the code at the current address with a call to the target.
212 UNIMPLEMENTED_MIPS();
216 // -----------------------------------------------------------------------------
217 // Implementation of Operand and MemOperand.
218 // See assembler-mips-inl.h for inlined constructors.
220 Operand::Operand(Handle<Object> handle) {
221 AllowDeferredHandleDereference using_raw_address;
223 // Verify all Objects referred by code are NOT in new space.
224 Object* obj = *handle;
225 if (obj->IsHeapObject()) {
226 DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
227 imm64_ = reinterpret_cast<intptr_t>(handle.location());
228 rmode_ = RelocInfo::EMBEDDED_OBJECT;
230 // No relocation needed.
231 imm64_ = reinterpret_cast<intptr_t>(obj);
232 rmode_ = RelocInfo::NONE64;
237 MemOperand::MemOperand(Register rm, int64_t offset) : Operand(rm) {
242 MemOperand::MemOperand(Register rm, int64_t unit, int64_t multiplier,
243 OffsetAddend offset_addend) : Operand(rm) {
244 offset_ = unit * multiplier + offset_addend;
248 // -----------------------------------------------------------------------------
249 // Specific instructions, constants, and masks.
251 static const int kNegOffset = 0x00008000;
252 // daddiu(sp, sp, 8) aka Pop() operation or part of Pop(r)
253 // operations as post-increment of sp.
254 const Instr kPopInstruction = DADDIU | (kRegister_sp_Code << kRsShift)
255 | (kRegister_sp_Code << kRtShift)
256 | (kPointerSize & kImm16Mask); // NOLINT
257 // daddiu(sp, sp, -8) part of Push(r) operation as pre-decrement of sp.
258 const Instr kPushInstruction = DADDIU | (kRegister_sp_Code << kRsShift)
259 | (kRegister_sp_Code << kRtShift)
260 | (-kPointerSize & kImm16Mask); // NOLINT
261 // sd(r, MemOperand(sp, 0))
262 const Instr kPushRegPattern = SD | (kRegister_sp_Code << kRsShift)
263 | (0 & kImm16Mask); // NOLINT
264 // ld(r, MemOperand(sp, 0))
265 const Instr kPopRegPattern = LD | (kRegister_sp_Code << kRsShift)
266 | (0 & kImm16Mask); // NOLINT
268 const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
269 | (0 & kImm16Mask); // NOLINT
271 const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
272 | (0 & kImm16Mask); // NOLINT
274 const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
275 | (kNegOffset & kImm16Mask); // NOLINT
277 const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
278 | (kNegOffset & kImm16Mask); // NOLINT
279 // A mask for the Rt register for push, pop, lw, sw instructions.
280 const Instr kRtMask = kRtFieldMask;
281 const Instr kLwSwInstrTypeMask = 0xffe00000;
282 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask;
283 const Instr kLwSwOffsetMask = kImm16Mask;
286 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
287 : AssemblerBase(isolate, buffer, buffer_size),
288 recorded_ast_id_(TypeFeedbackId::None()),
289 positions_recorder_(this) {
290 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
292 last_trampoline_pool_end_ = 0;
293 no_trampoline_pool_before_ = 0;
294 trampoline_pool_blocked_nesting_ = 0;
295 // We leave space (16 * kTrampolineSlotsSize)
296 // for BlockTrampolinePoolScope buffer.
297 next_buffer_check_ = FLAG_force_long_branches
298 ? kMaxInt : kMaxBranchOffset - kTrampolineSlotsSize * 16;
299 internal_trampoline_exception_ = false;
302 trampoline_emitted_ = FLAG_force_long_branches;
303 unbound_labels_count_ = 0;
304 block_buffer_growth_ = false;
306 ClearRecordedAstId();
310 void Assembler::GetCode(CodeDesc* desc) {
311 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
312 // Set up code descriptor.
313 desc->buffer = buffer_;
314 desc->buffer_size = buffer_size_;
315 desc->instr_size = pc_offset();
316 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
321 void Assembler::Align(int m) {
322 DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m));
323 while ((pc_offset() & (m - 1)) != 0) {
329 void Assembler::CodeTargetAlign() {
330 // No advantage to aligning branch/call targets to more than
331 // single instruction, that I am aware of.
336 Register Assembler::GetRtReg(Instr instr) {
338 rt.code_ = (instr & kRtFieldMask) >> kRtShift;
343 Register Assembler::GetRsReg(Instr instr) {
345 rs.code_ = (instr & kRsFieldMask) >> kRsShift;
350 Register Assembler::GetRdReg(Instr instr) {
352 rd.code_ = (instr & kRdFieldMask) >> kRdShift;
357 uint32_t Assembler::GetRt(Instr instr) {
358 return (instr & kRtFieldMask) >> kRtShift;
362 uint32_t Assembler::GetRtField(Instr instr) {
363 return instr & kRtFieldMask;
367 uint32_t Assembler::GetRs(Instr instr) {
368 return (instr & kRsFieldMask) >> kRsShift;
372 uint32_t Assembler::GetRsField(Instr instr) {
373 return instr & kRsFieldMask;
377 uint32_t Assembler::GetRd(Instr instr) {
378 return (instr & kRdFieldMask) >> kRdShift;
382 uint32_t Assembler::GetRdField(Instr instr) {
383 return instr & kRdFieldMask;
387 uint32_t Assembler::GetSa(Instr instr) {
388 return (instr & kSaFieldMask) >> kSaShift;
392 uint32_t Assembler::GetSaField(Instr instr) {
393 return instr & kSaFieldMask;
397 uint32_t Assembler::GetOpcodeField(Instr instr) {
398 return instr & kOpcodeMask;
402 uint32_t Assembler::GetFunction(Instr instr) {
403 return (instr & kFunctionFieldMask) >> kFunctionShift;
407 uint32_t Assembler::GetFunctionField(Instr instr) {
408 return instr & kFunctionFieldMask;
412 uint32_t Assembler::GetImmediate16(Instr instr) {
413 return instr & kImm16Mask;
417 uint32_t Assembler::GetLabelConst(Instr instr) {
418 return instr & ~kImm16Mask;
422 bool Assembler::IsPop(Instr instr) {
423 return (instr & ~kRtMask) == kPopRegPattern;
427 bool Assembler::IsPush(Instr instr) {
428 return (instr & ~kRtMask) == kPushRegPattern;
432 bool Assembler::IsSwRegFpOffset(Instr instr) {
433 return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
437 bool Assembler::IsLwRegFpOffset(Instr instr) {
438 return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
442 bool Assembler::IsSwRegFpNegOffset(Instr instr) {
443 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
444 kSwRegFpNegOffsetPattern);
448 bool Assembler::IsLwRegFpNegOffset(Instr instr) {
449 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
450 kLwRegFpNegOffsetPattern);
454 // Labels refer to positions in the (to be) generated code.
455 // There are bound, linked, and unused labels.
457 // Bound labels refer to known positions in the already
458 // generated code. pos() is the position the label refers to.
460 // Linked labels refer to unknown positions in the code
461 // to be generated; pos() is the position of the last
462 // instruction using the label.
464 // The link chain is terminated by a value in the instruction of -1,
465 // which is an otherwise illegal value (branch -1 is inf loop).
466 // The instruction 16-bit offset field addresses 32-bit words, but in
467 // code is conv to an 18-bit value addressing bytes, hence the -4 value.
469 const int kEndOfChain = -4;
470 // Determines the end of the Jump chain (a subset of the label link chain).
471 const int kEndOfJumpChain = 0;
474 bool Assembler::IsBranch(Instr instr) {
475 uint32_t opcode = GetOpcodeField(instr);
476 uint32_t rt_field = GetRtField(instr);
477 uint32_t rs_field = GetRsField(instr);
478 // Checks if the instruction is a branch.
479 return opcode == BEQ ||
487 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
488 rt_field == BLTZAL || rt_field == BGEZAL)) ||
489 (opcode == COP1 && rs_field == BC1) || // Coprocessor branch.
490 (opcode == COP1 && rs_field == BC1EQZ) ||
491 (opcode == COP1 && rs_field == BC1NEZ);
495 bool Assembler::IsEmittedConstant(Instr instr) {
496 uint32_t label_constant = GetLabelConst(instr);
497 return label_constant == 0; // Emitted label const in reg-exp engine.
501 bool Assembler::IsBeq(Instr instr) {
502 return GetOpcodeField(instr) == BEQ;
506 bool Assembler::IsBne(Instr instr) {
507 return GetOpcodeField(instr) == BNE;
511 bool Assembler::IsJump(Instr instr) {
512 uint32_t opcode = GetOpcodeField(instr);
513 uint32_t rt_field = GetRtField(instr);
514 uint32_t rd_field = GetRdField(instr);
515 uint32_t function_field = GetFunctionField(instr);
516 // Checks if the instruction is a jump.
517 return opcode == J || opcode == JAL ||
518 (opcode == SPECIAL && rt_field == 0 &&
519 ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
523 bool Assembler::IsJ(Instr instr) {
524 uint32_t opcode = GetOpcodeField(instr);
525 // Checks if the instruction is a jump.
530 bool Assembler::IsJal(Instr instr) {
531 return GetOpcodeField(instr) == JAL;
535 bool Assembler::IsJr(Instr instr) {
536 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
540 bool Assembler::IsJalr(Instr instr) {
541 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR;
545 bool Assembler::IsLui(Instr instr) {
546 uint32_t opcode = GetOpcodeField(instr);
547 // Checks if the instruction is a load upper immediate.
548 return opcode == LUI;
552 bool Assembler::IsOri(Instr instr) {
553 uint32_t opcode = GetOpcodeField(instr);
554 // Checks if the instruction is a load upper immediate.
555 return opcode == ORI;
559 bool Assembler::IsNop(Instr instr, unsigned int type) {
560 // See Assembler::nop(type).
562 uint32_t opcode = GetOpcodeField(instr);
563 uint32_t function = GetFunctionField(instr);
564 uint32_t rt = GetRt(instr);
565 uint32_t rd = GetRd(instr);
566 uint32_t sa = GetSa(instr);
568 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
569 // When marking non-zero type, use sll(zero_reg, at, type)
570 // to avoid use of mips ssnop and ehb special encodings
571 // of the sll instruction.
573 Register nop_rt_reg = (type == 0) ? zero_reg : at;
574 bool ret = (opcode == SPECIAL && function == SLL &&
575 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
576 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
583 int32_t Assembler::GetBranchOffset(Instr instr) {
584 DCHECK(IsBranch(instr));
585 return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
589 bool Assembler::IsLw(Instr instr) {
590 return ((instr & kOpcodeMask) == LW);
594 int16_t Assembler::GetLwOffset(Instr instr) {
596 return ((instr & kImm16Mask));
600 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
603 // We actually create a new lw instruction based on the original one.
604 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
605 | (offset & kImm16Mask);
611 bool Assembler::IsSw(Instr instr) {
612 return ((instr & kOpcodeMask) == SW);
616 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
618 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
622 bool Assembler::IsAddImmediate(Instr instr) {
623 return ((instr & kOpcodeMask) == ADDIU || (instr & kOpcodeMask) == DADDIU);
627 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
628 DCHECK(IsAddImmediate(instr));
629 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
633 bool Assembler::IsAndImmediate(Instr instr) {
634 return GetOpcodeField(instr) == ANDI;
638 int64_t Assembler::target_at(int64_t pos, bool is_internal) {
640 int64_t* p = reinterpret_cast<int64_t*>(buffer_ + pos);
641 int64_t address = *p;
642 if (address == kEndOfJumpChain) {
645 int64_t instr_address = reinterpret_cast<int64_t>(p);
646 int64_t delta = instr_address - address;
651 Instr instr = instr_at(pos);
652 if ((instr & ~kImm16Mask) == 0) {
653 // Emitted label constant, not part of a branch.
657 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
658 return (imm18 + pos);
661 // Check we have a branch or jump instruction.
662 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
663 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
664 // the compiler uses arithmetic shifts for signed integers.
665 if (IsBranch(instr)) {
666 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
667 if (imm18 == kEndOfChain) {
668 // EndOfChain sentinel is returned directly, not relative to pc or pos.
671 return pos + kBranchPCOffset + imm18;
673 } else if (IsLui(instr)) {
674 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
675 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
676 Instr instr_ori2 = instr_at(pos + 3 * Assembler::kInstrSize);
677 DCHECK(IsOri(instr_ori));
678 DCHECK(IsOri(instr_ori2));
680 // TODO(plind) create named constants for shift values.
681 int64_t imm = static_cast<int64_t>(instr_lui & kImm16Mask) << 48;
682 imm |= static_cast<int64_t>(instr_ori & kImm16Mask) << 32;
683 imm |= static_cast<int64_t>(instr_ori2 & kImm16Mask) << 16;
684 // Sign extend address;
687 if (imm == kEndOfJumpChain) {
688 // EndOfChain sentinel is returned directly, not relative to pc or pos.
691 uint64_t instr_address = reinterpret_cast<int64_t>(buffer_ + pos);
692 int64_t delta = instr_address - imm;
697 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
698 if (imm28 == kEndOfJumpChain) {
699 // EndOfChain sentinel is returned directly, not relative to pc or pos.
702 uint64_t instr_address = reinterpret_cast<int64_t>(buffer_ + pos);
703 instr_address &= kImm28Mask;
704 int64_t delta = instr_address - imm28;
712 void Assembler::target_at_put(int64_t pos, int64_t target_pos,
715 uint64_t imm = reinterpret_cast<uint64_t>(buffer_) + target_pos;
716 *reinterpret_cast<uint64_t*>(buffer_ + pos) = imm;
719 Instr instr = instr_at(pos);
720 if ((instr & ~kImm16Mask) == 0) {
721 DCHECK(target_pos == kEndOfChain || target_pos >= 0);
722 // Emitted label constant, not part of a branch.
723 // Make label relative to Code* of generated Code object.
724 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
728 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
729 if (IsBranch(instr)) {
730 int32_t imm18 = target_pos - (pos + kBranchPCOffset);
731 DCHECK((imm18 & 3) == 0);
733 instr &= ~kImm16Mask;
734 int32_t imm16 = imm18 >> 2;
735 DCHECK(is_int16(imm16));
737 instr_at_put(pos, instr | (imm16 & kImm16Mask));
738 } else if (IsLui(instr)) {
739 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
740 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
741 Instr instr_ori2 = instr_at(pos + 3 * Assembler::kInstrSize);
742 DCHECK(IsOri(instr_ori));
743 DCHECK(IsOri(instr_ori2));
745 uint64_t imm = reinterpret_cast<uint64_t>(buffer_) + target_pos;
746 DCHECK((imm & 3) == 0);
748 instr_lui &= ~kImm16Mask;
749 instr_ori &= ~kImm16Mask;
750 instr_ori2 &= ~kImm16Mask;
752 instr_at_put(pos + 0 * Assembler::kInstrSize,
753 instr_lui | ((imm >> 32) & kImm16Mask));
754 instr_at_put(pos + 1 * Assembler::kInstrSize,
755 instr_ori | ((imm >> 16) & kImm16Mask));
756 instr_at_put(pos + 3 * Assembler::kInstrSize,
757 instr_ori2 | (imm & kImm16Mask));
759 uint64_t imm28 = reinterpret_cast<uint64_t>(buffer_) + target_pos;
761 DCHECK((imm28 & 3) == 0);
763 instr &= ~kImm26Mask;
764 uint32_t imm26 = imm28 >> 2;
765 DCHECK(is_uint26(imm26));
767 instr_at_put(pos, instr | (imm26 & kImm26Mask));
772 void Assembler::print(Label* L) {
773 if (L->is_unused()) {
774 PrintF("unused label\n");
775 } else if (L->is_bound()) {
776 PrintF("bound label to %d\n", L->pos());
777 } else if (L->is_linked()) {
779 PrintF("unbound label");
780 while (l.is_linked()) {
781 PrintF("@ %d ", l.pos());
782 Instr instr = instr_at(l.pos());
783 if ((instr & ~kImm16Mask) == 0) {
786 PrintF("%d\n", instr);
788 next(&l, internal_reference_positions_.find(l.pos()) !=
789 internal_reference_positions_.end());
792 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
797 void Assembler::bind_to(Label* L, int pos) {
798 DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position.
799 int32_t trampoline_pos = kInvalidSlotPos;
800 bool is_internal = false;
801 if (L->is_linked() && !trampoline_emitted_) {
802 unbound_labels_count_--;
803 next_buffer_check_ += kTrampolineSlotsSize;
806 while (L->is_linked()) {
807 int32_t fixup_pos = L->pos();
808 int32_t dist = pos - fixup_pos;
809 is_internal = internal_reference_positions_.find(fixup_pos) !=
810 internal_reference_positions_.end();
811 next(L, is_internal); // Call next before overwriting link with target at
813 Instr instr = instr_at(fixup_pos);
815 target_at_put(fixup_pos, pos, is_internal);
816 } else if (IsBranch(instr)) {
817 if (dist > kMaxBranchOffset) {
818 if (trampoline_pos == kInvalidSlotPos) {
819 trampoline_pos = get_trampoline_entry(fixup_pos);
820 CHECK(trampoline_pos != kInvalidSlotPos);
822 DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset);
823 target_at_put(fixup_pos, trampoline_pos, false);
824 fixup_pos = trampoline_pos;
825 dist = pos - fixup_pos;
827 target_at_put(fixup_pos, pos, false);
829 DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));
830 target_at_put(fixup_pos, pos, false);
835 // Keep track of the last bound label so we don't eliminate any instructions
836 // before a bound label.
837 if (pos > last_bound_pos_)
838 last_bound_pos_ = pos;
842 void Assembler::bind(Label* L) {
843 DCHECK(!L->is_bound()); // Label can only be bound once.
844 bind_to(L, pc_offset());
848 void Assembler::next(Label* L, bool is_internal) {
849 DCHECK(L->is_linked());
850 int link = target_at(L->pos(), is_internal);
851 if (link == kEndOfChain) {
860 bool Assembler::is_near(Label* L) {
862 return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize);
868 // We have to use a temporary register for things that can be relocated even
869 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
870 // space. There is no guarantee that the relocated location can be similarly
872 bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
873 return !RelocInfo::IsNone(rmode);
876 void Assembler::GenInstrRegister(Opcode opcode,
881 SecondaryField func) {
882 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
883 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
884 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
889 void Assembler::GenInstrRegister(Opcode opcode,
894 SecondaryField func) {
895 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
896 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
897 | (msb << kRdShift) | (lsb << kSaShift) | func;
902 void Assembler::GenInstrRegister(Opcode opcode,
907 SecondaryField func) {
908 DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
909 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
910 | (fd.code() << kFdShift) | func;
915 void Assembler::GenInstrRegister(Opcode opcode,
920 SecondaryField func) {
921 DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
922 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)
923 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
928 void Assembler::GenInstrRegister(Opcode opcode,
933 SecondaryField func) {
934 DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
935 Instr instr = opcode | fmt | (rt.code() << kRtShift)
936 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
941 void Assembler::GenInstrRegister(Opcode opcode,
944 FPUControlRegister fs,
945 SecondaryField func) {
946 DCHECK(fs.is_valid() && rt.is_valid());
948 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
953 // Instructions with immediate value.
954 // Registers are in the order of the instruction encoding, from left to right.
955 void Assembler::GenInstrImmediate(Opcode opcode,
959 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
960 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
966 void Assembler::GenInstrImmediate(Opcode opcode,
970 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
971 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
976 void Assembler::GenInstrImmediate(Opcode opcode,
980 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
981 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
987 void Assembler::GenInstrJump(Opcode opcode,
989 BlockTrampolinePoolScope block_trampoline_pool(this);
990 DCHECK(is_uint26(address));
991 Instr instr = opcode | address;
993 BlockTrampolinePoolFor(1); // For associated delay slot.
997 // Returns the next free trampoline entry.
998 int32_t Assembler::get_trampoline_entry(int32_t pos) {
999 int32_t trampoline_entry = kInvalidSlotPos;
1000 if (!internal_trampoline_exception_) {
1001 if (trampoline_.start() > pos) {
1002 trampoline_entry = trampoline_.take_slot();
1005 if (kInvalidSlotPos == trampoline_entry) {
1006 internal_trampoline_exception_ = true;
1009 return trampoline_entry;
1013 uint64_t Assembler::jump_address(Label* L) {
1015 if (L->is_bound()) {
1016 target_pos = L->pos();
1018 if (L->is_linked()) {
1019 target_pos = L->pos(); // L's link.
1020 L->link_to(pc_offset());
1022 L->link_to(pc_offset());
1023 return kEndOfJumpChain;
1027 uint64_t imm = reinterpret_cast<uint64_t>(buffer_) + target_pos;
1028 DCHECK((imm & 3) == 0);
1034 int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
1036 if (L->is_bound()) {
1037 target_pos = L->pos();
1039 if (L->is_linked()) {
1040 target_pos = L->pos();
1041 L->link_to(pc_offset());
1043 L->link_to(pc_offset());
1044 if (!trampoline_emitted_) {
1045 unbound_labels_count_++;
1046 next_buffer_check_ -= kTrampolineSlotsSize;
1052 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);
1053 DCHECK((offset & 3) == 0);
1054 DCHECK(is_int16(offset >> 2));
1060 int32_t Assembler::branch_offset_compact(Label* L,
1061 bool jump_elimination_allowed) {
1063 if (L->is_bound()) {
1064 target_pos = L->pos();
1066 if (L->is_linked()) {
1067 target_pos = L->pos();
1068 L->link_to(pc_offset());
1070 L->link_to(pc_offset());
1071 if (!trampoline_emitted_) {
1072 unbound_labels_count_++;
1073 next_buffer_check_ -= kTrampolineSlotsSize;
1079 int32_t offset = target_pos - pc_offset();
1080 DCHECK((offset & 3) == 0);
1081 DCHECK(is_int16(offset >> 2));
1087 int32_t Assembler::branch_offset21(Label* L, bool jump_elimination_allowed) {
1089 if (L->is_bound()) {
1090 target_pos = L->pos();
1092 if (L->is_linked()) {
1093 target_pos = L->pos();
1094 L->link_to(pc_offset());
1096 L->link_to(pc_offset());
1097 if (!trampoline_emitted_) {
1098 unbound_labels_count_++;
1099 next_buffer_check_ -= kTrampolineSlotsSize;
1105 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);
1106 DCHECK((offset & 3) == 0);
1107 DCHECK(((offset >> 2) & 0xFFE00000) == 0); // Offset is 21bit width.
1113 int32_t Assembler::branch_offset21_compact(Label* L,
1114 bool jump_elimination_allowed) {
1116 if (L->is_bound()) {
1117 target_pos = L->pos();
1119 if (L->is_linked()) {
1120 target_pos = L->pos();
1121 L->link_to(pc_offset());
1123 L->link_to(pc_offset());
1124 if (!trampoline_emitted_) {
1125 unbound_labels_count_++;
1126 next_buffer_check_ -= kTrampolineSlotsSize;
1132 int32_t offset = target_pos - pc_offset();
1133 DCHECK((offset & 3) == 0);
1134 DCHECK(((offset >> 2) & 0xFFE00000) == 0); // Offset is 21bit width.
1140 void Assembler::label_at_put(Label* L, int at_offset) {
1142 if (L->is_bound()) {
1143 target_pos = L->pos();
1144 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
1146 if (L->is_linked()) {
1147 target_pos = L->pos(); // L's link.
1148 int32_t imm18 = target_pos - at_offset;
1149 DCHECK((imm18 & 3) == 0);
1150 int32_t imm16 = imm18 >> 2;
1151 DCHECK(is_int16(imm16));
1152 instr_at_put(at_offset, (imm16 & kImm16Mask));
1154 target_pos = kEndOfChain;
1155 instr_at_put(at_offset, 0);
1156 if (!trampoline_emitted_) {
1157 unbound_labels_count_++;
1158 next_buffer_check_ -= kTrampolineSlotsSize;
1161 L->link_to(at_offset);
1166 //------- Branch and jump instructions --------
1168 void Assembler::b(int16_t offset) {
1169 beq(zero_reg, zero_reg, offset);
1173 void Assembler::bal(int16_t offset) {
1174 positions_recorder()->WriteRecordedPositions();
1175 bgezal(zero_reg, offset);
1179 void Assembler::beq(Register rs, Register rt, int16_t offset) {
1180 BlockTrampolinePoolScope block_trampoline_pool(this);
1181 GenInstrImmediate(BEQ, rs, rt, offset);
1182 BlockTrampolinePoolFor(1); // For associated delay slot.
1186 void Assembler::bgez(Register rs, int16_t offset) {
1187 BlockTrampolinePoolScope block_trampoline_pool(this);
1188 GenInstrImmediate(REGIMM, rs, BGEZ, offset);
1189 BlockTrampolinePoolFor(1); // For associated delay slot.
1193 void Assembler::bgezc(Register rt, int16_t offset) {
1194 DCHECK(kArchVariant == kMips64r6);
1195 DCHECK(!(rt.is(zero_reg)));
1196 GenInstrImmediate(BLEZL, rt, rt, offset);
1200 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
1201 DCHECK(kArchVariant == kMips64r6);
1202 DCHECK(!(rs.is(zero_reg)));
1203 DCHECK(!(rt.is(zero_reg)));
1204 DCHECK(rs.code() != rt.code());
1205 GenInstrImmediate(BLEZ, rs, rt, offset);
1209 void Assembler::bgec(Register rs, Register rt, int16_t offset) {
1210 DCHECK(kArchVariant == kMips64r6);
1211 DCHECK(!(rs.is(zero_reg)));
1212 DCHECK(!(rt.is(zero_reg)));
1213 DCHECK(rs.code() != rt.code());
1214 GenInstrImmediate(BLEZL, rs, rt, offset);
1218 void Assembler::bgezal(Register rs, int16_t offset) {
1219 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
1220 BlockTrampolinePoolScope block_trampoline_pool(this);
1221 positions_recorder()->WriteRecordedPositions();
1222 GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
1223 BlockTrampolinePoolFor(1); // For associated delay slot.
1227 void Assembler::bgtz(Register rs, int16_t offset) {
1228 BlockTrampolinePoolScope block_trampoline_pool(this);
1229 GenInstrImmediate(BGTZ, rs, zero_reg, offset);
1230 BlockTrampolinePoolFor(1); // For associated delay slot.
1234 void Assembler::bgtzc(Register rt, int16_t offset) {
1235 DCHECK(kArchVariant == kMips64r6);
1236 DCHECK(!(rt.is(zero_reg)));
1237 GenInstrImmediate(BGTZL, zero_reg, rt, offset);
1241 void Assembler::blez(Register rs, int16_t offset) {
1242 BlockTrampolinePoolScope block_trampoline_pool(this);
1243 GenInstrImmediate(BLEZ, rs, zero_reg, offset);
1244 BlockTrampolinePoolFor(1); // For associated delay slot.
1248 void Assembler::blezc(Register rt, int16_t offset) {
1249 DCHECK(kArchVariant == kMips64r6);
1250 DCHECK(!(rt.is(zero_reg)));
1251 GenInstrImmediate(BLEZL, zero_reg, rt, offset);
1255 void Assembler::bltzc(Register rt, int16_t offset) {
1256 DCHECK(kArchVariant == kMips64r6);
1257 DCHECK(!(rt.is(zero_reg)));
1258 GenInstrImmediate(BGTZL, rt, rt, offset);
1262 void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
1263 DCHECK(kArchVariant == kMips64r6);
1264 DCHECK(!(rs.is(zero_reg)));
1265 DCHECK(!(rt.is(zero_reg)));
1266 DCHECK(rs.code() != rt.code());
1267 GenInstrImmediate(BGTZ, rs, rt, offset);
1271 void Assembler::bltc(Register rs, Register rt, int16_t offset) {
1272 DCHECK(kArchVariant == kMips64r6);
1273 DCHECK(!(rs.is(zero_reg)));
1274 DCHECK(!(rt.is(zero_reg)));
1275 DCHECK(rs.code() != rt.code());
1276 GenInstrImmediate(BGTZL, rs, rt, offset);
1280 void Assembler::bltz(Register rs, int16_t offset) {
1281 BlockTrampolinePoolScope block_trampoline_pool(this);
1282 GenInstrImmediate(REGIMM, rs, BLTZ, offset);
1283 BlockTrampolinePoolFor(1); // For associated delay slot.
1287 void Assembler::bltzal(Register rs, int16_t offset) {
1288 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
1289 BlockTrampolinePoolScope block_trampoline_pool(this);
1290 positions_recorder()->WriteRecordedPositions();
1291 GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
1292 BlockTrampolinePoolFor(1); // For associated delay slot.
1296 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1297 BlockTrampolinePoolScope block_trampoline_pool(this);
1298 GenInstrImmediate(BNE, rs, rt, offset);
1299 BlockTrampolinePoolFor(1); // For associated delay slot.
1303 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
1304 DCHECK(kArchVariant == kMips64r6);
1305 DCHECK(!(rs.is(zero_reg)));
1306 DCHECK(rs.code() >= rt.code());
1307 GenInstrImmediate(ADDI, rs, rt, offset);
1311 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
1312 DCHECK(kArchVariant == kMips64r6);
1313 DCHECK(!(rs.is(zero_reg)));
1314 DCHECK(rs.code() >= rt.code());
1315 GenInstrImmediate(DADDI, rs, rt, offset);
1319 void Assembler::blezalc(Register rt, int16_t offset) {
1320 DCHECK(kArchVariant == kMips64r6);
1321 DCHECK(!(rt.is(zero_reg)));
1322 GenInstrImmediate(BLEZ, zero_reg, rt, offset);
1326 void Assembler::bgezalc(Register rt, int16_t offset) {
1327 DCHECK(kArchVariant == kMips64r6);
1328 DCHECK(!(rt.is(zero_reg)));
1329 GenInstrImmediate(BLEZ, rt, rt, offset);
1333 void Assembler::bgezall(Register rs, int16_t offset) {
1334 DCHECK(kArchVariant == kMips64r6);
1335 DCHECK(!(rs.is(zero_reg)));
1336 GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
1340 void Assembler::bltzalc(Register rt, int16_t offset) {
1341 DCHECK(kArchVariant == kMips64r6);
1342 DCHECK(!(rt.is(zero_reg)));
1343 GenInstrImmediate(BGTZ, rt, rt, offset);
1347 void Assembler::bgtzalc(Register rt, int16_t offset) {
1348 DCHECK(kArchVariant == kMips64r6);
1349 DCHECK(!(rt.is(zero_reg)));
1350 GenInstrImmediate(BGTZ, zero_reg, rt, offset);
1354 void Assembler::beqzalc(Register rt, int16_t offset) {
1355 DCHECK(kArchVariant == kMips64r6);
1356 DCHECK(!(rt.is(zero_reg)));
1357 GenInstrImmediate(ADDI, zero_reg, rt, offset);
1361 void Assembler::bnezalc(Register rt, int16_t offset) {
1362 DCHECK(kArchVariant == kMips64r6);
1363 DCHECK(!(rt.is(zero_reg)));
1364 GenInstrImmediate(DADDI, zero_reg, rt, offset);
1368 void Assembler::beqc(Register rs, Register rt, int16_t offset) {
1369 DCHECK(kArchVariant == kMips64r6);
1370 DCHECK(rs.code() < rt.code());
1371 GenInstrImmediate(ADDI, rs, rt, offset);
1375 void Assembler::beqzc(Register rs, int32_t offset) {
1376 DCHECK(kArchVariant == kMips64r6);
1377 DCHECK(!(rs.is(zero_reg)));
1378 Instr instr = BEQZC | (rs.code() << kRsShift) | offset;
1383 void Assembler::bnec(Register rs, Register rt, int16_t offset) {
1384 DCHECK(kArchVariant == kMips64r6);
1385 DCHECK(rs.code() < rt.code());
1386 GenInstrImmediate(DADDI, rs, rt, offset);
1390 void Assembler::bnezc(Register rs, int32_t offset) {
1391 DCHECK(kArchVariant == kMips64r6);
1392 DCHECK(!(rs.is(zero_reg)));
1393 Instr instr = BNEZC | (rs.code() << kRsShift) | offset;
1398 void Assembler::j(int64_t target) {
1400 // Get pc of delay slot.
1401 uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
1402 bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
1403 (kImm26Bits + kImmFieldShift)) == 0;
1404 DCHECK(in_range && ((target & 3) == 0));
1406 GenInstrJump(J, target >> 2);
1410 void Assembler::jr(Register rs) {
1411 if (kArchVariant != kMips64r6) {
1412 BlockTrampolinePoolScope block_trampoline_pool(this);
1414 positions_recorder()->WriteRecordedPositions();
1416 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
1417 BlockTrampolinePoolFor(1); // For associated delay slot.
1424 void Assembler::jal(int64_t target) {
1426 // Get pc of delay slot.
1427 uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
1428 bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
1429 (kImm26Bits + kImmFieldShift)) == 0;
1430 DCHECK(in_range && ((target & 3) == 0));
1432 positions_recorder()->WriteRecordedPositions();
1433 GenInstrJump(JAL, target >> 2);
1437 void Assembler::jalr(Register rs, Register rd) {
1438 BlockTrampolinePoolScope block_trampoline_pool(this);
1439 positions_recorder()->WriteRecordedPositions();
1440 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1441 BlockTrampolinePoolFor(1); // For associated delay slot.
1445 void Assembler::j_or_jr(int64_t target, Register rs) {
1446 // Get pc of delay slot.
1447 uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
1448 bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
1449 (kImm26Bits + kImmFieldShift)) == 0;
1458 void Assembler::jal_or_jalr(int64_t target, Register rs) {
1459 // Get pc of delay slot.
1460 uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
1461 bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
1462 (kImm26Bits+kImmFieldShift)) == 0;
1471 // -------Data-processing-instructions---------
1475 void Assembler::addu(Register rd, Register rs, Register rt) {
1476 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1480 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1481 GenInstrImmediate(ADDIU, rs, rd, j);
1485 void Assembler::subu(Register rd, Register rs, Register rt) {
1486 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1490 void Assembler::mul(Register rd, Register rs, Register rt) {
1491 if (kArchVariant == kMips64r6) {
1492 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
1494 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1499 void Assembler::muh(Register rd, Register rs, Register rt) {
1500 DCHECK(kArchVariant == kMips64r6);
1501 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
1505 void Assembler::mulu(Register rd, Register rs, Register rt) {
1506 DCHECK(kArchVariant == kMips64r6);
1507 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
1511 void Assembler::muhu(Register rd, Register rs, Register rt) {
1512 DCHECK(kArchVariant == kMips64r6);
1513 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
1517 void Assembler::dmul(Register rd, Register rs, Register rt) {
1518 DCHECK(kArchVariant == kMips64r6);
1519 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH);
1523 void Assembler::dmuh(Register rd, Register rs, Register rt) {
1524 DCHECK(kArchVariant == kMips64r6);
1525 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH);
1529 void Assembler::dmulu(Register rd, Register rs, Register rt) {
1530 DCHECK(kArchVariant == kMips64r6);
1531 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U);
1535 void Assembler::dmuhu(Register rd, Register rs, Register rt) {
1536 DCHECK(kArchVariant == kMips64r6);
1537 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U);
1541 void Assembler::mult(Register rs, Register rt) {
1542 DCHECK(kArchVariant != kMips64r6);
1543 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1547 void Assembler::multu(Register rs, Register rt) {
1548 DCHECK(kArchVariant != kMips64r6);
1549 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1553 void Assembler::daddiu(Register rd, Register rs, int32_t j) {
1554 GenInstrImmediate(DADDIU, rs, rd, j);
1558 void Assembler::div(Register rs, Register rt) {
1559 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1563 void Assembler::div(Register rd, Register rs, Register rt) {
1564 DCHECK(kArchVariant == kMips64r6);
1565 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
1569 void Assembler::mod(Register rd, Register rs, Register rt) {
1570 DCHECK(kArchVariant == kMips64r6);
1571 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
1575 void Assembler::divu(Register rs, Register rt) {
1576 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1580 void Assembler::divu(Register rd, Register rs, Register rt) {
1581 DCHECK(kArchVariant == kMips64r6);
1582 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
1586 void Assembler::modu(Register rd, Register rs, Register rt) {
1587 DCHECK(kArchVariant == kMips64r6);
1588 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
1592 void Assembler::daddu(Register rd, Register rs, Register rt) {
1593 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU);
1597 void Assembler::dsubu(Register rd, Register rs, Register rt) {
1598 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU);
1602 void Assembler::dmult(Register rs, Register rt) {
1603 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT);
1607 void Assembler::dmultu(Register rs, Register rt) {
1608 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU);
1612 void Assembler::ddiv(Register rs, Register rt) {
1613 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV);
1617 void Assembler::ddiv(Register rd, Register rs, Register rt) {
1618 DCHECK(kArchVariant == kMips64r6);
1619 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD);
1623 void Assembler::dmod(Register rd, Register rs, Register rt) {
1624 DCHECK(kArchVariant == kMips64r6);
1625 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD);
1629 void Assembler::ddivu(Register rs, Register rt) {
1630 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU);
1634 void Assembler::ddivu(Register rd, Register rs, Register rt) {
1635 DCHECK(kArchVariant == kMips64r6);
1636 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U);
1640 void Assembler::dmodu(Register rd, Register rs, Register rt) {
1641 DCHECK(kArchVariant == kMips64r6);
1642 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U);
1648 void Assembler::and_(Register rd, Register rs, Register rt) {
1649 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1653 void Assembler::andi(Register rt, Register rs, int32_t j) {
1654 DCHECK(is_uint16(j));
1655 GenInstrImmediate(ANDI, rs, rt, j);
1659 void Assembler::or_(Register rd, Register rs, Register rt) {
1660 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1664 void Assembler::ori(Register rt, Register rs, int32_t j) {
1665 DCHECK(is_uint16(j));
1666 GenInstrImmediate(ORI, rs, rt, j);
1670 void Assembler::xor_(Register rd, Register rs, Register rt) {
1671 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1675 void Assembler::xori(Register rt, Register rs, int32_t j) {
1676 DCHECK(is_uint16(j));
1677 GenInstrImmediate(XORI, rs, rt, j);
1681 void Assembler::nor(Register rd, Register rs, Register rt) {
1682 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1687 void Assembler::sll(Register rd,
1690 bool coming_from_nop) {
1691 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
1692 // generated using the sll instruction. They must be generated using
1693 // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
1695 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1696 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1700 void Assembler::sllv(Register rd, Register rt, Register rs) {
1701 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1705 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1706 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1710 void Assembler::srlv(Register rd, Register rt, Register rs) {
1711 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1715 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1716 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1720 void Assembler::srav(Register rd, Register rt, Register rs) {
1721 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1725 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1726 // Should be called via MacroAssembler::Ror.
1727 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1728 DCHECK(kArchVariant == kMips64r2);
1729 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
1730 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1735 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1736 // Should be called via MacroAssembler::Ror.
1737 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1738 DCHECK(kArchVariant == kMips64r2);
1739 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1740 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1745 void Assembler::dsll(Register rd, Register rt, uint16_t sa) {
1746 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL);
1750 void Assembler::dsllv(Register rd, Register rt, Register rs) {
1751 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV);
1755 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) {
1756 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL);
1760 void Assembler::dsrlv(Register rd, Register rt, Register rs) {
1761 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV);
1765 void Assembler::drotr(Register rd, Register rt, uint16_t sa) {
1766 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1767 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
1768 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL;
1773 void Assembler::drotrv(Register rd, Register rt, Register rs) {
1774 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1775 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1776 | (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV;
1781 void Assembler::dsra(Register rd, Register rt, uint16_t sa) {
1782 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA);
1786 void Assembler::dsrav(Register rd, Register rt, Register rs) {
1787 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV);
1791 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) {
1792 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL32);
1796 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) {
1797 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL32);
1801 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) {
1802 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA32);
1806 // ------------Memory-instructions-------------
1808 // Helper for base-reg + offset, when offset is larger than int16.
1809 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
1810 DCHECK(!src.rm().is(at));
1811 DCHECK(is_int32(src.offset_));
1812 daddiu(at, zero_reg, (src.offset_ >> kLuiShift) & kImm16Mask);
1813 dsll(at, at, kLuiShift);
1814 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
1815 daddu(at, at, src.rm()); // Add base register.
1819 void Assembler::lb(Register rd, const MemOperand& rs) {
1820 if (is_int16(rs.offset_)) {
1821 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1822 } else { // Offset > 16 bits, use multiple instructions to load.
1823 LoadRegPlusOffsetToAt(rs);
1824 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0));
1829 void Assembler::lbu(Register rd, const MemOperand& rs) {
1830 if (is_int16(rs.offset_)) {
1831 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1832 } else { // Offset > 16 bits, use multiple instructions to load.
1833 LoadRegPlusOffsetToAt(rs);
1834 GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0));
1839 void Assembler::lh(Register rd, const MemOperand& rs) {
1840 if (is_int16(rs.offset_)) {
1841 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1842 } else { // Offset > 16 bits, use multiple instructions to load.
1843 LoadRegPlusOffsetToAt(rs);
1844 GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0));
1849 void Assembler::lhu(Register rd, const MemOperand& rs) {
1850 if (is_int16(rs.offset_)) {
1851 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1852 } else { // Offset > 16 bits, use multiple instructions to load.
1853 LoadRegPlusOffsetToAt(rs);
1854 GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0));
1859 void Assembler::lw(Register rd, const MemOperand& rs) {
1860 if (is_int16(rs.offset_)) {
1861 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1862 } else { // Offset > 16 bits, use multiple instructions to load.
1863 LoadRegPlusOffsetToAt(rs);
1864 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0));
1869 void Assembler::lwu(Register rd, const MemOperand& rs) {
1870 if (is_int16(rs.offset_)) {
1871 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_);
1872 } else { // Offset > 16 bits, use multiple instructions to load.
1873 LoadRegPlusOffsetToAt(rs);
1874 GenInstrImmediate(LWU, at, rd, 0); // Equiv to lwu(rd, MemOperand(at, 0));
1879 void Assembler::lwl(Register rd, const MemOperand& rs) {
1880 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
1884 void Assembler::lwr(Register rd, const MemOperand& rs) {
1885 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
1889 void Assembler::sb(Register rd, const MemOperand& rs) {
1890 if (is_int16(rs.offset_)) {
1891 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
1892 } else { // Offset > 16 bits, use multiple instructions to store.
1893 LoadRegPlusOffsetToAt(rs);
1894 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0));
1899 void Assembler::sh(Register rd, const MemOperand& rs) {
1900 if (is_int16(rs.offset_)) {
1901 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
1902 } else { // Offset > 16 bits, use multiple instructions to store.
1903 LoadRegPlusOffsetToAt(rs);
1904 GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0));
1909 void Assembler::sw(Register rd, const MemOperand& rs) {
1910 if (is_int16(rs.offset_)) {
1911 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
1912 } else { // Offset > 16 bits, use multiple instructions to store.
1913 LoadRegPlusOffsetToAt(rs);
1914 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0));
1919 void Assembler::swl(Register rd, const MemOperand& rs) {
1920 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
1924 void Assembler::swr(Register rd, const MemOperand& rs) {
1925 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
1929 void Assembler::lui(Register rd, int32_t j) {
1930 DCHECK(is_uint16(j));
1931 GenInstrImmediate(LUI, zero_reg, rd, j);
1935 void Assembler::aui(Register rs, Register rt, int32_t j) {
1936 // This instruction uses same opcode as 'lui'. The difference in encoding is
1937 // 'lui' has zero reg. for rs field.
1938 DCHECK(is_uint16(j));
1939 GenInstrImmediate(LUI, rs, rt, j);
1943 void Assembler::daui(Register rs, Register rt, int32_t j) {
1944 DCHECK(is_uint16(j));
1945 GenInstrImmediate(DAUI, rs, rt, j);
1949 void Assembler::dahi(Register rs, int32_t j) {
1950 DCHECK(is_uint16(j));
1951 GenInstrImmediate(REGIMM, rs, DAHI, j);
1955 void Assembler::dati(Register rs, int32_t j) {
1956 DCHECK(is_uint16(j));
1957 GenInstrImmediate(REGIMM, rs, DATI, j);
1961 void Assembler::ldl(Register rd, const MemOperand& rs) {
1962 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_);
1966 void Assembler::ldr(Register rd, const MemOperand& rs) {
1967 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_);
1971 void Assembler::sdl(Register rd, const MemOperand& rs) {
1972 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_);
1976 void Assembler::sdr(Register rd, const MemOperand& rs) {
1977 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_);
1981 void Assembler::ld(Register rd, const MemOperand& rs) {
1982 if (is_int16(rs.offset_)) {
1983 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_);
1984 } else { // Offset > 16 bits, use multiple instructions to load.
1985 LoadRegPlusOffsetToAt(rs);
1986 GenInstrImmediate(LD, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0));
1991 void Assembler::sd(Register rd, const MemOperand& rs) {
1992 if (is_int16(rs.offset_)) {
1993 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_);
1994 } else { // Offset > 16 bits, use multiple instructions to store.
1995 LoadRegPlusOffsetToAt(rs);
1996 GenInstrImmediate(SD, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0));
2001 // -------------Misc-instructions--------------
2003 // Break / Trap instructions.
2004 void Assembler::break_(uint32_t code, bool break_as_stop) {
2005 DCHECK((code & ~0xfffff) == 0);
2006 // We need to invalidate breaks that could be stops as well because the
2007 // simulator expects a char pointer after the stop instruction.
2008 // See constants-mips.h for explanation.
2009 DCHECK((break_as_stop &&
2010 code <= kMaxStopCode &&
2011 code > kMaxWatchpointCode) ||
2013 (code > kMaxStopCode ||
2014 code <= kMaxWatchpointCode)));
2015 Instr break_instr = SPECIAL | BREAK | (code << 6);
2020 void Assembler::stop(const char* msg, uint32_t code) {
2021 DCHECK(code > kMaxWatchpointCode);
2022 DCHECK(code <= kMaxStopCode);
2023 #if defined(V8_HOST_ARCH_MIPS) || defined(V8_HOST_ARCH_MIPS64)
2025 #else // V8_HOST_ARCH_MIPS
2026 BlockTrampolinePoolFor(3);
2027 // The Simulator will handle the stop instruction and get the message address.
2028 // On MIPS stop() is just a special kind of break_().
2030 emit(reinterpret_cast<uint64_t>(msg));
2035 void Assembler::tge(Register rs, Register rt, uint16_t code) {
2036 DCHECK(is_uint10(code));
2037 Instr instr = SPECIAL | TGE | rs.code() << kRsShift
2038 | rt.code() << kRtShift | code << 6;
2043 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
2044 DCHECK(is_uint10(code));
2045 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
2046 | rt.code() << kRtShift | code << 6;
2051 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
2052 DCHECK(is_uint10(code));
2054 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2059 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
2060 DCHECK(is_uint10(code));
2062 SPECIAL | TLTU | rs.code() << kRsShift
2063 | rt.code() << kRtShift | code << 6;
2068 void Assembler::teq(Register rs, Register rt, uint16_t code) {
2069 DCHECK(is_uint10(code));
2071 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2076 void Assembler::tne(Register rs, Register rt, uint16_t code) {
2077 DCHECK(is_uint10(code));
2079 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2084 // Move from HI/LO register.
2086 void Assembler::mfhi(Register rd) {
2087 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
2091 void Assembler::mflo(Register rd) {
2092 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
2096 // Set on less than instructions.
2097 void Assembler::slt(Register rd, Register rs, Register rt) {
2098 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
2102 void Assembler::sltu(Register rd, Register rs, Register rt) {
2103 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
2107 void Assembler::slti(Register rt, Register rs, int32_t j) {
2108 GenInstrImmediate(SLTI, rs, rt, j);
2112 void Assembler::sltiu(Register rt, Register rs, int32_t j) {
2113 GenInstrImmediate(SLTIU, rs, rt, j);
2117 // Conditional move.
2118 void Assembler::movz(Register rd, Register rs, Register rt) {
2119 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
2123 void Assembler::movn(Register rd, Register rs, Register rt) {
2124 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
2128 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
2130 rt.code_ = (cc & 0x0007) << 2 | 1;
2131 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2135 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
2137 rt.code_ = (cc & 0x0007) << 2 | 0;
2138 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2142 void Assembler::sel(SecondaryField fmt, FPURegister fd,
2143 FPURegister ft, FPURegister fs, uint8_t sel) {
2144 DCHECK(kArchVariant == kMips64r6);
2148 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
2149 fs.code() << kFsShift | fd.code() << kFdShift | SEL;
2155 void Assembler::seleqz(Register rs, Register rt, Register rd) {
2156 DCHECK(kArchVariant == kMips64r6);
2157 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
2162 void Assembler::seleqz(SecondaryField fmt, FPURegister fd,
2163 FPURegister ft, FPURegister fs) {
2164 DCHECK(kArchVariant == kMips64r6);
2168 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
2169 fs.code() << kFsShift | fd.code() << kFdShift | SELEQZ_C;
2175 void Assembler::selnez(Register rs, Register rt, Register rd) {
2176 DCHECK(kArchVariant == kMips64r6);
2177 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
2182 void Assembler::selnez(SecondaryField fmt, FPURegister fd,
2183 FPURegister ft, FPURegister fs) {
2184 DCHECK(kArchVariant == kMips64r6);
2188 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
2189 fs.code() << kFsShift | fd.code() << kFdShift | SELNEZ_C;
2195 void Assembler::clz(Register rd, Register rs) {
2196 if (kArchVariant != kMips64r6) {
2197 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
2198 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
2200 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
2205 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2206 // Should be called via MacroAssembler::Ins.
2207 // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
2208 DCHECK((kArchVariant == kMips64r2) || (kArchVariant == kMips64r6));
2209 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
2213 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2214 // Should be called via MacroAssembler::Ext.
2215 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
2216 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2217 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
2221 void Assembler::dext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2222 // Should be called via MacroAssembler::Ext.
2223 // Dext instr has 'rt' field as dest, and two uint5: msb, lsb.
2224 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2225 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT);
2229 void Assembler::pref(int32_t hint, const MemOperand& rs) {
2230 DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
2231 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
2237 // --------Coprocessor-instructions----------------
2239 // Load, store, move.
2240 void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
2241 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
2245 void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
2246 GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
2250 void Assembler::swc1(FPURegister fd, const MemOperand& src) {
2251 GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
2255 void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
2256 GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
2260 void Assembler::mtc1(Register rt, FPURegister fs) {
2261 GenInstrRegister(COP1, MTC1, rt, fs, f0);
2265 void Assembler::mthc1(Register rt, FPURegister fs) {
2266 GenInstrRegister(COP1, MTHC1, rt, fs, f0);
2270 void Assembler::dmtc1(Register rt, FPURegister fs) {
2271 GenInstrRegister(COP1, DMTC1, rt, fs, f0);
2275 void Assembler::mfc1(Register rt, FPURegister fs) {
2276 GenInstrRegister(COP1, MFC1, rt, fs, f0);
2280 void Assembler::mfhc1(Register rt, FPURegister fs) {
2281 GenInstrRegister(COP1, MFHC1, rt, fs, f0);
2285 void Assembler::dmfc1(Register rt, FPURegister fs) {
2286 GenInstrRegister(COP1, DMFC1, rt, fs, f0);
2290 void Assembler::ctc1(Register rt, FPUControlRegister fs) {
2291 GenInstrRegister(COP1, CTC1, rt, fs);
2295 void Assembler::cfc1(Register rt, FPUControlRegister fs) {
2296 GenInstrRegister(COP1, CFC1, rt, fs);
2300 void Assembler::DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) {
2304 *lo = i & 0xffffffff;
2311 void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2312 GenInstrRegister(COP1, D, ft, fs, fd, ADD_D);
2316 void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2317 GenInstrRegister(COP1, D, ft, fs, fd, SUB_D);
2321 void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2322 GenInstrRegister(COP1, D, ft, fs, fd, MUL_D);
2326 void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
2328 GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D);
2332 void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2333 GenInstrRegister(COP1, D, ft, fs, fd, DIV_D);
2337 void Assembler::abs_d(FPURegister fd, FPURegister fs) {
2338 GenInstrRegister(COP1, D, f0, fs, fd, ABS_D);
2342 void Assembler::mov_d(FPURegister fd, FPURegister fs) {
2343 GenInstrRegister(COP1, D, f0, fs, fd, MOV_D);
2347 void Assembler::neg_d(FPURegister fd, FPURegister fs) {
2348 GenInstrRegister(COP1, D, f0, fs, fd, NEG_D);
2352 void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
2353 GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D);
2359 void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) {
2360 GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S);
2364 void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) {
2365 GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D);
2369 void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) {
2370 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S);
2374 void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) {
2375 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D);
2379 void Assembler::round_w_s(FPURegister fd, FPURegister fs) {
2380 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S);
2384 void Assembler::round_w_d(FPURegister fd, FPURegister fs) {
2385 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D);
2389 void Assembler::floor_w_s(FPURegister fd, FPURegister fs) {
2390 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S);
2394 void Assembler::floor_w_d(FPURegister fd, FPURegister fs) {
2395 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D);
2399 void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) {
2400 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
2404 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
2405 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
2409 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
2410 DCHECK(kArchVariant == kMips64r2);
2411 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
2415 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
2416 DCHECK(kArchVariant == kMips64r2);
2417 GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
2421 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
2422 DCHECK(kArchVariant == kMips64r2);
2423 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
2427 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
2428 DCHECK(kArchVariant == kMips64r2);
2429 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
2433 void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
2434 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
2438 void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
2439 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
2443 void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
2444 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
2448 void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
2449 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
2453 void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
2454 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
2458 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
2459 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
2463 void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister ft,
2465 DCHECK(kArchVariant == kMips64r6);
2466 DCHECK((fmt == D) || (fmt == S));
2467 GenInstrRegister(COP1, fmt, ft, fs, fd, MIN);
2471 void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister ft,
2473 DCHECK(kArchVariant == kMips64r6);
2474 DCHECK((fmt == D) || (fmt == S));
2475 GenInstrRegister(COP1, fmt, ft, fs, fd, MINA);
2479 void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister ft,
2481 DCHECK(kArchVariant == kMips64r6);
2482 DCHECK((fmt == D) || (fmt == S));
2483 GenInstrRegister(COP1, fmt, ft, fs, fd, MAX);
2487 void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister ft,
2489 DCHECK(kArchVariant == kMips64r6);
2490 DCHECK((fmt == D) || (fmt == S));
2491 GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA);
2495 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
2496 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
2500 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
2501 DCHECK(kArchVariant == kMips64r2);
2502 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
2506 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
2507 GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
2511 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
2512 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
2516 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
2517 DCHECK(kArchVariant == kMips64r2);
2518 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
2522 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
2523 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
2527 // Conditions for >= MIPSr6.
2528 void Assembler::cmp(FPUCondition cond, SecondaryField fmt,
2529 FPURegister fd, FPURegister fs, FPURegister ft) {
2530 DCHECK(kArchVariant == kMips64r6);
2531 DCHECK((fmt & ~(31 << kRsShift)) == 0);
2532 Instr instr = COP1 | fmt | ft.code() << kFtShift |
2533 fs.code() << kFsShift | fd.code() << kFdShift | (0 << 5) | cond;
2538 void Assembler::bc1eqz(int16_t offset, FPURegister ft) {
2539 DCHECK(kArchVariant == kMips64r6);
2540 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
2545 void Assembler::bc1nez(int16_t offset, FPURegister ft) {
2546 DCHECK(kArchVariant == kMips64r6);
2547 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
2552 // Conditions for < MIPSr6.
2553 void Assembler::c(FPUCondition cond, SecondaryField fmt,
2554 FPURegister fs, FPURegister ft, uint16_t cc) {
2555 DCHECK(kArchVariant != kMips64r6);
2556 DCHECK(is_uint3(cc));
2557 DCHECK((fmt & ~(31 << kRsShift)) == 0);
2558 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift
2559 | cc << 8 | 3 << 4 | cond;
2564 void Assembler::fcmp(FPURegister src1, const double src2,
2565 FPUCondition cond) {
2566 DCHECK(src2 == 0.0);
2567 mtc1(zero_reg, f14);
2569 c(cond, D, src1, f14, 0);
2573 void Assembler::bc1f(int16_t offset, uint16_t cc) {
2574 DCHECK(is_uint3(cc));
2575 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
2580 void Assembler::bc1t(int16_t offset, uint16_t cc) {
2581 DCHECK(is_uint3(cc));
2582 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
2588 int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
2589 intptr_t pc_delta) {
2590 if (RelocInfo::IsInternalReference(rmode)) {
2591 int64_t* p = reinterpret_cast<int64_t*>(pc);
2592 if (*p == kEndOfJumpChain) {
2593 return 0; // Number of instructions patched.
2596 return 2; // Number of instructions patched.
2598 Instr instr = instr_at(pc);
2599 DCHECK(RelocInfo::IsInternalReferenceEncoded(rmode));
2600 DCHECK(IsJ(instr) || IsLui(instr));
2602 Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize);
2603 Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize);
2604 Instr instr_ori2 = instr_at(pc + 3 * Assembler::kInstrSize);
2605 DCHECK(IsOri(instr_ori));
2606 DCHECK(IsOri(instr_ori2));
2607 // TODO(plind): symbolic names for the shifts.
2608 int64_t imm = (instr_lui & static_cast<int64_t>(kImm16Mask)) << 48;
2609 imm |= (instr_ori & static_cast<int64_t>(kImm16Mask)) << 32;
2610 imm |= (instr_ori2 & static_cast<int64_t>(kImm16Mask)) << 16;
2611 // Sign extend address.
2614 if (imm == kEndOfJumpChain) {
2615 return 0; // Number of instructions patched.
2618 DCHECK((imm & 3) == 0);
2620 instr_lui &= ~kImm16Mask;
2621 instr_ori &= ~kImm16Mask;
2622 instr_ori2 &= ~kImm16Mask;
2624 instr_at_put(pc + 0 * Assembler::kInstrSize,
2625 instr_lui | ((imm >> 32) & kImm16Mask));
2626 instr_at_put(pc + 1 * Assembler::kInstrSize,
2627 instr_ori | (imm >> 16 & kImm16Mask));
2628 instr_at_put(pc + 3 * Assembler::kInstrSize,
2629 instr_ori2 | (imm & kImm16Mask));
2630 return 4; // Number of instructions patched.
2632 uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
2633 if (static_cast<int32_t>(imm28) == kEndOfJumpChain) {
2634 return 0; // Number of instructions patched.
2638 imm28 &= kImm28Mask;
2639 DCHECK((imm28 & 3) == 0);
2641 instr &= ~kImm26Mask;
2642 uint32_t imm26 = imm28 >> 2;
2643 DCHECK(is_uint26(imm26));
2645 instr_at_put(pc, instr | (imm26 & kImm26Mask));
2646 return 1; // Number of instructions patched.
2651 void Assembler::GrowBuffer() {
2652 if (!own_buffer_) FATAL("external code buffer is too small");
2654 // Compute new buffer size.
2655 CodeDesc desc; // The new buffer.
2656 if (buffer_size_ < 1 * MB) {
2657 desc.buffer_size = 2*buffer_size_;
2659 desc.buffer_size = buffer_size_ + 1*MB;
2661 CHECK_GT(desc.buffer_size, 0); // No overflow.
2663 // Set up new buffer.
2664 desc.buffer = NewArray<byte>(desc.buffer_size);
2666 desc.instr_size = pc_offset();
2667 desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
2670 intptr_t pc_delta = desc.buffer - buffer_;
2671 intptr_t rc_delta = (desc.buffer + desc.buffer_size) -
2672 (buffer_ + buffer_size_);
2673 MemMove(desc.buffer, buffer_, desc.instr_size);
2674 MemMove(reloc_info_writer.pos() + rc_delta,
2675 reloc_info_writer.pos(), desc.reloc_size);
2678 DeleteArray(buffer_);
2679 buffer_ = desc.buffer;
2680 buffer_size_ = desc.buffer_size;
2682 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2683 reloc_info_writer.last_pc() + pc_delta);
2685 // Relocate runtime entries.
2686 for (RelocIterator it(desc); !it.done(); it.next()) {
2687 RelocInfo::Mode rmode = it.rinfo()->rmode();
2688 if (rmode == RelocInfo::INTERNAL_REFERENCE_ENCODED ||
2689 rmode == RelocInfo::INTERNAL_REFERENCE) {
2690 byte* p = reinterpret_cast<byte*>(it.rinfo()->pc());
2691 RelocateInternalReference(rmode, p, pc_delta);
2694 DCHECK(!overflow());
2698 void Assembler::db(uint8_t data) {
2700 *reinterpret_cast<uint8_t*>(pc_) = data;
2701 pc_ += sizeof(uint8_t);
2705 void Assembler::dd(uint32_t data) {
2707 *reinterpret_cast<uint32_t*>(pc_) = data;
2708 pc_ += sizeof(uint32_t);
2712 void Assembler::dd(Label* label) {
2714 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2715 if (label->is_bound()) {
2716 uint64_t data = reinterpret_cast<uint64_t>(buffer_ + label->pos());
2717 *reinterpret_cast<uint64_t*>(pc_) = data;
2718 pc_ += sizeof(uint64_t);
2720 uint64_t target_pos = jump_address(label);
2722 internal_reference_positions_.insert(label->pos());
2727 void Assembler::emit_code_stub_address(Code* stub) {
2729 *reinterpret_cast<uint64_t*>(pc_) =
2730 reinterpret_cast<uint64_t>(stub->instruction_start());
2731 pc_ += sizeof(uint64_t);
2735 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2736 // We do not try to reuse pool constants.
2737 RelocInfo rinfo(pc_, rmode, data, NULL);
2738 if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) {
2739 // Adjust code for new modes.
2740 DCHECK(RelocInfo::IsDebugBreakSlot(rmode)
2741 || RelocInfo::IsJSReturn(rmode)
2742 || RelocInfo::IsComment(rmode)
2743 || RelocInfo::IsPosition(rmode));
2744 // These modes do not need an entry in the constant pool.
2746 if (!RelocInfo::IsNone(rinfo.rmode())) {
2747 // Don't record external references unless the heap will be serialized.
2748 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2749 !serializer_enabled() && !emit_debug_code()) {
2752 DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here.
2753 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
2754 RelocInfo reloc_info_with_ast_id(pc_,
2756 RecordedAstId().ToInt(),
2758 ClearRecordedAstId();
2759 reloc_info_writer.Write(&reloc_info_with_ast_id);
2761 reloc_info_writer.Write(&rinfo);
2767 void Assembler::BlockTrampolinePoolFor(int instructions) {
2768 BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize);
2772 void Assembler::CheckTrampolinePool() {
2773 // Some small sequences of instructions must not be broken up by the
2774 // insertion of a trampoline pool; such sequences are protected by setting
2775 // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_,
2776 // which are both checked here. Also, recursive calls to CheckTrampolinePool
2777 // are blocked by trampoline_pool_blocked_nesting_.
2778 if ((trampoline_pool_blocked_nesting_ > 0) ||
2779 (pc_offset() < no_trampoline_pool_before_)) {
2780 // Emission is currently blocked; make sure we try again as soon as
2782 if (trampoline_pool_blocked_nesting_ > 0) {
2783 next_buffer_check_ = pc_offset() + kInstrSize;
2785 next_buffer_check_ = no_trampoline_pool_before_;
2790 DCHECK(!trampoline_emitted_);
2791 DCHECK(unbound_labels_count_ >= 0);
2792 if (unbound_labels_count_ > 0) {
2793 // First we emit jump (2 instructions), then we emit trampoline pool.
2794 { BlockTrampolinePoolScope block_trampoline_pool(this);
2799 int pool_start = pc_offset();
2800 for (int i = 0; i < unbound_labels_count_; i++) {
2802 imm64 = jump_address(&after_pool);
2803 { BlockGrowBufferScope block_buf_growth(this);
2804 // Buffer growth (and relocation) must be blocked for internal
2805 // references until associated instructions are emitted and available
2807 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE_ENCODED);
2808 // TODO(plind): Verify this, presume I cannot use macro-assembler
2810 lui(at, (imm64 >> 32) & kImm16Mask);
2811 ori(at, at, (imm64 >> 16) & kImm16Mask);
2813 ori(at, at, imm64 & kImm16Mask);
2819 trampoline_ = Trampoline(pool_start, unbound_labels_count_);
2821 trampoline_emitted_ = true;
2822 // As we are only going to emit trampoline once, we need to prevent any
2823 // further emission.
2824 next_buffer_check_ = kMaxInt;
2827 // Number of branches to unbound label at this point is zero, so we can
2828 // move next buffer check to maximum.
2829 next_buffer_check_ = pc_offset() +
2830 kMaxBranchOffset - kTrampolineSlotsSize * 16;
2836 Address Assembler::target_address_at(Address pc) {
2837 Instr instr0 = instr_at(pc);
2838 Instr instr1 = instr_at(pc + 1 * kInstrSize);
2839 Instr instr3 = instr_at(pc + 3 * kInstrSize);
2841 // Interpret 4 instructions for address generated by li: See listing in
2842 // Assembler::set_target_address_at() just below.
2843 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) &&
2844 (GetOpcodeField(instr3) == ORI)) {
2845 // Assemble the 48 bit value.
2846 int64_t addr = static_cast<int64_t>(
2847 ((uint64_t)(GetImmediate16(instr0)) << 32) |
2848 ((uint64_t)(GetImmediate16(instr1)) << 16) |
2849 ((uint64_t)(GetImmediate16(instr3))));
2851 // Sign extend to get canonical address.
2852 addr = (addr << 16) >> 16;
2853 return reinterpret_cast<Address>(addr);
2855 // We should never get here, force a bad address if we do.
2857 return (Address)0x0;
2861 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
2862 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
2863 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
2864 // OS::nan_value() returns a qNaN.
2865 void Assembler::QuietNaN(HeapObject* object) {
2866 HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN());
2870 // On Mips64, a target address is stored in a 4-instruction sequence:
2871 // 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask);
2872 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
2873 // 2: dsll(rd, rd, 16);
2874 // 3: ori(rd, rd, j.imm32_ & kImm16Mask);
2876 // Patching the address must replace all the lui & ori instructions,
2877 // and flush the i-cache.
2879 // There is an optimization below, which emits a nop when the address
2880 // fits in just 16 bits. This is unlikely to help, and should be benchmarked,
2881 // and possibly removed.
2882 void Assembler::set_target_address_at(Address pc,
2884 ICacheFlushMode icache_flush_mode) {
2885 // There is an optimization where only 4 instructions are used to load address
2886 // in code on MIP64 because only 48-bits of address is effectively used.
2887 // It relies on fact the upper [63:48] bits are not used for virtual address
2888 // translation and they have to be set according to value of bit 47 in order
2889 // get canonical address.
2890 Instr instr1 = instr_at(pc + kInstrSize);
2891 uint32_t rt_code = GetRt(instr1);
2892 uint32_t* p = reinterpret_cast<uint32_t*>(pc);
2893 uint64_t itarget = reinterpret_cast<uint64_t>(target);
2896 // Check we have the result from a li macro-instruction.
2897 Instr instr0 = instr_at(pc);
2898 Instr instr3 = instr_at(pc + kInstrSize * 3);
2899 CHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI &&
2900 GetOpcodeField(instr3) == ORI));
2903 // Must use 4 instructions to insure patchable code.
2904 // lui rt, upper-16.
2905 // ori rt, rt, lower-16.
2907 // ori rt rt, lower-16.
2908 *p = LUI | (rt_code << kRtShift) | ((itarget >> 32) & kImm16Mask);
2909 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift)
2910 | ((itarget >> 16) & kImm16Mask);
2911 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
2912 | (itarget & kImm16Mask);
2914 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
2915 CpuFeatures::FlushICache(pc, 4 * Assembler::kInstrSize);
2920 void Assembler::JumpLabelToJumpRegister(Address pc) {
2921 // Address pc points to lui/ori instructions.
2922 // Jump to label may follow at pc + 2 * kInstrSize.
2923 uint32_t* p = reinterpret_cast<uint32_t*>(pc);
2925 Instr instr1 = instr_at(pc);
2927 Instr instr2 = instr_at(pc + 1 * kInstrSize);
2928 Instr instr3 = instr_at(pc + 6 * kInstrSize);
2929 bool patched = false;
2931 if (IsJal(instr3)) {
2932 DCHECK(GetOpcodeField(instr1) == LUI);
2933 DCHECK(GetOpcodeField(instr2) == ORI);
2935 uint32_t rs_field = GetRt(instr2) << kRsShift;
2936 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.
2937 *(p+6) = SPECIAL | rs_field | rd_field | JALR;
2939 } else if (IsJ(instr3)) {
2940 DCHECK(GetOpcodeField(instr1) == LUI);
2941 DCHECK(GetOpcodeField(instr2) == ORI);
2943 uint32_t rs_field = GetRt(instr2) << kRsShift;
2944 *(p+6) = SPECIAL | rs_field | JR;
2949 CpuFeatures::FlushICache(pc+6, sizeof(int32_t));
2954 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2955 // No out-of-line constant pool support.
2956 DCHECK(!FLAG_enable_ool_constant_pool);
2957 return isolate->factory()->empty_constant_pool_array();
2961 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2962 // No out-of-line constant pool support.
2963 DCHECK(!FLAG_enable_ool_constant_pool);
2968 } } // namespace v8::internal
2970 #endif // V8_TARGET_ARCH_MIPS64