1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
42 #include "src/assembler.h"
43 #include "src/compiler.h"
44 #include "src/isolate.h"
51 // 1) We would prefer to use an enum, but enum values are assignment-
52 // compatible with int, which has caused code-generation bugs.
54 // 2) We would prefer to use a class instead of a struct but we don't like
55 // the register initialization to depend on the particular initialization
56 // order (which appears to be different on OS X, Linux, and Windows for the
57 // installed versions of C++ we tried). Using a struct permits C-style
58 // "initialization". Also, the Register objects cannot be const as this
59 // forces initialization stubs in MSVC, making us dependent on initialization
62 // 3) By not using an enum, we are possibly preventing the compiler from
63 // doing certain constant folds, which may significantly reduce the
64 // code generated for some assembly instructions (because they boil down
65 // to a few constants). If this is a problem, we could change the code
66 // such that we use an enum in optimized mode, and the struct in debug
67 // mode. This way we get the compile-time error checking in debug mode
68 // and best performance in optimized code.
71 static const int kMaxNumAllocatableRegisters = 6;
72 static int NumAllocatableRegisters() {
73 return kMaxNumAllocatableRegisters;
75 static const int kNumRegisters = 8;
77 static inline const char* AllocationIndexToString(int index);
79 static inline int ToAllocationIndex(Register reg);
81 static inline Register FromAllocationIndex(int index);
83 static Register from_code(int code) {
85 DCHECK(code < kNumRegisters);
86 Register r = { code };
89 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
90 bool is(Register reg) const { return code_ == reg.code_; }
91 // eax, ebx, ecx and edx are byte registers, the rest are not.
92 bool is_byte_register() const { return code_ <= 3; }
102 // Unfortunately we can't make this private in a struct.
106 const int kRegister_eax_Code = 0;
107 const int kRegister_ecx_Code = 1;
108 const int kRegister_edx_Code = 2;
109 const int kRegister_ebx_Code = 3;
110 const int kRegister_esp_Code = 4;
111 const int kRegister_ebp_Code = 5;
112 const int kRegister_esi_Code = 6;
113 const int kRegister_edi_Code = 7;
114 const int kRegister_no_reg_Code = -1;
116 const Register eax = { kRegister_eax_Code };
117 const Register ecx = { kRegister_ecx_Code };
118 const Register edx = { kRegister_edx_Code };
119 const Register ebx = { kRegister_ebx_Code };
120 const Register esp = { kRegister_esp_Code };
121 const Register ebp = { kRegister_ebp_Code };
122 const Register esi = { kRegister_esi_Code };
123 const Register edi = { kRegister_edi_Code };
124 const Register no_reg = { kRegister_no_reg_Code };
127 inline const char* Register::AllocationIndexToString(int index) {
128 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
129 // This is the mapping of allocation indices to registers.
130 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
131 return kNames[index];
135 inline int Register::ToAllocationIndex(Register reg) {
136 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
137 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
141 inline Register Register::FromAllocationIndex(int index) {
142 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
143 return (index >= 4) ? from_code(index + 2) : from_code(index);
148 static const int kMaxNumAllocatableRegisters = 7;
149 static const int kMaxNumRegisters = 8;
150 static int NumAllocatableRegisters() {
151 return kMaxNumAllocatableRegisters;
154 // TODO(turbofan): Proper support for float32.
155 static int NumAllocatableAliasedRegisters() {
156 return NumAllocatableRegisters();
159 static int ToAllocationIndex(XMMRegister reg) {
160 DCHECK(reg.code() != 0);
161 return reg.code() - 1;
164 static XMMRegister FromAllocationIndex(int index) {
165 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
166 return from_code(index + 1);
169 static XMMRegister from_code(int code) {
170 XMMRegister result = { code };
174 bool is_valid() const {
175 return 0 <= code_ && code_ < kMaxNumRegisters;
183 bool is(XMMRegister reg) const { return code_ == reg.code_; }
185 static const char* AllocationIndexToString(int index) {
186 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
187 const char* const names[] = {
203 typedef XMMRegister DoubleRegister;
206 const XMMRegister xmm0 = { 0 };
207 const XMMRegister xmm1 = { 1 };
208 const XMMRegister xmm2 = { 2 };
209 const XMMRegister xmm3 = { 3 };
210 const XMMRegister xmm4 = { 4 };
211 const XMMRegister xmm5 = { 5 };
212 const XMMRegister xmm6 = { 6 };
213 const XMMRegister xmm7 = { 7 };
214 const XMMRegister no_xmm_reg = { -1 };
218 // any value < 0 is considered no_condition
240 not_carry = above_equal,
242 not_zero = not_equal,
248 // Returns the equivalent of !cc.
249 // Negation of the default no_condition (-1) results in a non-default
250 // no_condition value (-2). As long as tests for no_condition check
251 // for condition < 0, this will work as expected.
252 inline Condition NegateCondition(Condition cc) {
253 return static_cast<Condition>(cc ^ 1);
257 // Commute a condition such that {a cond b == b cond' a}.
258 inline Condition CommuteCondition(Condition cc) {
275 return greater_equal;
283 kRoundToNearest = 0x0,
290 // -----------------------------------------------------------------------------
291 // Machine instruction Immediates
293 class Immediate BASE_EMBEDDED {
295 inline explicit Immediate(int x);
296 inline explicit Immediate(const ExternalReference& ext);
297 inline explicit Immediate(Handle<Object> handle);
298 inline explicit Immediate(Smi* value);
299 inline explicit Immediate(Address addr);
301 static Immediate CodeRelativeOffset(Label* label) {
302 return Immediate(label);
305 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
306 bool is_int8() const {
307 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
309 bool is_int16() const {
310 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
314 inline explicit Immediate(Label* value);
317 RelocInfo::Mode rmode_;
319 friend class Operand;
320 friend class Assembler;
321 friend class MacroAssembler;
325 // -----------------------------------------------------------------------------
326 // Machine instruction Operands
333 times_int_size = times_4,
334 times_half_pointer_size = times_2,
335 times_pointer_size = times_4,
336 times_twice_pointer_size = times_8
340 class Operand BASE_EMBEDDED {
343 INLINE(explicit Operand(Register reg));
346 INLINE(explicit Operand(XMMRegister xmm_reg));
349 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
352 INLINE(explicit Operand(Immediate imm));
355 explicit Operand(Register base, int32_t disp,
356 RelocInfo::Mode rmode = RelocInfo::NONE32);
358 // [base + index*scale + disp/r]
359 explicit Operand(Register base,
363 RelocInfo::Mode rmode = RelocInfo::NONE32);
365 // [index*scale + disp/r]
366 explicit Operand(Register index,
369 RelocInfo::Mode rmode = RelocInfo::NONE32);
371 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) {
372 return Operand(index, scale, reinterpret_cast<int32_t>(table),
373 RelocInfo::INTERNAL_REFERENCE);
376 static Operand StaticVariable(const ExternalReference& ext) {
377 return Operand(reinterpret_cast<int32_t>(ext.address()),
378 RelocInfo::EXTERNAL_REFERENCE);
381 static Operand StaticArray(Register index,
383 const ExternalReference& arr) {
384 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
385 RelocInfo::EXTERNAL_REFERENCE);
388 static Operand ForCell(Handle<Cell> cell) {
389 AllowDeferredHandleDereference embedding_raw_address;
390 return Operand(reinterpret_cast<int32_t>(cell.location()),
394 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
395 return Operand(base, imm.x_, imm.rmode_);
398 // Returns true if this Operand is a wrapper for the specified register.
399 bool is_reg(Register reg) const;
401 // Returns true if this Operand is a wrapper for one register.
402 bool is_reg_only() const;
404 // Asserts that this Operand is a wrapper for one register and returns the
406 Register reg() const;
409 // Set the ModRM byte without an encoded 'reg' register. The
410 // register is encoded later as part of the emit_operand operation.
411 inline void set_modrm(int mod, Register rm);
413 inline void set_sib(ScaleFactor scale, Register index, Register base);
414 inline void set_disp8(int8_t disp);
415 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
418 // The number of bytes in buf_.
420 // Only valid if len_ > 4.
421 RelocInfo::Mode rmode_;
423 friend class Assembler;
424 friend class MacroAssembler;
428 // -----------------------------------------------------------------------------
429 // A Displacement describes the 32bit immediate field of an instruction which
430 // may be used together with a Label in order to refer to a yet unknown code
431 // position. Displacements stored in the instruction stream are used to describe
432 // the instruction and to chain a list of instructions using the same Label.
433 // A Displacement contains 2 different fields:
435 // next field: position of next displacement in the chain (0 = end of list)
436 // type field: instruction type
438 // A next value of null (0) indicates the end of a chain (note that there can
439 // be no displacement at position zero, because there is always at least one
440 // instruction byte before the displacement).
442 // Displacement _data field layout
444 // |31.....2|1......0|
447 class Displacement BASE_EMBEDDED {
449 enum Type { UNCONDITIONAL_JUMP, CODE_RELATIVE, OTHER, CODE_ABSOLUTE };
451 int data() const { return data_; }
452 Type type() const { return TypeField::decode(data_); }
453 void next(Label* L) const {
454 int n = NextField::decode(data_);
455 n > 0 ? L->link_to(n) : L->Unuse();
457 void link_to(Label* L) { init(L, type()); }
459 explicit Displacement(int data) { data_ = data; }
461 Displacement(Label* L, Type type) { init(L, type); }
464 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
465 NextField::decode(data_));
471 class TypeField: public BitField<Type, 0, 2> {};
472 class NextField: public BitField<int, 2, 32-2> {};
474 void init(Label* L, Type type);
478 class Assembler : public AssemblerBase {
480 // We check before assembling an instruction that there is sufficient
481 // space to write an instruction and its relocation information.
482 // The relocation writer's position must be kGap bytes above the end of
483 // the generated instructions. This leaves enough space for the
484 // longest possible ia32 instruction, 15 bytes, and the longest possible
485 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
486 // (There is a 15 byte limit on ia32 instruction length that rules out some
487 // otherwise valid instructions.)
488 // This allows for a single, fast space check per instruction.
489 static const int kGap = 32;
492 // Create an assembler. Instructions and relocation information are emitted
493 // into a buffer, with the instructions starting from the beginning and the
494 // relocation information starting from the end of the buffer. See CodeDesc
495 // for a detailed comment on the layout (globals.h).
497 // If the provided buffer is NULL, the assembler allocates and grows its own
498 // buffer, and buffer_size determines the initial buffer size. The buffer is
499 // owned by the assembler and deallocated upon destruction of the assembler.
501 // If the provided buffer is not NULL, the assembler uses the provided buffer
502 // for code generation and assumes its size to be buffer_size. If the buffer
503 // is too small, a fatal error occurs. No deallocation of the buffer is done
504 // upon destruction of the assembler.
505 // TODO(vitalyr): the assembler does not need an isolate.
506 Assembler(Isolate* isolate, void* buffer, int buffer_size);
507 virtual ~Assembler() { }
509 // GetCode emits any pending (non-emitted) code and fills the descriptor
510 // desc. GetCode() is idempotent; it returns the same result if no other
511 // Assembler functions are invoked in between GetCode() calls.
512 void GetCode(CodeDesc* desc);
514 // Read/Modify the code target in the branch/call instruction at pc.
515 inline static Address target_address_at(Address pc,
516 ConstantPoolArray* constant_pool);
517 inline static void set_target_address_at(Address pc,
518 ConstantPoolArray* constant_pool,
520 ICacheFlushMode icache_flush_mode =
521 FLUSH_ICACHE_IF_NEEDED);
522 static inline Address target_address_at(Address pc, Code* code) {
523 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
524 return target_address_at(pc, constant_pool);
526 static inline void set_target_address_at(Address pc,
529 ICacheFlushMode icache_flush_mode =
530 FLUSH_ICACHE_IF_NEEDED) {
531 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
532 set_target_address_at(pc, constant_pool, target);
535 // Return the code target address at a call site from the return address
536 // of that call in the instruction stream.
537 inline static Address target_address_from_return_address(Address pc);
539 // Return the code target address of the patch debug break slot
540 inline static Address break_address_from_return_address(Address pc);
542 // This sets the branch destination (which is in the instruction on x86).
543 // This is for calls and branches within generated code.
544 inline static void deserialization_set_special_target_at(
545 Address instruction_payload, Code* code, Address target) {
546 set_target_address_at(instruction_payload, code, target);
549 // This sets the internal reference at the pc.
550 inline static void deserialization_set_target_internal_reference_at(
551 Address pc, Address target,
552 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
554 static const int kSpecialTargetSize = kPointerSize;
556 // Distance between the address of the code target in the call instruction
557 // and the return address
558 static const int kCallTargetAddressOffset = kPointerSize;
559 // Distance between start of patched return sequence and the emitted address
561 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
563 // Distance between start of patched debug break slot and the emitted address
565 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
567 static const int kCallInstructionLength = 5;
568 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
569 static const int kJSReturnSequenceLength = 6;
571 // The debug break slot must be able to contain a call instruction.
572 static const int kDebugBreakSlotLength = kCallInstructionLength;
574 // One byte opcode for test al, 0xXX.
575 static const byte kTestAlByte = 0xA8;
576 // One byte opcode for nop.
577 static const byte kNopByte = 0x90;
579 // One byte opcode for a short unconditional jump.
580 static const byte kJmpShortOpcode = 0xEB;
581 // One byte prefix for a short conditional jump.
582 static const byte kJccShortPrefix = 0x70;
583 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
584 static const byte kJcShortOpcode = kJccShortPrefix | carry;
585 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
586 static const byte kJzShortOpcode = kJccShortPrefix | zero;
589 // ---------------------------------------------------------------------------
592 // - function names correspond one-to-one to ia32 instruction mnemonics
593 // - unless specified otherwise, instructions operate on 32bit operands
594 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
595 // - instructions on 16bit (word) operands/registers have a trailing '_w'
596 // - naming conflicts with C++ keywords are resolved via a trailing '_'
598 // NOTE ON INTERFACE: Currently, the interface is not very consistent
599 // in the sense that some operations (e.g. mov()) can be called in more
600 // the one way to generate the same instruction: The Register argument
601 // can in some cases be replaced with an Operand(Register) argument.
602 // This should be cleaned up and made more orthogonal. The questions
603 // is: should we always use Operands instead of Registers where an
604 // Operand is possible, or should we have a Register (overloaded) form
605 // instead? We must be careful to make sure that the selected instruction
606 // is obvious from the parameters to avoid hard-to-find code generation
609 // Insert the smallest number of nop instructions
610 // possible to align the pc offset to a multiple
611 // of m. m must be a power of 2.
613 void Nop(int bytes = 1);
614 // Aligns code to something that's optimal for a jump target for the platform.
615 void CodeTargetAlign();
624 void push(const Immediate& x);
625 void push_imm32(int32_t imm32);
626 void push(Register src);
627 void push(const Operand& src);
629 void pop(Register dst);
630 void pop(const Operand& dst);
632 void enter(const Immediate& size);
636 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
637 void mov_b(Register dst, const Operand& src);
638 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
639 void mov_b(const Operand& dst, int8_t src) { mov_b(dst, Immediate(src)); }
640 void mov_b(const Operand& dst, const Immediate& src);
641 void mov_b(const Operand& dst, Register src);
643 void mov_w(Register dst, const Operand& src);
644 void mov_w(const Operand& dst, int16_t src) { mov_w(dst, Immediate(src)); }
645 void mov_w(const Operand& dst, const Immediate& src);
646 void mov_w(const Operand& dst, Register src);
648 void mov(Register dst, int32_t imm32);
649 void mov(Register dst, const Immediate& x);
650 void mov(Register dst, Handle<Object> handle);
651 void mov(Register dst, const Operand& src);
652 void mov(Register dst, Register src);
653 void mov(const Operand& dst, const Immediate& x);
654 void mov(const Operand& dst, Handle<Object> handle);
655 void mov(const Operand& dst, Register src);
657 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
658 void movsx_b(Register dst, const Operand& src);
660 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
661 void movsx_w(Register dst, const Operand& src);
663 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
664 void movzx_b(Register dst, const Operand& src);
666 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
667 void movzx_w(Register dst, const Operand& src);
670 void cmov(Condition cc, Register dst, Register src) {
671 cmov(cc, dst, Operand(src));
673 void cmov(Condition cc, Register dst, const Operand& src);
678 // Repetitive string instructions.
684 void xchg(Register dst, Register src);
685 void xchg(Register dst, const Operand& src);
688 void adc(Register dst, int32_t imm32);
689 void adc(Register dst, const Operand& src);
691 void add(Register dst, Register src) { add(dst, Operand(src)); }
692 void add(Register dst, const Operand& src);
693 void add(const Operand& dst, Register src);
694 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
695 void add(const Operand& dst, const Immediate& x);
697 void and_(Register dst, int32_t imm32);
698 void and_(Register dst, const Immediate& x);
699 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
700 void and_(Register dst, const Operand& src);
701 void and_(const Operand& dst, Register src);
702 void and_(const Operand& dst, const Immediate& x);
704 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
705 void cmpb(const Operand& op, int8_t imm8);
706 void cmpb(Register reg, const Operand& op);
707 void cmpb(const Operand& op, Register reg);
708 void cmpb_al(const Operand& op);
709 void cmpw_ax(const Operand& op);
710 void cmpw(const Operand& op, Immediate imm16);
711 void cmp(Register reg, int32_t imm32);
712 void cmp(Register reg, Handle<Object> handle);
713 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
714 void cmp(Register reg, const Operand& op);
715 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
716 void cmp(const Operand& op, const Immediate& imm);
717 void cmp(const Operand& op, Handle<Object> handle);
719 void dec_b(Register dst);
720 void dec_b(const Operand& dst);
722 void dec(Register dst);
723 void dec(const Operand& dst);
727 void idiv(Register src) { idiv(Operand(src)); }
728 void idiv(const Operand& src);
729 void div(Register src) { div(Operand(src)); }
730 void div(const Operand& src);
732 // Signed multiply instructions.
733 void imul(Register src); // edx:eax = eax * src.
734 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
735 void imul(Register dst, const Operand& src); // dst = dst * src.
736 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
737 void imul(Register dst, const Operand& src, int32_t imm32);
739 void inc(Register dst);
740 void inc(const Operand& dst);
742 void lea(Register dst, const Operand& src);
744 // Unsigned multiply instruction.
745 void mul(Register src); // edx:eax = eax * reg.
747 void neg(Register dst);
748 void neg(const Operand& dst);
750 void not_(Register dst);
751 void not_(const Operand& dst);
753 void or_(Register dst, int32_t imm32);
754 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
755 void or_(Register dst, const Operand& src);
756 void or_(const Operand& dst, Register src);
757 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
758 void or_(const Operand& dst, const Immediate& x);
760 void rcl(Register dst, uint8_t imm8);
761 void rcr(Register dst, uint8_t imm8);
763 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
764 void ror(const Operand& dst, uint8_t imm8);
765 void ror_cl(Register dst) { ror_cl(Operand(dst)); }
766 void ror_cl(const Operand& dst);
768 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
769 void sar(const Operand& dst, uint8_t imm8);
770 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
771 void sar_cl(const Operand& dst);
773 void sbb(Register dst, const Operand& src);
775 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
776 void shld(Register dst, const Operand& src);
778 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
779 void shl(const Operand& dst, uint8_t imm8);
780 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
781 void shl_cl(const Operand& dst);
783 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
784 void shrd(Register dst, const Operand& src);
786 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
787 void shr(const Operand& dst, uint8_t imm8);
788 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
789 void shr_cl(const Operand& dst);
791 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
792 void sub(const Operand& dst, const Immediate& x);
793 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
794 void sub(Register dst, const Operand& src);
795 void sub(const Operand& dst, Register src);
797 void test(Register reg, const Immediate& imm);
798 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
799 void test(Register reg, const Operand& op);
800 void test_b(Register reg, const Operand& op);
801 void test(const Operand& op, const Immediate& imm);
802 void test_b(Register reg, uint8_t imm8);
803 void test_b(const Operand& op, uint8_t imm8);
805 void xor_(Register dst, int32_t imm32);
806 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
807 void xor_(Register dst, const Operand& src);
808 void xor_(const Operand& dst, Register src);
809 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
810 void xor_(const Operand& dst, const Immediate& x);
813 void bt(const Operand& dst, Register src);
814 void bts(Register dst, Register src) { bts(Operand(dst), src); }
815 void bts(const Operand& dst, Register src);
816 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
817 void bsr(Register dst, const Operand& src);
826 // Label operations & relative jumps (PPUM Appendix D)
828 // Takes a branch opcode (cc) and a label (L) and generates
829 // either a backward branch or a forward branch and links it
830 // to the label fixup chain. Usage:
832 // Label L; // unbound label
833 // j(cc, &L); // forward branch to unbound label
834 // bind(&L); // bind label to the current pc
835 // j(cc, &L); // backward branch to bound label
836 // bind(&L); // illegal: a label may be bound only once
838 // Note: The same Label can be used for forward and backward branches
839 // but it may be bound only once.
841 void bind(Label* L); // binds an unbound label L to the current code position
845 void call(byte* entry, RelocInfo::Mode rmode);
846 int CallSize(const Operand& adr);
847 void call(Register reg) { call(Operand(reg)); }
848 void call(const Operand& adr);
849 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
850 void call(Handle<Code> code,
851 RelocInfo::Mode rmode,
852 TypeFeedbackId id = TypeFeedbackId::None());
855 // unconditional jump to L
856 void jmp(Label* L, Label::Distance distance = Label::kFar);
857 void jmp(byte* entry, RelocInfo::Mode rmode);
858 void jmp(Register reg) { jmp(Operand(reg)); }
859 void jmp(const Operand& adr);
860 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
865 Label::Distance distance = Label::kFar);
866 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
867 void j(Condition cc, Handle<Code> code);
869 // Floating-point operations
878 void fld_s(const Operand& adr);
879 void fld_d(const Operand& adr);
881 void fstp_s(const Operand& adr);
882 void fst_s(const Operand& adr);
883 void fstp_d(const Operand& adr);
884 void fst_d(const Operand& adr);
886 void fild_s(const Operand& adr);
887 void fild_d(const Operand& adr);
889 void fist_s(const Operand& adr);
891 void fistp_s(const Operand& adr);
892 void fistp_d(const Operand& adr);
894 // The fisttp instructions require SSE3.
895 void fisttp_s(const Operand& adr);
896 void fisttp_d(const Operand& adr);
917 void fisub_s(const Operand& adr);
919 void faddp(int i = 1);
920 void fsubp(int i = 1);
921 void fsubrp(int i = 1);
922 void fmulp(int i = 1);
923 void fdivp(int i = 1);
927 void fxch(int i = 1);
929 void ffree(int i = 0);
944 void setcc(Condition cc, Register reg);
949 void addss(XMMRegister dst, XMMRegister src) { addss(dst, Operand(src)); }
950 void addss(XMMRegister dst, const Operand& src);
951 void subss(XMMRegister dst, XMMRegister src) { subss(dst, Operand(src)); }
952 void subss(XMMRegister dst, const Operand& src);
953 void mulss(XMMRegister dst, XMMRegister src) { mulss(dst, Operand(src)); }
954 void mulss(XMMRegister dst, const Operand& src);
955 void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); }
956 void divss(XMMRegister dst, const Operand& src);
958 void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); }
959 void ucomiss(XMMRegister dst, const Operand& src);
960 void movaps(XMMRegister dst, XMMRegister src);
961 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
963 void andps(XMMRegister dst, const Operand& src);
964 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
965 void xorps(XMMRegister dst, const Operand& src);
966 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
967 void orps(XMMRegister dst, const Operand& src);
968 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
970 void addps(XMMRegister dst, const Operand& src);
971 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
972 void subps(XMMRegister dst, const Operand& src);
973 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
974 void mulps(XMMRegister dst, const Operand& src);
975 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
976 void divps(XMMRegister dst, const Operand& src);
977 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
980 void cvttss2si(Register dst, const Operand& src);
981 void cvttss2si(Register dst, XMMRegister src) {
982 cvttss2si(dst, Operand(src));
984 void cvttsd2si(Register dst, const Operand& src);
985 void cvttsd2si(Register dst, XMMRegister src) {
986 cvttsd2si(dst, Operand(src));
988 void cvtsd2si(Register dst, XMMRegister src);
990 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
991 void cvtsi2sd(XMMRegister dst, const Operand& src);
992 void cvtss2sd(XMMRegister dst, const Operand& src);
993 void cvtss2sd(XMMRegister dst, XMMRegister src) {
994 cvtss2sd(dst, Operand(src));
996 void cvtsd2ss(XMMRegister dst, const Operand& src);
997 void cvtsd2ss(XMMRegister dst, XMMRegister src) {
998 cvtsd2ss(dst, Operand(src));
1000 void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
1001 void addsd(XMMRegister dst, const Operand& src);
1002 void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
1003 void subsd(XMMRegister dst, const Operand& src);
1004 void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); }
1005 void mulsd(XMMRegister dst, const Operand& src);
1006 void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
1007 void divsd(XMMRegister dst, const Operand& src);
1008 void xorpd(XMMRegister dst, XMMRegister src);
1009 void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
1010 void sqrtsd(XMMRegister dst, const Operand& src);
1012 void andpd(XMMRegister dst, XMMRegister src);
1013 void orpd(XMMRegister dst, XMMRegister src);
1015 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1016 void ucomisd(XMMRegister dst, const Operand& src);
1018 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1020 void movmskpd(Register dst, XMMRegister src);
1021 void movmskps(Register dst, XMMRegister src);
1023 void cmpltsd(XMMRegister dst, XMMRegister src);
1024 void pcmpeqd(XMMRegister dst, XMMRegister src);
1026 void punpckldq(XMMRegister dst, XMMRegister src);
1027 void punpckhdq(XMMRegister dst, XMMRegister src);
1029 void maxsd(XMMRegister dst, XMMRegister src) { maxsd(dst, Operand(src)); }
1030 void maxsd(XMMRegister dst, const Operand& src);
1031 void minsd(XMMRegister dst, XMMRegister src) { minsd(dst, Operand(src)); }
1032 void minsd(XMMRegister dst, const Operand& src);
1034 void movdqa(XMMRegister dst, const Operand& src);
1035 void movdqa(const Operand& dst, XMMRegister src);
1036 void movdqu(XMMRegister dst, const Operand& src);
1037 void movdqu(const Operand& dst, XMMRegister src);
1038 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1046 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1047 void movd(XMMRegister dst, const Operand& src);
1048 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1049 void movd(const Operand& dst, XMMRegister src);
1050 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1051 void movsd(XMMRegister dst, const Operand& src);
1052 void movsd(const Operand& dst, XMMRegister src);
1055 void movss(XMMRegister dst, const Operand& src);
1056 void movss(const Operand& dst, XMMRegister src);
1057 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1058 void extractps(Register dst, XMMRegister src, byte imm8);
1060 void pand(XMMRegister dst, XMMRegister src);
1061 void pxor(XMMRegister dst, XMMRegister src);
1062 void por(XMMRegister dst, XMMRegister src);
1063 void ptest(XMMRegister dst, XMMRegister src);
1065 void pslld(XMMRegister reg, int8_t shift);
1066 void psrld(XMMRegister reg, int8_t shift);
1067 void psllq(XMMRegister reg, int8_t shift);
1068 void psllq(XMMRegister dst, XMMRegister src);
1069 void psrlq(XMMRegister reg, int8_t shift);
1070 void psrlq(XMMRegister dst, XMMRegister src);
1071 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1072 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1073 pextrd(Operand(dst), src, offset);
1075 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1076 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1077 pinsrd(dst, Operand(src), offset);
1079 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1081 // Parallel XMM operations.
1082 void movntdqa(XMMRegister dst, const Operand& src);
1083 void movntdq(const Operand& dst, XMMRegister src);
1086 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1087 vfmadd132sd(dst, src1, Operand(src2));
1089 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1090 vfmadd213sd(dst, src1, Operand(src2));
1092 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1093 vfmadd231sd(dst, src1, Operand(src2));
1095 void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1096 vfmasd(0x99, dst, src1, src2);
1098 void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1099 vfmasd(0xa9, dst, src1, src2);
1101 void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1102 vfmasd(0xb9, dst, src1, src2);
1104 void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1105 vfmsub132sd(dst, src1, Operand(src2));
1107 void vfmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1108 vfmsub213sd(dst, src1, Operand(src2));
1110 void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1111 vfmsub231sd(dst, src1, Operand(src2));
1113 void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1114 vfmasd(0x9b, dst, src1, src2);
1116 void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1117 vfmasd(0xab, dst, src1, src2);
1119 void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1120 vfmasd(0xbb, dst, src1, src2);
1122 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1123 vfnmadd132sd(dst, src1, Operand(src2));
1125 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1126 vfnmadd213sd(dst, src1, Operand(src2));
1128 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1129 vfnmadd231sd(dst, src1, Operand(src2));
1131 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1132 vfmasd(0x9d, dst, src1, src2);
1134 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1135 vfmasd(0xad, dst, src1, src2);
1137 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1138 vfmasd(0xbd, dst, src1, src2);
1140 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1141 vfnmsub132sd(dst, src1, Operand(src2));
1143 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1144 vfnmsub213sd(dst, src1, Operand(src2));
1146 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1147 vfnmsub231sd(dst, src1, Operand(src2));
1149 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1150 vfmasd(0x9f, dst, src1, src2);
1152 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1153 vfmasd(0xaf, dst, src1, src2);
1155 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1156 vfmasd(0xbf, dst, src1, src2);
1158 void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1160 void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1161 vfmadd132ss(dst, src1, Operand(src2));
1163 void vfmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1164 vfmadd213ss(dst, src1, Operand(src2));
1166 void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1167 vfmadd231ss(dst, src1, Operand(src2));
1169 void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1170 vfmass(0x99, dst, src1, src2);
1172 void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1173 vfmass(0xa9, dst, src1, src2);
1175 void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1176 vfmass(0xb9, dst, src1, src2);
1178 void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1179 vfmsub132ss(dst, src1, Operand(src2));
1181 void vfmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1182 vfmsub213ss(dst, src1, Operand(src2));
1184 void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1185 vfmsub231ss(dst, src1, Operand(src2));
1187 void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1188 vfmass(0x9b, dst, src1, src2);
1190 void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1191 vfmass(0xab, dst, src1, src2);
1193 void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1194 vfmass(0xbb, dst, src1, src2);
1196 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1197 vfnmadd132ss(dst, src1, Operand(src2));
1199 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1200 vfnmadd213ss(dst, src1, Operand(src2));
1202 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1203 vfnmadd231ss(dst, src1, Operand(src2));
1205 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1206 vfmass(0x9d, dst, src1, src2);
1208 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1209 vfmass(0xad, dst, src1, src2);
1211 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1212 vfmass(0xbd, dst, src1, src2);
1214 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1215 vfnmsub132ss(dst, src1, Operand(src2));
1217 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1218 vfnmsub213ss(dst, src1, Operand(src2));
1220 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1221 vfnmsub231ss(dst, src1, Operand(src2));
1223 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1224 vfmass(0x9f, dst, src1, src2);
1226 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1227 vfmass(0xaf, dst, src1, src2);
1229 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1230 vfmass(0xbf, dst, src1, src2);
1232 void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1234 void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1235 vaddsd(dst, src1, Operand(src2));
1237 void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1238 vsd(0x58, dst, src1, src2);
1240 void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1241 vsubsd(dst, src1, Operand(src2));
1243 void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1244 vsd(0x5c, dst, src1, src2);
1246 void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1247 vmulsd(dst, src1, Operand(src2));
1249 void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1250 vsd(0x59, dst, src1, src2);
1252 void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1253 vdivsd(dst, src1, Operand(src2));
1255 void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1256 vsd(0x5e, dst, src1, src2);
1258 void vmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1259 vmaxsd(dst, src1, Operand(src2));
1261 void vmaxsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1262 vsd(0x5f, dst, src1, src2);
1264 void vminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1265 vminsd(dst, src1, Operand(src2));
1267 void vminsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1268 vsd(0x5d, dst, src1, src2);
1270 void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1272 // Prefetch src position into cache level.
1273 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1275 void prefetch(const Operand& src, int level);
1276 // TODO(lrn): Need SFENCE for movnt?
1278 // Check the code size generated from label to here.
1279 int SizeOfCodeGeneratedSince(Label* label) {
1280 return pc_offset() - label->pos();
1283 // Mark address of the ExitJSFrame code.
1284 void RecordJSReturn();
1286 // Mark address of a debug break slot.
1287 void RecordDebugBreakSlot();
1289 // Record a comment relocation entry that can be used by a disassembler.
1290 // Use --code-comments to enable.
1291 void RecordComment(const char* msg);
1293 // Record a deoptimization reason that can be used by a log or cpu profiler.
1294 // Use --trace-deopt to enable.
1295 void RecordDeoptReason(const int reason, const SourcePosition position);
1297 // Writes a single byte or word of data in the code stream. Used for
1298 // inline tables, e.g., jump-tables.
1299 void db(uint8_t data);
1300 void dd(uint32_t data);
1301 void dd(Label* label);
1303 // Check if there is less than kGap bytes available in the buffer.
1304 // If this is the case, we need to grow the buffer before emitting
1305 // an instruction or relocation information.
1306 inline bool buffer_overflow() const {
1307 return pc_ >= reloc_info_writer.pos() - kGap;
1310 // Get the number of bytes available in the buffer.
1311 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1313 static bool IsNop(Address addr);
1315 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1317 int relocation_writer_size() {
1318 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1321 // Avoid overflows for displacements etc.
1322 static const int kMaximalBufferSize = 512*MB;
1324 byte byte_at(int pos) { return buffer_[pos]; }
1325 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1327 // Allocate a constant pool of the correct size for the generated code.
1328 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1330 // Generate the constant pool for the generated code.
1331 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1334 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1335 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1336 void emit_sse_operand(Register dst, XMMRegister src);
1337 void emit_sse_operand(XMMRegister dst, Register src);
1339 byte* addr_at(int pos) { return buffer_ + pos; }
1343 uint32_t long_at(int pos) {
1344 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1346 void long_at_put(int pos, uint32_t x) {
1347 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1352 inline void emit(uint32_t x);
1353 inline void emit(Handle<Object> handle);
1354 inline void emit(uint32_t x,
1355 RelocInfo::Mode rmode,
1356 TypeFeedbackId id = TypeFeedbackId::None());
1357 inline void emit(Handle<Code> code,
1358 RelocInfo::Mode rmode,
1359 TypeFeedbackId id = TypeFeedbackId::None());
1360 inline void emit(const Immediate& x);
1361 inline void emit_w(const Immediate& x);
1363 // Emit the code-object-relative offset of the label's position
1364 inline void emit_code_relative_offset(Label* label);
1366 // instruction generation
1367 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1369 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1370 // with a given destination expression and an immediate operand. It attempts
1371 // to use the shortest encoding possible.
1372 // sel specifies the /n in the modrm byte (see the Intel PRM).
1373 void emit_arith(int sel, Operand dst, const Immediate& x);
1375 void emit_operand(Register reg, const Operand& adr);
1377 void emit_label(Label* label);
1379 void emit_farith(int b1, int b2, int i);
1382 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 };
1383 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128 };
1384 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 };
1385 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x2 };
1386 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp,
1387 LeadingOpcode m, VexW w);
1390 void print(Label* L);
1391 void bind_to(Label* L, int pos);
1394 inline Displacement disp_at(Label* L);
1395 inline void disp_at_put(Label* L, Displacement disp);
1396 inline void emit_disp(Label* L, Displacement::Type type);
1397 inline void emit_near_disp(Label* L);
1399 // record reloc info for current pc_
1400 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1402 friend class CodePatcher;
1403 friend class EnsureSpace;
1405 // Internal reference positions, required for (potential) patching in
1406 // GrowBuffer(); contains only those internal references whose labels
1407 // are already bound.
1408 std::deque<int> internal_reference_positions_;
1411 RelocInfoWriter reloc_info_writer;
1413 PositionsRecorder positions_recorder_;
1414 friend class PositionsRecorder;
1418 // Helper class that ensures that there is enough space for generating
1419 // instructions and relocation information. The constructor makes
1420 // sure that there is enough space and (in debug mode) the destructor
1421 // checks that we did not generate too much.
1422 class EnsureSpace BASE_EMBEDDED {
1424 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1425 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1427 space_before_ = assembler_->available_space();
1433 int bytes_generated = space_before_ - assembler_->available_space();
1434 DCHECK(bytes_generated < assembler_->kGap);
1439 Assembler* assembler_;
1445 } } // namespace v8::internal
1447 #endif // V8_IA32_ASSEMBLER_IA32_H_