1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
42 #include "src/assembler.h"
43 #include "src/isolate.h"
44 #include "src/serialize.h"
51 // 1) We would prefer to use an enum, but enum values are assignment-
52 // compatible with int, which has caused code-generation bugs.
54 // 2) We would prefer to use a class instead of a struct but we don't like
55 // the register initialization to depend on the particular initialization
56 // order (which appears to be different on OS X, Linux, and Windows for the
57 // installed versions of C++ we tried). Using a struct permits C-style
58 // "initialization". Also, the Register objects cannot be const as this
59 // forces initialization stubs in MSVC, making us dependent on initialization
62 // 3) By not using an enum, we are possibly preventing the compiler from
63 // doing certain constant folds, which may significantly reduce the
64 // code generated for some assembly instructions (because they boil down
65 // to a few constants). If this is a problem, we could change the code
66 // such that we use an enum in optimized mode, and the struct in debug
67 // mode. This way we get the compile-time error checking in debug mode
68 // and best performance in optimized code.
71 static const int kMaxNumAllocatableRegisters = 6;
72 static int NumAllocatableRegisters() {
73 return kMaxNumAllocatableRegisters;
75 static const int kNumRegisters = 8;
77 static inline const char* AllocationIndexToString(int index);
79 static inline int ToAllocationIndex(Register reg);
81 static inline Register FromAllocationIndex(int index);
83 static Register from_code(int code) {
85 DCHECK(code < kNumRegisters);
86 Register r = { code };
89 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
90 bool is(Register reg) const { return code_ == reg.code_; }
91 // eax, ebx, ecx and edx are byte registers, the rest are not.
92 bool is_byte_register() const { return code_ <= 3; }
102 // Unfortunately we can't make this private in a struct.
106 const int kRegister_eax_Code = 0;
107 const int kRegister_ecx_Code = 1;
108 const int kRegister_edx_Code = 2;
109 const int kRegister_ebx_Code = 3;
110 const int kRegister_esp_Code = 4;
111 const int kRegister_ebp_Code = 5;
112 const int kRegister_esi_Code = 6;
113 const int kRegister_edi_Code = 7;
114 const int kRegister_no_reg_Code = -1;
116 const Register eax = { kRegister_eax_Code };
117 const Register ecx = { kRegister_ecx_Code };
118 const Register edx = { kRegister_edx_Code };
119 const Register ebx = { kRegister_ebx_Code };
120 const Register esp = { kRegister_esp_Code };
121 const Register ebp = { kRegister_ebp_Code };
122 const Register esi = { kRegister_esi_Code };
123 const Register edi = { kRegister_edi_Code };
124 const Register no_reg = { kRegister_no_reg_Code };
127 inline const char* Register::AllocationIndexToString(int index) {
128 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
129 // This is the mapping of allocation indices to registers.
130 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
131 return kNames[index];
135 inline int Register::ToAllocationIndex(Register reg) {
136 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
137 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
141 inline Register Register::FromAllocationIndex(int index) {
142 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
143 return (index >= 4) ? from_code(index + 2) : from_code(index);
148 static const int kMaxNumAllocatableRegisters = 7;
149 static const int kMaxNumRegisters = 8;
150 static int NumAllocatableRegisters() {
151 return kMaxNumAllocatableRegisters;
154 // TODO(turbofan): Proper support for float32.
155 static int NumAllocatableAliasedRegisters() {
156 return NumAllocatableRegisters();
159 static int ToAllocationIndex(XMMRegister reg) {
160 DCHECK(reg.code() != 0);
161 return reg.code() - 1;
164 static XMMRegister FromAllocationIndex(int index) {
165 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
166 return from_code(index + 1);
169 static XMMRegister from_code(int code) {
170 XMMRegister result = { code };
174 bool is_valid() const {
175 return 0 <= code_ && code_ < kMaxNumRegisters;
183 bool is(XMMRegister reg) const { return code_ == reg.code_; }
185 static const char* AllocationIndexToString(int index) {
186 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
187 const char* const names[] = {
203 typedef XMMRegister DoubleRegister;
206 const XMMRegister xmm0 = { 0 };
207 const XMMRegister xmm1 = { 1 };
208 const XMMRegister xmm2 = { 2 };
209 const XMMRegister xmm3 = { 3 };
210 const XMMRegister xmm4 = { 4 };
211 const XMMRegister xmm5 = { 5 };
212 const XMMRegister xmm6 = { 6 };
213 const XMMRegister xmm7 = { 7 };
214 const XMMRegister no_xmm_reg = { -1 };
218 // any value < 0 is considered no_condition
240 not_carry = above_equal,
242 not_zero = not_equal,
248 // Returns the equivalent of !cc.
249 // Negation of the default no_condition (-1) results in a non-default
250 // no_condition value (-2). As long as tests for no_condition check
251 // for condition < 0, this will work as expected.
252 inline Condition NegateCondition(Condition cc) {
253 return static_cast<Condition>(cc ^ 1);
257 // Commute a condition such that {a cond b == b cond' a}.
258 inline Condition CommuteCondition(Condition cc) {
275 return greater_equal;
282 // -----------------------------------------------------------------------------
283 // Machine instruction Immediates
285 class Immediate BASE_EMBEDDED {
287 inline explicit Immediate(int x);
288 inline explicit Immediate(const ExternalReference& ext);
289 inline explicit Immediate(Handle<Object> handle);
290 inline explicit Immediate(Smi* value);
291 inline explicit Immediate(Address addr);
293 static Immediate CodeRelativeOffset(Label* label) {
294 return Immediate(label);
297 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
298 bool is_int8() const {
299 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
301 bool is_int16() const {
302 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
306 inline explicit Immediate(Label* value);
309 RelocInfo::Mode rmode_;
311 friend class Operand;
312 friend class Assembler;
313 friend class MacroAssembler;
317 // -----------------------------------------------------------------------------
318 // Machine instruction Operands
325 times_int_size = times_4,
326 times_half_pointer_size = times_2,
327 times_pointer_size = times_4,
328 times_twice_pointer_size = times_8
332 class Operand BASE_EMBEDDED {
335 INLINE(explicit Operand(Register reg));
338 INLINE(explicit Operand(XMMRegister xmm_reg));
341 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
344 INLINE(explicit Operand(Immediate imm));
347 explicit Operand(Register base, int32_t disp,
348 RelocInfo::Mode rmode = RelocInfo::NONE32);
350 // [base + index*scale + disp/r]
351 explicit Operand(Register base,
355 RelocInfo::Mode rmode = RelocInfo::NONE32);
357 // [index*scale + disp/r]
358 explicit Operand(Register index,
361 RelocInfo::Mode rmode = RelocInfo::NONE32);
363 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) {
364 return Operand(index, scale, reinterpret_cast<int32_t>(table),
365 RelocInfo::INTERNAL_REFERENCE);
368 static Operand StaticVariable(const ExternalReference& ext) {
369 return Operand(reinterpret_cast<int32_t>(ext.address()),
370 RelocInfo::EXTERNAL_REFERENCE);
373 static Operand StaticArray(Register index,
375 const ExternalReference& arr) {
376 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
377 RelocInfo::EXTERNAL_REFERENCE);
380 static Operand ForCell(Handle<Cell> cell) {
381 AllowDeferredHandleDereference embedding_raw_address;
382 return Operand(reinterpret_cast<int32_t>(cell.location()),
386 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
387 return Operand(base, imm.x_, imm.rmode_);
390 // Returns true if this Operand is a wrapper for the specified register.
391 bool is_reg(Register reg) const;
393 // Returns true if this Operand is a wrapper for one register.
394 bool is_reg_only() const;
396 // Asserts that this Operand is a wrapper for one register and returns the
398 Register reg() const;
401 // Set the ModRM byte without an encoded 'reg' register. The
402 // register is encoded later as part of the emit_operand operation.
403 inline void set_modrm(int mod, Register rm);
405 inline void set_sib(ScaleFactor scale, Register index, Register base);
406 inline void set_disp8(int8_t disp);
407 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
410 // The number of bytes in buf_.
412 // Only valid if len_ > 4.
413 RelocInfo::Mode rmode_;
415 friend class Assembler;
416 friend class MacroAssembler;
420 // -----------------------------------------------------------------------------
421 // A Displacement describes the 32bit immediate field of an instruction which
422 // may be used together with a Label in order to refer to a yet unknown code
423 // position. Displacements stored in the instruction stream are used to describe
424 // the instruction and to chain a list of instructions using the same Label.
425 // A Displacement contains 2 different fields:
427 // next field: position of next displacement in the chain (0 = end of list)
428 // type field: instruction type
430 // A next value of null (0) indicates the end of a chain (note that there can
431 // be no displacement at position zero, because there is always at least one
432 // instruction byte before the displacement).
434 // Displacement _data field layout
436 // |31.....2|1......0|
439 class Displacement BASE_EMBEDDED {
441 enum Type { UNCONDITIONAL_JUMP, CODE_RELATIVE, OTHER, CODE_ABSOLUTE };
443 int data() const { return data_; }
444 Type type() const { return TypeField::decode(data_); }
445 void next(Label* L) const {
446 int n = NextField::decode(data_);
447 n > 0 ? L->link_to(n) : L->Unuse();
449 void link_to(Label* L) { init(L, type()); }
451 explicit Displacement(int data) { data_ = data; }
453 Displacement(Label* L, Type type) { init(L, type); }
456 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
457 NextField::decode(data_));
463 class TypeField: public BitField<Type, 0, 2> {};
464 class NextField: public BitField<int, 2, 32-2> {};
466 void init(Label* L, Type type);
470 class Assembler : public AssemblerBase {
472 // We check before assembling an instruction that there is sufficient
473 // space to write an instruction and its relocation information.
474 // The relocation writer's position must be kGap bytes above the end of
475 // the generated instructions. This leaves enough space for the
476 // longest possible ia32 instruction, 15 bytes, and the longest possible
477 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
478 // (There is a 15 byte limit on ia32 instruction length that rules out some
479 // otherwise valid instructions.)
480 // This allows for a single, fast space check per instruction.
481 static const int kGap = 32;
484 // Create an assembler. Instructions and relocation information are emitted
485 // into a buffer, with the instructions starting from the beginning and the
486 // relocation information starting from the end of the buffer. See CodeDesc
487 // for a detailed comment on the layout (globals.h).
489 // If the provided buffer is NULL, the assembler allocates and grows its own
490 // buffer, and buffer_size determines the initial buffer size. The buffer is
491 // owned by the assembler and deallocated upon destruction of the assembler.
493 // If the provided buffer is not NULL, the assembler uses the provided buffer
494 // for code generation and assumes its size to be buffer_size. If the buffer
495 // is too small, a fatal error occurs. No deallocation of the buffer is done
496 // upon destruction of the assembler.
497 // TODO(vitalyr): the assembler does not need an isolate.
498 Assembler(Isolate* isolate, void* buffer, int buffer_size);
499 virtual ~Assembler() { }
501 // GetCode emits any pending (non-emitted) code and fills the descriptor
502 // desc. GetCode() is idempotent; it returns the same result if no other
503 // Assembler functions are invoked in between GetCode() calls.
504 void GetCode(CodeDesc* desc);
506 // Read/Modify the code target in the branch/call instruction at pc.
507 inline static Address target_address_at(Address pc,
508 ConstantPoolArray* constant_pool);
509 inline static void set_target_address_at(Address pc,
510 ConstantPoolArray* constant_pool,
512 ICacheFlushMode icache_flush_mode =
513 FLUSH_ICACHE_IF_NEEDED);
514 static inline Address target_address_at(Address pc, Code* code) {
515 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
516 return target_address_at(pc, constant_pool);
518 static inline void set_target_address_at(Address pc,
521 ICacheFlushMode icache_flush_mode =
522 FLUSH_ICACHE_IF_NEEDED) {
523 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
524 set_target_address_at(pc, constant_pool, target);
527 // Return the code target address at a call site from the return address
528 // of that call in the instruction stream.
529 inline static Address target_address_from_return_address(Address pc);
531 // Return the code target address of the patch debug break slot
532 inline static Address break_address_from_return_address(Address pc);
534 // This sets the branch destination (which is in the instruction on x86).
535 // This is for calls and branches within generated code.
536 inline static void deserialization_set_special_target_at(
537 Address instruction_payload, Code* code, Address target) {
538 set_target_address_at(instruction_payload, code, target);
541 static const int kSpecialTargetSize = kPointerSize;
543 // Distance between the address of the code target in the call instruction
544 // and the return address
545 static const int kCallTargetAddressOffset = kPointerSize;
546 // Distance between start of patched return sequence and the emitted address
548 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
550 // Distance between start of patched debug break slot and the emitted address
552 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
554 static const int kCallInstructionLength = 5;
555 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
556 static const int kJSReturnSequenceLength = 6;
558 // The debug break slot must be able to contain a call instruction.
559 static const int kDebugBreakSlotLength = kCallInstructionLength;
561 // One byte opcode for test al, 0xXX.
562 static const byte kTestAlByte = 0xA8;
563 // One byte opcode for nop.
564 static const byte kNopByte = 0x90;
566 // One byte opcode for a short unconditional jump.
567 static const byte kJmpShortOpcode = 0xEB;
568 // One byte prefix for a short conditional jump.
569 static const byte kJccShortPrefix = 0x70;
570 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
571 static const byte kJcShortOpcode = kJccShortPrefix | carry;
572 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
573 static const byte kJzShortOpcode = kJccShortPrefix | zero;
576 // ---------------------------------------------------------------------------
579 // - function names correspond one-to-one to ia32 instruction mnemonics
580 // - unless specified otherwise, instructions operate on 32bit operands
581 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
582 // - instructions on 16bit (word) operands/registers have a trailing '_w'
583 // - naming conflicts with C++ keywords are resolved via a trailing '_'
585 // NOTE ON INTERFACE: Currently, the interface is not very consistent
586 // in the sense that some operations (e.g. mov()) can be called in more
587 // the one way to generate the same instruction: The Register argument
588 // can in some cases be replaced with an Operand(Register) argument.
589 // This should be cleaned up and made more orthogonal. The questions
590 // is: should we always use Operands instead of Registers where an
591 // Operand is possible, or should we have a Register (overloaded) form
592 // instead? We must be careful to make sure that the selected instruction
593 // is obvious from the parameters to avoid hard-to-find code generation
596 // Insert the smallest number of nop instructions
597 // possible to align the pc offset to a multiple
598 // of m. m must be a power of 2.
600 void Nop(int bytes = 1);
601 // Aligns code to something that's optimal for a jump target for the platform.
602 void CodeTargetAlign();
611 void push(const Immediate& x);
612 void push_imm32(int32_t imm32);
613 void push(Register src);
614 void push(const Operand& src);
616 void pop(Register dst);
617 void pop(const Operand& dst);
619 void enter(const Immediate& size);
623 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
624 void mov_b(Register dst, const Operand& src);
625 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
626 void mov_b(const Operand& dst, int8_t src) { mov_b(dst, Immediate(src)); }
627 void mov_b(const Operand& dst, const Immediate& src);
628 void mov_b(const Operand& dst, Register src);
630 void mov_w(Register dst, const Operand& src);
631 void mov_w(const Operand& dst, int16_t src) { mov_w(dst, Immediate(src)); }
632 void mov_w(const Operand& dst, const Immediate& src);
633 void mov_w(const Operand& dst, Register src);
635 void mov(Register dst, int32_t imm32);
636 void mov(Register dst, const Immediate& x);
637 void mov(Register dst, Handle<Object> handle);
638 void mov(Register dst, const Operand& src);
639 void mov(Register dst, Register src);
640 void mov(const Operand& dst, const Immediate& x);
641 void mov(const Operand& dst, Handle<Object> handle);
642 void mov(const Operand& dst, Register src);
644 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
645 void movsx_b(Register dst, const Operand& src);
647 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
648 void movsx_w(Register dst, const Operand& src);
650 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
651 void movzx_b(Register dst, const Operand& src);
653 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
654 void movzx_w(Register dst, const Operand& src);
657 void cmov(Condition cc, Register dst, Register src) {
658 cmov(cc, dst, Operand(src));
660 void cmov(Condition cc, Register dst, const Operand& src);
665 // Repetitive string instructions.
671 void xchg(Register dst, Register src);
672 void xchg(Register dst, const Operand& src);
675 void adc(Register dst, int32_t imm32);
676 void adc(Register dst, const Operand& src);
678 void add(Register dst, Register src) { add(dst, Operand(src)); }
679 void add(Register dst, const Operand& src);
680 void add(const Operand& dst, Register src);
681 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
682 void add(const Operand& dst, const Immediate& x);
684 void and_(Register dst, int32_t imm32);
685 void and_(Register dst, const Immediate& x);
686 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
687 void and_(Register dst, const Operand& src);
688 void and_(const Operand& dst, Register src);
689 void and_(const Operand& dst, const Immediate& x);
691 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
692 void cmpb(const Operand& op, int8_t imm8);
693 void cmpb(Register reg, const Operand& op);
694 void cmpb(const Operand& op, Register reg);
695 void cmpb_al(const Operand& op);
696 void cmpw_ax(const Operand& op);
697 void cmpw(const Operand& op, Immediate imm16);
698 void cmp(Register reg, int32_t imm32);
699 void cmp(Register reg, Handle<Object> handle);
700 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
701 void cmp(Register reg, const Operand& op);
702 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
703 void cmp(const Operand& op, const Immediate& imm);
704 void cmp(const Operand& op, Handle<Object> handle);
706 void dec_b(Register dst);
707 void dec_b(const Operand& dst);
709 void dec(Register dst);
710 void dec(const Operand& dst);
714 void idiv(Register src) { idiv(Operand(src)); }
715 void idiv(const Operand& src);
716 void div(Register src) { div(Operand(src)); }
717 void div(const Operand& src);
719 // Signed multiply instructions.
720 void imul(Register src); // edx:eax = eax * src.
721 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
722 void imul(Register dst, const Operand& src); // dst = dst * src.
723 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
724 void imul(Register dst, const Operand& src, int32_t imm32);
726 void inc(Register dst);
727 void inc(const Operand& dst);
729 void lea(Register dst, const Operand& src);
731 // Unsigned multiply instruction.
732 void mul(Register src); // edx:eax = eax * reg.
734 void neg(Register dst);
735 void neg(const Operand& dst);
737 void not_(Register dst);
738 void not_(const Operand& dst);
740 void or_(Register dst, int32_t imm32);
741 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
742 void or_(Register dst, const Operand& src);
743 void or_(const Operand& dst, Register src);
744 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
745 void or_(const Operand& dst, const Immediate& x);
747 void rcl(Register dst, uint8_t imm8);
748 void rcr(Register dst, uint8_t imm8);
750 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
751 void ror(const Operand& dst, uint8_t imm8);
752 void ror_cl(Register dst) { ror_cl(Operand(dst)); }
753 void ror_cl(const Operand& dst);
755 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
756 void sar(const Operand& dst, uint8_t imm8);
757 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
758 void sar_cl(const Operand& dst);
760 void sbb(Register dst, const Operand& src);
762 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
763 void shld(Register dst, const Operand& src);
765 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
766 void shl(const Operand& dst, uint8_t imm8);
767 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
768 void shl_cl(const Operand& dst);
770 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
771 void shrd(Register dst, const Operand& src);
773 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
774 void shr(const Operand& dst, uint8_t imm8);
775 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
776 void shr_cl(const Operand& dst);
778 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
779 void sub(const Operand& dst, const Immediate& x);
780 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
781 void sub(Register dst, const Operand& src);
782 void sub(const Operand& dst, Register src);
784 void test(Register reg, const Immediate& imm);
785 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
786 void test(Register reg, const Operand& op);
787 void test_b(Register reg, const Operand& op);
788 void test(const Operand& op, const Immediate& imm);
789 void test_b(Register reg, uint8_t imm8);
790 void test_b(const Operand& op, uint8_t imm8);
792 void xor_(Register dst, int32_t imm32);
793 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
794 void xor_(Register dst, const Operand& src);
795 void xor_(const Operand& dst, Register src);
796 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
797 void xor_(const Operand& dst, const Immediate& x);
800 void bt(const Operand& dst, Register src);
801 void bts(Register dst, Register src) { bts(Operand(dst), src); }
802 void bts(const Operand& dst, Register src);
803 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
804 void bsr(Register dst, const Operand& src);
813 // Label operations & relative jumps (PPUM Appendix D)
815 // Takes a branch opcode (cc) and a label (L) and generates
816 // either a backward branch or a forward branch and links it
817 // to the label fixup chain. Usage:
819 // Label L; // unbound label
820 // j(cc, &L); // forward branch to unbound label
821 // bind(&L); // bind label to the current pc
822 // j(cc, &L); // backward branch to bound label
823 // bind(&L); // illegal: a label may be bound only once
825 // Note: The same Label can be used for forward and backward branches
826 // but it may be bound only once.
828 void bind(Label* L); // binds an unbound label L to the current code position
832 void call(byte* entry, RelocInfo::Mode rmode);
833 int CallSize(const Operand& adr);
834 void call(Register reg) { call(Operand(reg)); }
835 void call(const Operand& adr);
836 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
837 void call(Handle<Code> code,
838 RelocInfo::Mode rmode,
839 TypeFeedbackId id = TypeFeedbackId::None());
842 // unconditional jump to L
843 void jmp(Label* L, Label::Distance distance = Label::kFar);
844 void jmp(byte* entry, RelocInfo::Mode rmode);
845 void jmp(Register reg) { jmp(Operand(reg)); }
846 void jmp(const Operand& adr);
847 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
852 Label::Distance distance = Label::kFar);
853 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
854 void j(Condition cc, Handle<Code> code);
856 // Floating-point operations
865 void fld_s(const Operand& adr);
866 void fld_d(const Operand& adr);
868 void fstp_s(const Operand& adr);
869 void fst_s(const Operand& adr);
870 void fstp_d(const Operand& adr);
871 void fst_d(const Operand& adr);
873 void fild_s(const Operand& adr);
874 void fild_d(const Operand& adr);
876 void fist_s(const Operand& adr);
878 void fistp_s(const Operand& adr);
879 void fistp_d(const Operand& adr);
881 // The fisttp instructions require SSE3.
882 void fisttp_s(const Operand& adr);
883 void fisttp_d(const Operand& adr);
904 void fisub_s(const Operand& adr);
906 void faddp(int i = 1);
907 void fsubp(int i = 1);
908 void fsubrp(int i = 1);
909 void fmulp(int i = 1);
910 void fdivp(int i = 1);
914 void fxch(int i = 1);
916 void ffree(int i = 0);
931 void setcc(Condition cc, Register reg);
936 void addss(XMMRegister dst, XMMRegister src) { addss(dst, Operand(src)); }
937 void addss(XMMRegister dst, const Operand& src);
938 void subss(XMMRegister dst, XMMRegister src) { subss(dst, Operand(src)); }
939 void subss(XMMRegister dst, const Operand& src);
940 void mulss(XMMRegister dst, XMMRegister src) { mulss(dst, Operand(src)); }
941 void mulss(XMMRegister dst, const Operand& src);
942 void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); }
943 void divss(XMMRegister dst, const Operand& src);
945 void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); }
946 void ucomiss(XMMRegister dst, const Operand& src);
947 void movaps(XMMRegister dst, XMMRegister src);
948 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
950 void andps(XMMRegister dst, const Operand& src);
951 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
952 void xorps(XMMRegister dst, const Operand& src);
953 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
954 void orps(XMMRegister dst, const Operand& src);
955 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
957 void addps(XMMRegister dst, const Operand& src);
958 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
959 void subps(XMMRegister dst, const Operand& src);
960 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
961 void mulps(XMMRegister dst, const Operand& src);
962 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
963 void divps(XMMRegister dst, const Operand& src);
964 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
967 void cvttss2si(Register dst, const Operand& src);
968 void cvttss2si(Register dst, XMMRegister src) {
969 cvttss2si(dst, Operand(src));
971 void cvttsd2si(Register dst, const Operand& src);
972 void cvttsd2si(Register dst, XMMRegister src) {
973 cvttsd2si(dst, Operand(src));
975 void cvtsd2si(Register dst, XMMRegister src);
977 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
978 void cvtsi2sd(XMMRegister dst, const Operand& src);
979 void cvtss2sd(XMMRegister dst, const Operand& src);
980 void cvtss2sd(XMMRegister dst, XMMRegister src) {
981 cvtss2sd(dst, Operand(src));
983 void cvtsd2ss(XMMRegister dst, const Operand& src);
984 void cvtsd2ss(XMMRegister dst, XMMRegister src) {
985 cvtsd2ss(dst, Operand(src));
987 void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
988 void addsd(XMMRegister dst, const Operand& src);
989 void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
990 void subsd(XMMRegister dst, const Operand& src);
991 void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); }
992 void mulsd(XMMRegister dst, const Operand& src);
993 void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
994 void divsd(XMMRegister dst, const Operand& src);
995 void xorpd(XMMRegister dst, XMMRegister src);
996 void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
997 void sqrtsd(XMMRegister dst, const Operand& src);
999 void andpd(XMMRegister dst, XMMRegister src);
1000 void orpd(XMMRegister dst, XMMRegister src);
1002 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1003 void ucomisd(XMMRegister dst, const Operand& src);
1006 kRoundToNearest = 0x0,
1012 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1014 void movmskpd(Register dst, XMMRegister src);
1015 void movmskps(Register dst, XMMRegister src);
1017 void cmpltsd(XMMRegister dst, XMMRegister src);
1018 void pcmpeqd(XMMRegister dst, XMMRegister src);
1020 void movdqa(XMMRegister dst, const Operand& src);
1021 void movdqa(const Operand& dst, XMMRegister src);
1022 void movdqu(XMMRegister dst, const Operand& src);
1023 void movdqu(const Operand& dst, XMMRegister src);
1024 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1032 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1033 void movd(XMMRegister dst, const Operand& src);
1034 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1035 void movd(const Operand& dst, XMMRegister src);
1036 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1037 void movsd(XMMRegister dst, const Operand& src);
1038 void movsd(const Operand& dst, XMMRegister src);
1041 void movss(XMMRegister dst, const Operand& src);
1042 void movss(const Operand& dst, XMMRegister src);
1043 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1044 void extractps(Register dst, XMMRegister src, byte imm8);
1046 void pand(XMMRegister dst, XMMRegister src);
1047 void pxor(XMMRegister dst, XMMRegister src);
1048 void por(XMMRegister dst, XMMRegister src);
1049 void ptest(XMMRegister dst, XMMRegister src);
1051 void pslld(XMMRegister reg, int8_t shift);
1052 void psrld(XMMRegister reg, int8_t shift);
1053 void psllq(XMMRegister reg, int8_t shift);
1054 void psllq(XMMRegister dst, XMMRegister src);
1055 void psrlq(XMMRegister reg, int8_t shift);
1056 void psrlq(XMMRegister dst, XMMRegister src);
1057 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1058 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1059 pextrd(Operand(dst), src, offset);
1061 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1062 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1063 pinsrd(dst, Operand(src), offset);
1065 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1067 // Parallel XMM operations.
1068 void movntdqa(XMMRegister dst, const Operand& src);
1069 void movntdq(const Operand& dst, XMMRegister src);
1072 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1073 vfmadd132sd(dst, src1, Operand(src2));
1075 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1076 vfmadd213sd(dst, src1, Operand(src2));
1078 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1079 vfmadd231sd(dst, src1, Operand(src2));
1081 void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1082 vfmasd(0x99, dst, src1, src2);
1084 void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1085 vfmasd(0xa9, dst, src1, src2);
1087 void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1088 vfmasd(0xb9, dst, src1, src2);
1090 void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1091 vfmsub132sd(dst, src1, Operand(src2));
1093 void vfmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1094 vfmsub213sd(dst, src1, Operand(src2));
1096 void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1097 vfmsub231sd(dst, src1, Operand(src2));
1099 void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1100 vfmasd(0x9b, dst, src1, src2);
1102 void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1103 vfmasd(0xab, dst, src1, src2);
1105 void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1106 vfmasd(0xbb, dst, src1, src2);
1108 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1109 vfnmadd132sd(dst, src1, Operand(src2));
1111 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1112 vfnmadd213sd(dst, src1, Operand(src2));
1114 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1115 vfnmadd231sd(dst, src1, Operand(src2));
1117 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1118 vfmasd(0x9d, dst, src1, src2);
1120 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1121 vfmasd(0xad, dst, src1, src2);
1123 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1124 vfmasd(0xbd, dst, src1, src2);
1126 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1127 vfnmsub132sd(dst, src1, Operand(src2));
1129 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1130 vfnmsub213sd(dst, src1, Operand(src2));
1132 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1133 vfnmsub231sd(dst, src1, Operand(src2));
1135 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1136 vfmasd(0x9f, dst, src1, src2);
1138 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1139 vfmasd(0xaf, dst, src1, src2);
1141 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1142 vfmasd(0xbf, dst, src1, src2);
1144 void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1146 void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1147 vfmadd132ss(dst, src1, Operand(src2));
1149 void vfmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1150 vfmadd213ss(dst, src1, Operand(src2));
1152 void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1153 vfmadd231ss(dst, src1, Operand(src2));
1155 void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1156 vfmass(0x99, dst, src1, src2);
1158 void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1159 vfmass(0xa9, dst, src1, src2);
1161 void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1162 vfmass(0xb9, dst, src1, src2);
1164 void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1165 vfmsub132ss(dst, src1, Operand(src2));
1167 void vfmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1168 vfmsub213ss(dst, src1, Operand(src2));
1170 void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1171 vfmsub231ss(dst, src1, Operand(src2));
1173 void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1174 vfmass(0x9b, dst, src1, src2);
1176 void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1177 vfmass(0xab, dst, src1, src2);
1179 void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1180 vfmass(0xbb, dst, src1, src2);
1182 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1183 vfnmadd132ss(dst, src1, Operand(src2));
1185 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1186 vfnmadd213ss(dst, src1, Operand(src2));
1188 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1189 vfnmadd231ss(dst, src1, Operand(src2));
1191 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1192 vfmass(0x9d, dst, src1, src2);
1194 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1195 vfmass(0xad, dst, src1, src2);
1197 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1198 vfmass(0xbd, dst, src1, src2);
1200 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1201 vfnmsub132ss(dst, src1, Operand(src2));
1203 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1204 vfnmsub213ss(dst, src1, Operand(src2));
1206 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1207 vfnmsub231ss(dst, src1, Operand(src2));
1209 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1210 vfmass(0x9f, dst, src1, src2);
1212 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1213 vfmass(0xaf, dst, src1, src2);
1215 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1216 vfmass(0xbf, dst, src1, src2);
1218 void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1220 void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1221 vaddsd(dst, src1, Operand(src2));
1223 void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1224 vsd(0x58, dst, src1, src2);
1226 void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1227 vsubsd(dst, src1, Operand(src2));
1229 void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1230 vsd(0x5c, dst, src1, src2);
1232 void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1233 vmulsd(dst, src1, Operand(src2));
1235 void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1236 vsd(0x59, dst, src1, src2);
1238 void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1239 vdivsd(dst, src1, Operand(src2));
1241 void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
1242 vsd(0x5e, dst, src1, src2);
1244 void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
1246 // Prefetch src position into cache level.
1247 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1249 void prefetch(const Operand& src, int level);
1250 // TODO(lrn): Need SFENCE for movnt?
1252 // Check the code size generated from label to here.
1253 int SizeOfCodeGeneratedSince(Label* label) {
1254 return pc_offset() - label->pos();
1257 // Mark address of the ExitJSFrame code.
1258 void RecordJSReturn();
1260 // Mark address of a debug break slot.
1261 void RecordDebugBreakSlot();
1263 // Record a comment relocation entry that can be used by a disassembler.
1264 // Use --code-comments to enable.
1265 void RecordComment(const char* msg);
1267 // Record a deoptimization reason that can be used by a log or cpu profiler.
1268 // Use --trace-deopt to enable.
1269 void RecordDeoptReason(const int reason, const int raw_position);
1271 // Writes a single byte or word of data in the code stream. Used for
1272 // inline tables, e.g., jump-tables.
1273 void db(uint8_t data);
1274 void dd(uint32_t data);
1275 void dd(Label* label);
1277 // Check if there is less than kGap bytes available in the buffer.
1278 // If this is the case, we need to grow the buffer before emitting
1279 // an instruction or relocation information.
1280 inline bool buffer_overflow() const {
1281 return pc_ >= reloc_info_writer.pos() - kGap;
1284 // Get the number of bytes available in the buffer.
1285 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1287 static bool IsNop(Address addr);
1289 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1291 int relocation_writer_size() {
1292 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1295 // Avoid overflows for displacements etc.
1296 static const int kMaximalBufferSize = 512*MB;
1298 byte byte_at(int pos) { return buffer_[pos]; }
1299 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1301 // Allocate a constant pool of the correct size for the generated code.
1302 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1304 // Generate the constant pool for the generated code.
1305 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1308 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1309 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1310 void emit_sse_operand(Register dst, XMMRegister src);
1311 void emit_sse_operand(XMMRegister dst, Register src);
1313 byte* addr_at(int pos) { return buffer_ + pos; }
1317 uint32_t long_at(int pos) {
1318 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1320 void long_at_put(int pos, uint32_t x) {
1321 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1326 inline void emit(uint32_t x);
1327 inline void emit(Handle<Object> handle);
1328 inline void emit(uint32_t x,
1329 RelocInfo::Mode rmode,
1330 TypeFeedbackId id = TypeFeedbackId::None());
1331 inline void emit(Handle<Code> code,
1332 RelocInfo::Mode rmode,
1333 TypeFeedbackId id = TypeFeedbackId::None());
1334 inline void emit(const Immediate& x);
1335 inline void emit_w(const Immediate& x);
1337 // Emit the code-object-relative offset of the label's position
1338 inline void emit_code_relative_offset(Label* label);
1340 // instruction generation
1341 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1343 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1344 // with a given destination expression and an immediate operand. It attempts
1345 // to use the shortest encoding possible.
1346 // sel specifies the /n in the modrm byte (see the Intel PRM).
1347 void emit_arith(int sel, Operand dst, const Immediate& x);
1349 void emit_operand(Register reg, const Operand& adr);
1351 void emit_label(Label* label);
1353 void emit_farith(int b1, int b2, int i);
1356 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 };
1357 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128 };
1358 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 };
1359 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x2 };
1360 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp,
1361 LeadingOpcode m, VexW w);
1364 void print(Label* L);
1365 void bind_to(Label* L, int pos);
1368 inline Displacement disp_at(Label* L);
1369 inline void disp_at_put(Label* L, Displacement disp);
1370 inline void emit_disp(Label* L, Displacement::Type type);
1371 inline void emit_near_disp(Label* L);
1373 // record reloc info for current pc_
1374 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1376 friend class CodePatcher;
1377 friend class EnsureSpace;
1379 // Internal reference positions, required for (potential) patching in
1380 // GrowBuffer(); contains only those internal references whose labels
1381 // are already bound.
1382 std::deque<int> internal_reference_positions_;
1385 RelocInfoWriter reloc_info_writer;
1387 PositionsRecorder positions_recorder_;
1388 friend class PositionsRecorder;
1392 // Helper class that ensures that there is enough space for generating
1393 // instructions and relocation information. The constructor makes
1394 // sure that there is enough space and (in debug mode) the destructor
1395 // checks that we did not generate too much.
1396 class EnsureSpace BASE_EMBEDDED {
1398 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1399 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1401 space_before_ = assembler_->available_space();
1407 int bytes_generated = space_before_ - assembler_->available_space();
1408 DCHECK(bytes_generated < assembler_->kGap);
1413 Assembler* assembler_;
1419 } } // namespace v8::internal
1421 #endif // V8_IA32_ASSEMBLER_IA32_H_