1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
37 #include "src/ia32/assembler-ia32.h"
41 #if V8_TARGET_ARCH_IA32
44 #include <intrin.h> // _xgetbv()
47 #include <sys/sysctl.h>
50 #include "src/base/bits.h"
51 #include "src/base/cpu.h"
52 #include "src/disassembler.h"
53 #include "src/macro-assembler.h"
59 // -----------------------------------------------------------------------------
60 // Implementation of CpuFeatures
66 V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
68 // Check xgetbv; this uses a .byte sequence instead of the instruction
69 // directly because older assemblers do not include support for xgetbv and
70 // there is no easy way to conditionally compile based on the assembler
72 __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
73 return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
76 #define _XCR_XFEATURE_ENABLED_MASK 0
78 #endif // !V8_LIBC_MSVCRT
81 bool OSHasAVXSupport() {
83 // Mac OS X up to 10.9 has a bug where AVX transitions were indeed being
84 // caused by ISRs, so we detect that here and disable AVX in that case.
86 size_t buffer_size = arraysize(buffer);
87 int ctl_name[] = {CTL_KERN, KERN_OSRELEASE};
88 if (sysctl(ctl_name, 2, buffer, &buffer_size, nullptr, 0) != 0) {
89 V8_Fatal(__FILE__, __LINE__, "V8 failed to get kernel version");
91 // The buffer now contains a string of the form XX.YY.ZZ, where
92 // XX is the major kernel version component.
93 char* period_pos = strchr(buffer, '.');
94 DCHECK_NOT_NULL(period_pos);
96 long kernel_version_major = strtol(buffer, nullptr, 10); // NOLINT
97 if (kernel_version_major <= 13) return false;
98 #endif // V8_OS_MACOSX
99 // Check whether OS claims to support AVX.
100 uint64_t feature_mask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
101 return (feature_mask & 0x6) == 0x6;
107 void CpuFeatures::ProbeImpl(bool cross_compile) {
109 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
110 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
112 // Only use statically determined features for cross compile (snapshot).
113 if (cross_compile) return;
115 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
116 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
117 if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
119 supported_ |= 1u << AVX;
121 if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
123 supported_ |= 1u << FMA3;
125 if (strcmp(FLAG_mcpu, "auto") == 0) {
126 if (cpu.is_atom()) supported_ |= 1u << ATOM;
127 } else if (strcmp(FLAG_mcpu, "atom") == 0) {
128 supported_ |= 1u << ATOM;
133 void CpuFeatures::PrintTarget() { }
134 void CpuFeatures::PrintFeatures() {
135 printf("SSE3=%d SSE4_1=%d AVX=%d FMA3=%d ATOM=%d\n",
136 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
137 CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
138 CpuFeatures::IsSupported(ATOM));
142 // -----------------------------------------------------------------------------
143 // Implementation of Displacement
145 void Displacement::init(Label* L, Type type) {
146 DCHECK(!L->is_bound());
148 if (L->is_linked()) {
150 DCHECK(next > 0); // Displacements must be at positions > 0
152 // Ensure that we _never_ overflow the next field.
153 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
154 data_ = NextField::encode(next) | TypeField::encode(type);
158 // -----------------------------------------------------------------------------
159 // Implementation of RelocInfo
162 const int RelocInfo::kApplyMask =
163 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
164 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
165 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
168 bool RelocInfo::IsCodedSpecially() {
169 // The deserializer needs to know whether a pointer is specially coded. Being
170 // specially coded on IA32 means that it is a relative address, as used by
171 // branch instructions. These are also the ones that need changing when a
172 // code object moves.
173 return (1 << rmode_) & kApplyMask;
177 bool RelocInfo::IsInConstantPool() {
182 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
183 // Patch the code at the current address with the supplied instructions.
184 for (int i = 0; i < instruction_count; i++) {
185 *(pc_ + i) = *(instructions + i);
188 // Indicate that code has changed.
189 CpuFeatures::FlushICache(pc_, instruction_count);
193 // Patch the code at the current PC with a call to the target address.
194 // Additional guard int3 instructions can be added if required.
195 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
196 // Call instruction takes up 5 bytes and int3 takes up one byte.
197 static const int kCallCodeSize = 5;
198 int code_size = kCallCodeSize + guard_bytes;
200 // Create a code patcher.
201 CodePatcher patcher(pc_, code_size);
203 // Add a label for checking the size of the code used for returning.
205 Label check_codesize;
206 patcher.masm()->bind(&check_codesize);
210 patcher.masm()->call(target, RelocInfo::NONE32);
212 // Check that the size of the code generated is as expected.
213 DCHECK_EQ(kCallCodeSize,
214 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
216 // Add the requested number of int3 instructions after the call.
217 DCHECK_GE(guard_bytes, 0);
218 for (int i = 0; i < guard_bytes; i++) {
219 patcher.masm()->int3();
224 // -----------------------------------------------------------------------------
225 // Implementation of Operand
227 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
229 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
232 if (base.is(esp)) set_sib(times_1, esp, base);
233 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
236 if (base.is(esp)) set_sib(times_1, esp, base);
241 if (base.is(esp)) set_sib(times_1, esp, base);
242 set_dispr(disp, rmode);
247 Operand::Operand(Register base,
251 RelocInfo::Mode rmode) {
252 DCHECK(!index.is(esp)); // illegal addressing mode
253 // [base + index*scale + disp/r]
254 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
255 // [base + index*scale]
257 set_sib(scale, index, base);
258 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
259 // [base + index*scale + disp8]
261 set_sib(scale, index, base);
264 // [base + index*scale + disp/r]
266 set_sib(scale, index, base);
267 set_dispr(disp, rmode);
272 Operand::Operand(Register index,
275 RelocInfo::Mode rmode) {
276 DCHECK(!index.is(esp)); // illegal addressing mode
277 // [index*scale + disp/r]
279 set_sib(scale, index, ebp);
280 set_dispr(disp, rmode);
284 bool Operand::is_reg(Register reg) const {
285 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
286 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
290 bool Operand::is_reg_only() const {
291 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
295 Register Operand::reg() const {
296 DCHECK(is_reg_only());
297 return Register::from_code(buf_[0] & 0x07);
301 // -----------------------------------------------------------------------------
302 // Implementation of Assembler.
304 // Emit a single byte. Must always be inlined.
309 #ifdef GENERATED_CODE_COVERAGE
310 static void InitCoverageLog();
313 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
314 : AssemblerBase(isolate, buffer, buffer_size),
315 positions_recorder_(this) {
316 // Clear the buffer in debug mode unless it was provided by the
317 // caller in which case we can't be sure it's okay to overwrite
318 // existing code in it; see CodePatcher::CodePatcher(...).
321 memset(buffer_, 0xCC, buffer_size_); // int3
325 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
327 #ifdef GENERATED_CODE_COVERAGE
333 void Assembler::GetCode(CodeDesc* desc) {
334 // Finalize code (at this point overflow() may be true, but the gap ensures
335 // that we are still not overlapping instructions and relocation info).
336 reloc_info_writer.Finish();
337 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
338 // Set up code descriptor.
339 desc->buffer = buffer_;
340 desc->buffer_size = buffer_size_;
341 desc->instr_size = pc_offset();
342 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
347 void Assembler::Align(int m) {
348 DCHECK(base::bits::IsPowerOfTwo32(m));
350 int addr = pc_offset();
351 Nop((m - (addr & mask)) & mask);
355 bool Assembler::IsNop(Address addr) {
357 while (*a == 0x66) a++;
358 if (*a == 0x90) return true;
359 if (a[0] == 0xf && a[1] == 0x1f) return true;
364 void Assembler::Nop(int bytes) {
365 EnsureSpace ensure_space(this);
367 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
429 void Assembler::CodeTargetAlign() {
430 Align(16); // Preferred alignment of jump targets on ia32.
434 void Assembler::cpuid() {
435 EnsureSpace ensure_space(this);
441 void Assembler::pushad() {
442 EnsureSpace ensure_space(this);
447 void Assembler::popad() {
448 EnsureSpace ensure_space(this);
453 void Assembler::pushfd() {
454 EnsureSpace ensure_space(this);
459 void Assembler::popfd() {
460 EnsureSpace ensure_space(this);
465 void Assembler::push(const Immediate& x) {
466 EnsureSpace ensure_space(this);
477 void Assembler::push_imm32(int32_t imm32) {
478 EnsureSpace ensure_space(this);
484 void Assembler::push(Register src) {
485 EnsureSpace ensure_space(this);
486 EMIT(0x50 | src.code());
490 void Assembler::push(const Operand& src) {
491 EnsureSpace ensure_space(this);
493 emit_operand(esi, src);
497 void Assembler::pop(Register dst) {
498 DCHECK(reloc_info_writer.last_pc() != NULL);
499 EnsureSpace ensure_space(this);
500 EMIT(0x58 | dst.code());
504 void Assembler::pop(const Operand& dst) {
505 EnsureSpace ensure_space(this);
507 emit_operand(eax, dst);
511 void Assembler::enter(const Immediate& size) {
512 EnsureSpace ensure_space(this);
519 void Assembler::leave() {
520 EnsureSpace ensure_space(this);
525 void Assembler::mov_b(Register dst, const Operand& src) {
526 CHECK(dst.is_byte_register());
527 EnsureSpace ensure_space(this);
529 emit_operand(dst, src);
533 void Assembler::mov_b(const Operand& dst, const Immediate& src) {
534 EnsureSpace ensure_space(this);
536 emit_operand(eax, dst);
537 EMIT(static_cast<int8_t>(src.x_));
541 void Assembler::mov_b(const Operand& dst, Register src) {
542 CHECK(src.is_byte_register());
543 EnsureSpace ensure_space(this);
545 emit_operand(src, dst);
549 void Assembler::mov_w(Register dst, const Operand& src) {
550 EnsureSpace ensure_space(this);
553 emit_operand(dst, src);
557 void Assembler::mov_w(const Operand& dst, Register src) {
558 EnsureSpace ensure_space(this);
561 emit_operand(src, dst);
565 void Assembler::mov_w(const Operand& dst, const Immediate& src) {
566 EnsureSpace ensure_space(this);
569 emit_operand(eax, dst);
570 EMIT(static_cast<int8_t>(src.x_ & 0xff));
571 EMIT(static_cast<int8_t>(src.x_ >> 8));
575 void Assembler::mov(Register dst, int32_t imm32) {
576 EnsureSpace ensure_space(this);
577 EMIT(0xB8 | dst.code());
582 void Assembler::mov(Register dst, const Immediate& x) {
583 EnsureSpace ensure_space(this);
584 EMIT(0xB8 | dst.code());
589 void Assembler::mov(Register dst, Handle<Object> handle) {
590 EnsureSpace ensure_space(this);
591 EMIT(0xB8 | dst.code());
596 void Assembler::mov(Register dst, const Operand& src) {
597 EnsureSpace ensure_space(this);
599 emit_operand(dst, src);
603 void Assembler::mov(Register dst, Register src) {
604 EnsureSpace ensure_space(this);
606 EMIT(0xC0 | src.code() << 3 | dst.code());
610 void Assembler::mov(const Operand& dst, const Immediate& x) {
611 EnsureSpace ensure_space(this);
613 emit_operand(eax, dst);
618 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
619 EnsureSpace ensure_space(this);
621 emit_operand(eax, dst);
626 void Assembler::mov(const Operand& dst, Register src) {
627 EnsureSpace ensure_space(this);
629 emit_operand(src, dst);
633 void Assembler::movsx_b(Register dst, const Operand& src) {
634 EnsureSpace ensure_space(this);
637 emit_operand(dst, src);
641 void Assembler::movsx_w(Register dst, const Operand& src) {
642 EnsureSpace ensure_space(this);
645 emit_operand(dst, src);
649 void Assembler::movzx_b(Register dst, const Operand& src) {
650 EnsureSpace ensure_space(this);
653 emit_operand(dst, src);
657 void Assembler::movzx_w(Register dst, const Operand& src) {
658 EnsureSpace ensure_space(this);
661 emit_operand(dst, src);
665 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
666 EnsureSpace ensure_space(this);
667 // Opcode: 0f 40 + cc /r.
670 emit_operand(dst, src);
674 void Assembler::cld() {
675 EnsureSpace ensure_space(this);
680 void Assembler::rep_movs() {
681 EnsureSpace ensure_space(this);
687 void Assembler::rep_stos() {
688 EnsureSpace ensure_space(this);
694 void Assembler::stos() {
695 EnsureSpace ensure_space(this);
700 void Assembler::xchg(Register dst, Register src) {
701 EnsureSpace ensure_space(this);
702 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
703 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
706 EMIT(0xC0 | src.code() << 3 | dst.code());
711 void Assembler::xchg(Register dst, const Operand& src) {
712 EnsureSpace ensure_space(this);
714 emit_operand(dst, src);
718 void Assembler::adc(Register dst, int32_t imm32) {
719 EnsureSpace ensure_space(this);
720 emit_arith(2, Operand(dst), Immediate(imm32));
724 void Assembler::adc(Register dst, const Operand& src) {
725 EnsureSpace ensure_space(this);
727 emit_operand(dst, src);
731 void Assembler::add(Register dst, const Operand& src) {
732 EnsureSpace ensure_space(this);
734 emit_operand(dst, src);
738 void Assembler::add(const Operand& dst, Register src) {
739 EnsureSpace ensure_space(this);
741 emit_operand(src, dst);
745 void Assembler::add(const Operand& dst, const Immediate& x) {
746 DCHECK(reloc_info_writer.last_pc() != NULL);
747 EnsureSpace ensure_space(this);
748 emit_arith(0, dst, x);
752 void Assembler::and_(Register dst, int32_t imm32) {
753 and_(dst, Immediate(imm32));
757 void Assembler::and_(Register dst, const Immediate& x) {
758 EnsureSpace ensure_space(this);
759 emit_arith(4, Operand(dst), x);
763 void Assembler::and_(Register dst, const Operand& src) {
764 EnsureSpace ensure_space(this);
766 emit_operand(dst, src);
770 void Assembler::and_(const Operand& dst, const Immediate& x) {
771 EnsureSpace ensure_space(this);
772 emit_arith(4, dst, x);
776 void Assembler::and_(const Operand& dst, Register src) {
777 EnsureSpace ensure_space(this);
779 emit_operand(src, dst);
783 void Assembler::cmpb(const Operand& op, int8_t imm8) {
784 EnsureSpace ensure_space(this);
785 if (op.is_reg(eax)) {
789 emit_operand(edi, op); // edi == 7
795 void Assembler::cmpb(const Operand& op, Register reg) {
796 CHECK(reg.is_byte_register());
797 EnsureSpace ensure_space(this);
799 emit_operand(reg, op);
803 void Assembler::cmpb(Register reg, const Operand& op) {
804 CHECK(reg.is_byte_register());
805 EnsureSpace ensure_space(this);
807 emit_operand(reg, op);
811 void Assembler::cmpw(const Operand& op, Immediate imm16) {
812 DCHECK(imm16.is_int16());
813 EnsureSpace ensure_space(this);
816 emit_operand(edi, op);
821 void Assembler::cmp(Register reg, int32_t imm32) {
822 EnsureSpace ensure_space(this);
823 emit_arith(7, Operand(reg), Immediate(imm32));
827 void Assembler::cmp(Register reg, Handle<Object> handle) {
828 EnsureSpace ensure_space(this);
829 emit_arith(7, Operand(reg), Immediate(handle));
833 void Assembler::cmp(Register reg, const Operand& op) {
834 EnsureSpace ensure_space(this);
836 emit_operand(reg, op);
840 void Assembler::cmp(const Operand& op, const Immediate& imm) {
841 EnsureSpace ensure_space(this);
842 emit_arith(7, op, imm);
846 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
847 EnsureSpace ensure_space(this);
848 emit_arith(7, op, Immediate(handle));
852 void Assembler::cmpb_al(const Operand& op) {
853 EnsureSpace ensure_space(this);
854 EMIT(0x38); // CMP r/m8, r8
855 emit_operand(eax, op); // eax has same code as register al.
859 void Assembler::cmpw_ax(const Operand& op) {
860 EnsureSpace ensure_space(this);
862 EMIT(0x39); // CMP r/m16, r16
863 emit_operand(eax, op); // eax has same code as register ax.
867 void Assembler::dec_b(Register dst) {
868 CHECK(dst.is_byte_register());
869 EnsureSpace ensure_space(this);
871 EMIT(0xC8 | dst.code());
875 void Assembler::dec_b(const Operand& dst) {
876 EnsureSpace ensure_space(this);
878 emit_operand(ecx, dst);
882 void Assembler::dec(Register dst) {
883 EnsureSpace ensure_space(this);
884 EMIT(0x48 | dst.code());
888 void Assembler::dec(const Operand& dst) {
889 EnsureSpace ensure_space(this);
891 emit_operand(ecx, dst);
895 void Assembler::cdq() {
896 EnsureSpace ensure_space(this);
901 void Assembler::idiv(const Operand& src) {
902 EnsureSpace ensure_space(this);
904 emit_operand(edi, src);
908 void Assembler::div(const Operand& src) {
909 EnsureSpace ensure_space(this);
911 emit_operand(esi, src);
915 void Assembler::imul(Register reg) {
916 EnsureSpace ensure_space(this);
918 EMIT(0xE8 | reg.code());
922 void Assembler::imul(Register dst, const Operand& src) {
923 EnsureSpace ensure_space(this);
926 emit_operand(dst, src);
930 void Assembler::imul(Register dst, Register src, int32_t imm32) {
931 imul(dst, Operand(src), imm32);
935 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
936 EnsureSpace ensure_space(this);
937 if (is_int8(imm32)) {
939 emit_operand(dst, src);
943 emit_operand(dst, src);
949 void Assembler::inc(Register dst) {
950 EnsureSpace ensure_space(this);
951 EMIT(0x40 | dst.code());
955 void Assembler::inc(const Operand& dst) {
956 EnsureSpace ensure_space(this);
958 emit_operand(eax, dst);
962 void Assembler::lea(Register dst, const Operand& src) {
963 EnsureSpace ensure_space(this);
965 emit_operand(dst, src);
969 void Assembler::mul(Register src) {
970 EnsureSpace ensure_space(this);
972 EMIT(0xE0 | src.code());
976 void Assembler::neg(Register dst) {
977 EnsureSpace ensure_space(this);
979 EMIT(0xD8 | dst.code());
983 void Assembler::neg(const Operand& dst) {
984 EnsureSpace ensure_space(this);
986 emit_operand(ebx, dst);
990 void Assembler::not_(Register dst) {
991 EnsureSpace ensure_space(this);
993 EMIT(0xD0 | dst.code());
997 void Assembler::not_(const Operand& dst) {
998 EnsureSpace ensure_space(this);
1000 emit_operand(edx, dst);
1004 void Assembler::or_(Register dst, int32_t imm32) {
1005 EnsureSpace ensure_space(this);
1006 emit_arith(1, Operand(dst), Immediate(imm32));
1010 void Assembler::or_(Register dst, const Operand& src) {
1011 EnsureSpace ensure_space(this);
1013 emit_operand(dst, src);
1017 void Assembler::or_(const Operand& dst, const Immediate& x) {
1018 EnsureSpace ensure_space(this);
1019 emit_arith(1, dst, x);
1023 void Assembler::or_(const Operand& dst, Register src) {
1024 EnsureSpace ensure_space(this);
1026 emit_operand(src, dst);
1030 void Assembler::rcl(Register dst, uint8_t imm8) {
1031 EnsureSpace ensure_space(this);
1032 DCHECK(is_uint5(imm8)); // illegal shift count
1035 EMIT(0xD0 | dst.code());
1038 EMIT(0xD0 | dst.code());
1044 void Assembler::rcr(Register dst, uint8_t imm8) {
1045 EnsureSpace ensure_space(this);
1046 DCHECK(is_uint5(imm8)); // illegal shift count
1049 EMIT(0xD8 | dst.code());
1052 EMIT(0xD8 | dst.code());
1058 void Assembler::ror(const Operand& dst, uint8_t imm8) {
1059 EnsureSpace ensure_space(this);
1060 DCHECK(is_uint5(imm8)); // illegal shift count
1063 emit_operand(ecx, dst);
1066 emit_operand(ecx, dst);
1072 void Assembler::ror_cl(const Operand& dst) {
1073 EnsureSpace ensure_space(this);
1075 emit_operand(ecx, dst);
1079 void Assembler::sar(const Operand& dst, uint8_t imm8) {
1080 EnsureSpace ensure_space(this);
1081 DCHECK(is_uint5(imm8)); // illegal shift count
1084 emit_operand(edi, dst);
1087 emit_operand(edi, dst);
1093 void Assembler::sar_cl(const Operand& dst) {
1094 EnsureSpace ensure_space(this);
1096 emit_operand(edi, dst);
1100 void Assembler::sbb(Register dst, const Operand& src) {
1101 EnsureSpace ensure_space(this);
1103 emit_operand(dst, src);
1107 void Assembler::shld(Register dst, const Operand& src) {
1108 EnsureSpace ensure_space(this);
1111 emit_operand(dst, src);
1115 void Assembler::shl(const Operand& dst, uint8_t imm8) {
1116 EnsureSpace ensure_space(this);
1117 DCHECK(is_uint5(imm8)); // illegal shift count
1120 emit_operand(esp, dst);
1123 emit_operand(esp, dst);
1129 void Assembler::shl_cl(const Operand& dst) {
1130 EnsureSpace ensure_space(this);
1132 emit_operand(esp, dst);
1136 void Assembler::shrd(Register dst, const Operand& src) {
1137 EnsureSpace ensure_space(this);
1140 emit_operand(dst, src);
1144 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1145 EnsureSpace ensure_space(this);
1146 DCHECK(is_uint5(imm8)); // illegal shift count
1149 emit_operand(ebp, dst);
1152 emit_operand(ebp, dst);
1158 void Assembler::shr_cl(const Operand& dst) {
1159 EnsureSpace ensure_space(this);
1161 emit_operand(ebp, dst);
1165 void Assembler::sub(const Operand& dst, const Immediate& x) {
1166 EnsureSpace ensure_space(this);
1167 emit_arith(5, dst, x);
1171 void Assembler::sub(Register dst, const Operand& src) {
1172 EnsureSpace ensure_space(this);
1174 emit_operand(dst, src);
1178 void Assembler::sub(const Operand& dst, Register src) {
1179 EnsureSpace ensure_space(this);
1181 emit_operand(src, dst);
1185 void Assembler::test(Register reg, const Immediate& imm) {
1186 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1187 test_b(reg, imm.x_);
1191 EnsureSpace ensure_space(this);
1192 // This is not using emit_arith because test doesn't support
1193 // sign-extension of 8-bit operands.
1198 EMIT(0xC0 | reg.code());
1204 void Assembler::test(Register reg, const Operand& op) {
1205 EnsureSpace ensure_space(this);
1207 emit_operand(reg, op);
1211 void Assembler::test_b(Register reg, const Operand& op) {
1212 CHECK(reg.is_byte_register());
1213 EnsureSpace ensure_space(this);
1215 emit_operand(reg, op);
1219 void Assembler::test(const Operand& op, const Immediate& imm) {
1220 if (op.is_reg_only()) {
1221 test(op.reg(), imm);
1224 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1225 return test_b(op, imm.x_);
1227 EnsureSpace ensure_space(this);
1229 emit_operand(eax, op);
1234 void Assembler::test_b(Register reg, uint8_t imm8) {
1235 EnsureSpace ensure_space(this);
1236 // Only use test against byte for registers that have a byte
1237 // variant: eax, ebx, ecx, and edx.
1241 } else if (reg.is_byte_register()) {
1242 emit_arith_b(0xF6, 0xC0, reg, imm8);
1245 EMIT(0xC0 | reg.code());
1251 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1252 if (op.is_reg_only()) {
1253 test_b(op.reg(), imm8);
1256 EnsureSpace ensure_space(this);
1258 emit_operand(eax, op);
1263 void Assembler::xor_(Register dst, int32_t imm32) {
1264 EnsureSpace ensure_space(this);
1265 emit_arith(6, Operand(dst), Immediate(imm32));
1269 void Assembler::xor_(Register dst, const Operand& src) {
1270 EnsureSpace ensure_space(this);
1272 emit_operand(dst, src);
1276 void Assembler::xor_(const Operand& dst, Register src) {
1277 EnsureSpace ensure_space(this);
1279 emit_operand(src, dst);
1283 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1284 EnsureSpace ensure_space(this);
1285 emit_arith(6, dst, x);
1289 void Assembler::bt(const Operand& dst, Register src) {
1290 EnsureSpace ensure_space(this);
1293 emit_operand(src, dst);
1297 void Assembler::bts(const Operand& dst, Register src) {
1298 EnsureSpace ensure_space(this);
1301 emit_operand(src, dst);
1305 void Assembler::bsr(Register dst, const Operand& src) {
1306 EnsureSpace ensure_space(this);
1309 emit_operand(dst, src);
1313 void Assembler::hlt() {
1314 EnsureSpace ensure_space(this);
1319 void Assembler::int3() {
1320 EnsureSpace ensure_space(this);
1325 void Assembler::nop() {
1326 EnsureSpace ensure_space(this);
1331 void Assembler::ret(int imm16) {
1332 EnsureSpace ensure_space(this);
1333 DCHECK(is_uint16(imm16));
1339 EMIT((imm16 >> 8) & 0xFF);
1344 void Assembler::ud2() {
1345 EnsureSpace ensure_space(this);
1351 // Labels refer to positions in the (to be) generated code.
1352 // There are bound, linked, and unused labels.
1354 // Bound labels refer to known positions in the already
1355 // generated code. pos() is the position the label refers to.
1357 // Linked labels refer to unknown positions in the code
1358 // to be generated; pos() is the position of the 32bit
1359 // Displacement of the last instruction using the label.
1362 void Assembler::print(Label* L) {
1363 if (L->is_unused()) {
1364 PrintF("unused label\n");
1365 } else if (L->is_bound()) {
1366 PrintF("bound label to %d\n", L->pos());
1367 } else if (L->is_linked()) {
1369 PrintF("unbound label");
1370 while (l.is_linked()) {
1371 Displacement disp = disp_at(&l);
1372 PrintF("@ %d ", l.pos());
1378 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1383 void Assembler::bind_to(Label* L, int pos) {
1384 EnsureSpace ensure_space(this);
1385 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1386 while (L->is_linked()) {
1387 Displacement disp = disp_at(L);
1388 int fixup_pos = L->pos();
1389 if (disp.type() == Displacement::CODE_ABSOLUTE) {
1390 long_at_put(fixup_pos, reinterpret_cast<int>(buffer_ + pos));
1391 internal_reference_positions_.push_back(fixup_pos);
1392 } else if (disp.type() == Displacement::CODE_RELATIVE) {
1393 // Relative to Code* heap object pointer.
1394 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1396 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1397 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1399 // Relative address, relative to point after address.
1400 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1401 long_at_put(fixup_pos, imm32);
1405 while (L->is_near_linked()) {
1406 int fixup_pos = L->near_link_pos();
1407 int offset_to_next =
1408 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1409 DCHECK(offset_to_next <= 0);
1410 // Relative address, relative to point after address.
1411 int disp = pos - fixup_pos - sizeof(int8_t);
1412 CHECK(0 <= disp && disp <= 127);
1413 set_byte_at(fixup_pos, disp);
1414 if (offset_to_next < 0) {
1415 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1424 void Assembler::bind(Label* L) {
1425 EnsureSpace ensure_space(this);
1426 DCHECK(!L->is_bound()); // label can only be bound once
1427 bind_to(L, pc_offset());
1431 void Assembler::call(Label* L) {
1432 positions_recorder()->WriteRecordedPositions();
1433 EnsureSpace ensure_space(this);
1434 if (L->is_bound()) {
1435 const int long_size = 5;
1436 int offs = L->pos() - pc_offset();
1438 // 1110 1000 #32-bit disp.
1440 emit(offs - long_size);
1442 // 1110 1000 #32-bit disp.
1444 emit_disp(L, Displacement::OTHER);
1449 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1450 positions_recorder()->WriteRecordedPositions();
1451 EnsureSpace ensure_space(this);
1452 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1454 if (RelocInfo::IsRuntimeEntry(rmode)) {
1455 emit(reinterpret_cast<uint32_t>(entry), rmode);
1457 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1462 int Assembler::CallSize(const Operand& adr) {
1463 // Call size is 1 (opcode) + adr.len_ (operand).
1464 return 1 + adr.len_;
1468 void Assembler::call(const Operand& adr) {
1469 positions_recorder()->WriteRecordedPositions();
1470 EnsureSpace ensure_space(this);
1472 emit_operand(edx, adr);
1476 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1477 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1481 void Assembler::call(Handle<Code> code,
1482 RelocInfo::Mode rmode,
1483 TypeFeedbackId ast_id) {
1484 positions_recorder()->WriteRecordedPositions();
1485 EnsureSpace ensure_space(this);
1486 DCHECK(RelocInfo::IsCodeTarget(rmode)
1487 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1489 emit(code, rmode, ast_id);
1493 void Assembler::jmp(Label* L, Label::Distance distance) {
1494 EnsureSpace ensure_space(this);
1495 if (L->is_bound()) {
1496 const int short_size = 2;
1497 const int long_size = 5;
1498 int offs = L->pos() - pc_offset();
1500 if (is_int8(offs - short_size)) {
1501 // 1110 1011 #8-bit disp.
1503 EMIT((offs - short_size) & 0xFF);
1505 // 1110 1001 #32-bit disp.
1507 emit(offs - long_size);
1509 } else if (distance == Label::kNear) {
1513 // 1110 1001 #32-bit disp.
1515 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1520 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1521 EnsureSpace ensure_space(this);
1522 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1524 if (RelocInfo::IsRuntimeEntry(rmode)) {
1525 emit(reinterpret_cast<uint32_t>(entry), rmode);
1527 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1532 void Assembler::jmp(const Operand& adr) {
1533 EnsureSpace ensure_space(this);
1535 emit_operand(esp, adr);
1539 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1540 EnsureSpace ensure_space(this);
1541 DCHECK(RelocInfo::IsCodeTarget(rmode));
1547 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1548 EnsureSpace ensure_space(this);
1549 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1550 if (L->is_bound()) {
1551 const int short_size = 2;
1552 const int long_size = 6;
1553 int offs = L->pos() - pc_offset();
1555 if (is_int8(offs - short_size)) {
1556 // 0111 tttn #8-bit disp
1558 EMIT((offs - short_size) & 0xFF);
1560 // 0000 1111 1000 tttn #32-bit disp
1563 emit(offs - long_size);
1565 } else if (distance == Label::kNear) {
1569 // 0000 1111 1000 tttn #32-bit disp
1570 // Note: could eliminate cond. jumps to this jump if condition
1571 // is the same however, seems to be rather unlikely case.
1574 emit_disp(L, Displacement::OTHER);
1579 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1580 EnsureSpace ensure_space(this);
1581 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1582 // 0000 1111 1000 tttn #32-bit disp.
1585 if (RelocInfo::IsRuntimeEntry(rmode)) {
1586 emit(reinterpret_cast<uint32_t>(entry), rmode);
1588 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1593 void Assembler::j(Condition cc, Handle<Code> code) {
1594 EnsureSpace ensure_space(this);
1595 // 0000 1111 1000 tttn #32-bit disp
1598 emit(code, RelocInfo::CODE_TARGET);
1602 // FPU instructions.
1604 void Assembler::fld(int i) {
1605 EnsureSpace ensure_space(this);
1606 emit_farith(0xD9, 0xC0, i);
1610 void Assembler::fstp(int i) {
1611 EnsureSpace ensure_space(this);
1612 emit_farith(0xDD, 0xD8, i);
1616 void Assembler::fld1() {
1617 EnsureSpace ensure_space(this);
1623 void Assembler::fldpi() {
1624 EnsureSpace ensure_space(this);
1630 void Assembler::fldz() {
1631 EnsureSpace ensure_space(this);
1637 void Assembler::fldln2() {
1638 EnsureSpace ensure_space(this);
1644 void Assembler::fld_s(const Operand& adr) {
1645 EnsureSpace ensure_space(this);
1647 emit_operand(eax, adr);
1651 void Assembler::fld_d(const Operand& adr) {
1652 EnsureSpace ensure_space(this);
1654 emit_operand(eax, adr);
1658 void Assembler::fstp_s(const Operand& adr) {
1659 EnsureSpace ensure_space(this);
1661 emit_operand(ebx, adr);
1665 void Assembler::fst_s(const Operand& adr) {
1666 EnsureSpace ensure_space(this);
1668 emit_operand(edx, adr);
1672 void Assembler::fstp_d(const Operand& adr) {
1673 EnsureSpace ensure_space(this);
1675 emit_operand(ebx, adr);
1679 void Assembler::fst_d(const Operand& adr) {
1680 EnsureSpace ensure_space(this);
1682 emit_operand(edx, adr);
1686 void Assembler::fild_s(const Operand& adr) {
1687 EnsureSpace ensure_space(this);
1689 emit_operand(eax, adr);
1693 void Assembler::fild_d(const Operand& adr) {
1694 EnsureSpace ensure_space(this);
1696 emit_operand(ebp, adr);
1700 void Assembler::fistp_s(const Operand& adr) {
1701 EnsureSpace ensure_space(this);
1703 emit_operand(ebx, adr);
1707 void Assembler::fisttp_s(const Operand& adr) {
1708 DCHECK(IsEnabled(SSE3));
1709 EnsureSpace ensure_space(this);
1711 emit_operand(ecx, adr);
1715 void Assembler::fisttp_d(const Operand& adr) {
1716 DCHECK(IsEnabled(SSE3));
1717 EnsureSpace ensure_space(this);
1719 emit_operand(ecx, adr);
1723 void Assembler::fist_s(const Operand& adr) {
1724 EnsureSpace ensure_space(this);
1726 emit_operand(edx, adr);
1730 void Assembler::fistp_d(const Operand& adr) {
1731 EnsureSpace ensure_space(this);
1733 emit_operand(edi, adr);
1737 void Assembler::fabs() {
1738 EnsureSpace ensure_space(this);
1744 void Assembler::fchs() {
1745 EnsureSpace ensure_space(this);
1751 void Assembler::fcos() {
1752 EnsureSpace ensure_space(this);
1758 void Assembler::fsin() {
1759 EnsureSpace ensure_space(this);
1765 void Assembler::fptan() {
1766 EnsureSpace ensure_space(this);
1772 void Assembler::fyl2x() {
1773 EnsureSpace ensure_space(this);
1779 void Assembler::f2xm1() {
1780 EnsureSpace ensure_space(this);
1786 void Assembler::fscale() {
1787 EnsureSpace ensure_space(this);
1793 void Assembler::fninit() {
1794 EnsureSpace ensure_space(this);
1800 void Assembler::fadd(int i) {
1801 EnsureSpace ensure_space(this);
1802 emit_farith(0xDC, 0xC0, i);
1806 void Assembler::fadd_i(int i) {
1807 EnsureSpace ensure_space(this);
1808 emit_farith(0xD8, 0xC0, i);
1812 void Assembler::fsub(int i) {
1813 EnsureSpace ensure_space(this);
1814 emit_farith(0xDC, 0xE8, i);
1818 void Assembler::fsub_i(int i) {
1819 EnsureSpace ensure_space(this);
1820 emit_farith(0xD8, 0xE0, i);
1824 void Assembler::fisub_s(const Operand& adr) {
1825 EnsureSpace ensure_space(this);
1827 emit_operand(esp, adr);
1831 void Assembler::fmul_i(int i) {
1832 EnsureSpace ensure_space(this);
1833 emit_farith(0xD8, 0xC8, i);
1837 void Assembler::fmul(int i) {
1838 EnsureSpace ensure_space(this);
1839 emit_farith(0xDC, 0xC8, i);
1843 void Assembler::fdiv(int i) {
1844 EnsureSpace ensure_space(this);
1845 emit_farith(0xDC, 0xF8, i);
1849 void Assembler::fdiv_i(int i) {
1850 EnsureSpace ensure_space(this);
1851 emit_farith(0xD8, 0xF0, i);
1855 void Assembler::faddp(int i) {
1856 EnsureSpace ensure_space(this);
1857 emit_farith(0xDE, 0xC0, i);
1861 void Assembler::fsubp(int i) {
1862 EnsureSpace ensure_space(this);
1863 emit_farith(0xDE, 0xE8, i);
1867 void Assembler::fsubrp(int i) {
1868 EnsureSpace ensure_space(this);
1869 emit_farith(0xDE, 0xE0, i);
1873 void Assembler::fmulp(int i) {
1874 EnsureSpace ensure_space(this);
1875 emit_farith(0xDE, 0xC8, i);
1879 void Assembler::fdivp(int i) {
1880 EnsureSpace ensure_space(this);
1881 emit_farith(0xDE, 0xF8, i);
1885 void Assembler::fprem() {
1886 EnsureSpace ensure_space(this);
1892 void Assembler::fprem1() {
1893 EnsureSpace ensure_space(this);
1899 void Assembler::fxch(int i) {
1900 EnsureSpace ensure_space(this);
1901 emit_farith(0xD9, 0xC8, i);
1905 void Assembler::fincstp() {
1906 EnsureSpace ensure_space(this);
1912 void Assembler::ffree(int i) {
1913 EnsureSpace ensure_space(this);
1914 emit_farith(0xDD, 0xC0, i);
1918 void Assembler::ftst() {
1919 EnsureSpace ensure_space(this);
1925 void Assembler::fucomp(int i) {
1926 EnsureSpace ensure_space(this);
1927 emit_farith(0xDD, 0xE8, i);
1931 void Assembler::fucompp() {
1932 EnsureSpace ensure_space(this);
1938 void Assembler::fucomi(int i) {
1939 EnsureSpace ensure_space(this);
1945 void Assembler::fucomip() {
1946 EnsureSpace ensure_space(this);
1952 void Assembler::fcompp() {
1953 EnsureSpace ensure_space(this);
1959 void Assembler::fnstsw_ax() {
1960 EnsureSpace ensure_space(this);
1966 void Assembler::fwait() {
1967 EnsureSpace ensure_space(this);
1972 void Assembler::frndint() {
1973 EnsureSpace ensure_space(this);
1979 void Assembler::fnclex() {
1980 EnsureSpace ensure_space(this);
1986 void Assembler::sahf() {
1987 EnsureSpace ensure_space(this);
1992 void Assembler::setcc(Condition cc, Register reg) {
1993 DCHECK(reg.is_byte_register());
1994 EnsureSpace ensure_space(this);
1997 EMIT(0xC0 | reg.code());
2001 void Assembler::cvttss2si(Register dst, const Operand& src) {
2002 EnsureSpace ensure_space(this);
2006 emit_operand(dst, src);
2010 void Assembler::cvttsd2si(Register dst, const Operand& src) {
2011 EnsureSpace ensure_space(this);
2015 emit_operand(dst, src);
2019 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
2020 EnsureSpace ensure_space(this);
2024 emit_sse_operand(dst, src);
2028 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
2029 EnsureSpace ensure_space(this);
2033 emit_sse_operand(dst, src);
2037 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2038 EnsureSpace ensure_space(this);
2042 emit_sse_operand(dst, src);
2046 void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
2047 EnsureSpace ensure_space(this);
2051 emit_sse_operand(dst, src);
2055 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2056 EnsureSpace ensure_space(this);
2060 emit_sse_operand(dst, src);
2064 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2065 EnsureSpace ensure_space(this);
2069 emit_sse_operand(dst, src);
2073 void Assembler::subsd(XMMRegister dst, const Operand& src) {
2074 EnsureSpace ensure_space(this);
2078 emit_sse_operand(dst, src);
2082 void Assembler::divsd(XMMRegister dst, const Operand& src) {
2083 EnsureSpace ensure_space(this);
2087 emit_sse_operand(dst, src);
2091 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2092 EnsureSpace ensure_space(this);
2096 emit_sse_operand(dst, src);
2100 void Assembler::andps(XMMRegister dst, const Operand& src) {
2101 EnsureSpace ensure_space(this);
2104 emit_sse_operand(dst, src);
2108 void Assembler::orps(XMMRegister dst, const Operand& src) {
2109 EnsureSpace ensure_space(this);
2112 emit_sse_operand(dst, src);
2116 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2117 EnsureSpace ensure_space(this);
2120 emit_sse_operand(dst, src);
2124 void Assembler::addps(XMMRegister dst, const Operand& src) {
2125 EnsureSpace ensure_space(this);
2128 emit_sse_operand(dst, src);
2132 void Assembler::subps(XMMRegister dst, const Operand& src) {
2133 EnsureSpace ensure_space(this);
2136 emit_sse_operand(dst, src);
2140 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2141 EnsureSpace ensure_space(this);
2144 emit_sse_operand(dst, src);
2148 void Assembler::divps(XMMRegister dst, const Operand& src) {
2149 EnsureSpace ensure_space(this);
2152 emit_sse_operand(dst, src);
2156 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2157 EnsureSpace ensure_space(this);
2161 emit_sse_operand(dst, src);
2165 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2166 EnsureSpace ensure_space(this);
2170 emit_sse_operand(dst, src);
2174 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2175 EnsureSpace ensure_space(this);
2179 emit_sse_operand(dst, src);
2183 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2184 EnsureSpace ensure_space(this);
2188 emit_sse_operand(dst, src);
2192 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2193 DCHECK(IsEnabled(SSE4_1));
2194 EnsureSpace ensure_space(this);
2199 emit_sse_operand(dst, src);
2200 // Mask precision exeption.
2201 EMIT(static_cast<byte>(mode) | 0x8);
2205 void Assembler::movmskpd(Register dst, XMMRegister src) {
2206 EnsureSpace ensure_space(this);
2210 emit_sse_operand(dst, src);
2214 void Assembler::movmskps(Register dst, XMMRegister src) {
2215 EnsureSpace ensure_space(this);
2218 emit_sse_operand(dst, src);
2222 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2223 EnsureSpace ensure_space(this);
2227 emit_sse_operand(dst, src);
2231 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2232 EnsureSpace ensure_space(this);
2236 emit_sse_operand(dst, src);
2241 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2242 EnsureSpace ensure_space(this);
2245 emit_sse_operand(dst, src);
2249 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2250 DCHECK(is_uint8(imm8));
2251 EnsureSpace ensure_space(this);
2254 emit_sse_operand(dst, src);
2259 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2260 EnsureSpace ensure_space(this);
2264 emit_sse_operand(src, dst);
2268 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2269 EnsureSpace ensure_space(this);
2273 emit_sse_operand(dst, src);
2277 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2278 EnsureSpace ensure_space(this);
2282 emit_sse_operand(src, dst);
2286 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2287 EnsureSpace ensure_space(this);
2291 emit_sse_operand(dst, src);
2295 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2296 DCHECK(IsEnabled(SSE4_1));
2297 EnsureSpace ensure_space(this);
2302 emit_sse_operand(dst, src);
2306 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2307 EnsureSpace ensure_space(this);
2311 emit_sse_operand(src, dst);
2315 void Assembler::prefetch(const Operand& src, int level) {
2316 DCHECK(is_uint2(level));
2317 EnsureSpace ensure_space(this);
2320 // Emit hint number in Reg position of RegR/M.
2321 XMMRegister code = XMMRegister::from_code(level);
2322 emit_sse_operand(code, src);
2326 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2327 EnsureSpace ensure_space(this);
2328 EMIT(0xF2); // double
2330 EMIT(0x11); // store
2331 emit_sse_operand(src, dst);
2335 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2336 EnsureSpace ensure_space(this);
2337 EMIT(0xF2); // double
2340 emit_sse_operand(dst, src);
2344 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2345 EnsureSpace ensure_space(this);
2346 EMIT(0xF3); // float
2348 EMIT(0x11); // store
2349 emit_sse_operand(src, dst);
2353 void Assembler::movss(XMMRegister dst, const Operand& src) {
2354 EnsureSpace ensure_space(this);
2355 EMIT(0xF3); // float
2358 emit_sse_operand(dst, src);
2362 void Assembler::movd(XMMRegister dst, const Operand& src) {
2363 EnsureSpace ensure_space(this);
2367 emit_sse_operand(dst, src);
2371 void Assembler::movd(const Operand& dst, XMMRegister src) {
2372 EnsureSpace ensure_space(this);
2376 emit_sse_operand(src, dst);
2380 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2381 DCHECK(IsEnabled(SSE4_1));
2382 DCHECK(is_uint8(imm8));
2383 EnsureSpace ensure_space(this);
2388 emit_sse_operand(src, dst);
2393 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2394 EnsureSpace ensure_space(this);
2398 emit_sse_operand(dst, src);
2402 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2403 EnsureSpace ensure_space(this);
2407 emit_sse_operand(dst, src);
2411 void Assembler::por(XMMRegister dst, XMMRegister src) {
2412 EnsureSpace ensure_space(this);
2416 emit_sse_operand(dst, src);
2420 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2421 DCHECK(IsEnabled(SSE4_1));
2422 EnsureSpace ensure_space(this);
2427 emit_sse_operand(dst, src);
2431 void Assembler::pslld(XMMRegister reg, int8_t shift) {
2432 EnsureSpace ensure_space(this);
2436 emit_sse_operand(esi, reg); // esi == 6
2441 void Assembler::psrld(XMMRegister reg, int8_t shift) {
2442 EnsureSpace ensure_space(this);
2446 emit_sse_operand(edx, reg); // edx == 2
2451 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2452 EnsureSpace ensure_space(this);
2456 emit_sse_operand(esi, reg); // esi == 6
2461 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2462 EnsureSpace ensure_space(this);
2466 emit_sse_operand(dst, src);
2470 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2471 EnsureSpace ensure_space(this);
2475 emit_sse_operand(edx, reg); // edx == 2
2480 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2481 EnsureSpace ensure_space(this);
2485 emit_sse_operand(dst, src);
2489 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2490 EnsureSpace ensure_space(this);
2494 emit_sse_operand(dst, src);
2499 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2500 DCHECK(IsEnabled(SSE4_1));
2501 EnsureSpace ensure_space(this);
2506 emit_sse_operand(src, dst);
2511 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2512 DCHECK(IsEnabled(SSE4_1));
2513 EnsureSpace ensure_space(this);
2518 emit_sse_operand(dst, src);
2523 void Assembler::addss(XMMRegister dst, const Operand& src) {
2524 EnsureSpace ensure_space(this);
2528 emit_sse_operand(dst, src);
2532 void Assembler::subss(XMMRegister dst, const Operand& src) {
2533 EnsureSpace ensure_space(this);
2537 emit_sse_operand(dst, src);
2541 void Assembler::mulss(XMMRegister dst, const Operand& src) {
2542 EnsureSpace ensure_space(this);
2546 emit_sse_operand(dst, src);
2550 void Assembler::divss(XMMRegister dst, const Operand& src) {
2551 EnsureSpace ensure_space(this);
2555 emit_sse_operand(dst, src);
2559 void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
2560 EnsureSpace ensure_space(this);
2563 emit_sse_operand(dst, src);
2568 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
2569 const Operand& src2) {
2570 DCHECK(IsEnabled(FMA3));
2571 EnsureSpace ensure_space(this);
2572 emit_vex_prefix(src1, kLIG, k66, k0F38, kW1);
2574 emit_sse_operand(dst, src2);
2578 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
2579 const Operand& src2) {
2580 DCHECK(IsEnabled(FMA3));
2581 EnsureSpace ensure_space(this);
2582 emit_vex_prefix(src1, kLIG, k66, k0F38, kW0);
2584 emit_sse_operand(dst, src2);
2588 void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1,
2589 const Operand& src2) {
2590 DCHECK(IsEnabled(AVX));
2591 EnsureSpace ensure_space(this);
2592 emit_vex_prefix(src1, kLIG, kF2, k0F, kWIG);
2594 emit_sse_operand(dst, src2);
2598 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2599 Register ireg = { reg.code() };
2600 emit_operand(ireg, adr);
2604 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2605 EMIT(0xC0 | dst.code() << 3 | src.code());
2609 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2610 EMIT(0xC0 | dst.code() << 3 | src.code());
2614 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2615 EMIT(0xC0 | (dst.code() << 3) | src.code());
2619 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp,
2620 LeadingOpcode mm, VexW w) {
2621 if (mm != k0F || w != kW0) {
2624 EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp);
2627 EMIT(((~vreg.code()) << 3) | l | pp);
2632 void Assembler::GrowBuffer() {
2633 DCHECK(buffer_overflow());
2634 if (!own_buffer_) FATAL("external code buffer is too small");
2636 // Compute new buffer size.
2637 CodeDesc desc; // the new buffer
2638 desc.buffer_size = 2 * buffer_size_;
2640 // Some internal data structures overflow for very large buffers,
2641 // they must ensure that kMaximalBufferSize is not too large.
2642 if ((desc.buffer_size > kMaximalBufferSize) ||
2643 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2644 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2647 // Set up new buffer.
2648 desc.buffer = NewArray<byte>(desc.buffer_size);
2649 desc.instr_size = pc_offset();
2650 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2652 // Clear the buffer in debug mode. Use 'int3' instructions to make
2653 // sure to get into problems if we ever run uninitialized code.
2655 memset(desc.buffer, 0xCC, desc.buffer_size);
2659 int pc_delta = desc.buffer - buffer_;
2660 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2661 MemMove(desc.buffer, buffer_, desc.instr_size);
2662 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2666 DeleteArray(buffer_);
2667 buffer_ = desc.buffer;
2668 buffer_size_ = desc.buffer_size;
2670 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2671 reloc_info_writer.last_pc() + pc_delta);
2673 // Relocate internal references.
2674 for (auto pos : internal_reference_positions_) {
2675 int32_t* p = reinterpret_cast<int32_t*>(buffer_ + pos);
2679 DCHECK(!buffer_overflow());
2683 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2684 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2685 DCHECK(is_uint8(imm8));
2686 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
2688 EMIT(op2 | dst.code());
2693 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2694 DCHECK((0 <= sel) && (sel <= 7));
2695 Register ireg = { sel };
2697 EMIT(0x83); // using a sign-extended 8-bit immediate.
2698 emit_operand(ireg, dst);
2700 } else if (dst.is_reg(eax)) {
2701 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2704 EMIT(0x81); // using a literal 32-bit immediate.
2705 emit_operand(ireg, dst);
2711 void Assembler::emit_operand(Register reg, const Operand& adr) {
2712 const unsigned length = adr.len_;
2715 // Emit updated ModRM byte containing the given register.
2716 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2718 // Emit the rest of the encoded operand.
2719 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2722 // Emit relocation information if necessary.
2723 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2724 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2725 RecordRelocInfo(adr.rmode_);
2726 if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) { // Fixup for labels
2727 emit_label(*reinterpret_cast<Label**>(pc_));
2729 pc_ += sizeof(int32_t);
2735 void Assembler::emit_label(Label* label) {
2736 if (label->is_bound()) {
2737 internal_reference_positions_.push_back(pc_offset());
2738 emit(reinterpret_cast<uint32_t>(buffer_ + label->pos()));
2740 emit_disp(label, Displacement::CODE_ABSOLUTE);
2745 void Assembler::emit_farith(int b1, int b2, int i) {
2746 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2747 DCHECK(0 <= i && i < 8); // illegal stack offset
2753 void Assembler::db(uint8_t data) {
2754 EnsureSpace ensure_space(this);
2759 void Assembler::dd(uint32_t data) {
2760 EnsureSpace ensure_space(this);
2765 void Assembler::dd(Label* label) {
2766 EnsureSpace ensure_space(this);
2767 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2772 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2773 DCHECK(!RelocInfo::IsNone(rmode));
2774 // Don't record external references unless the heap will be serialized.
2775 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2776 !serializer_enabled() && !emit_debug_code()) {
2779 RelocInfo rinfo(pc_, rmode, data, NULL);
2780 reloc_info_writer.Write(&rinfo);
2784 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2785 // No out-of-line constant pool support.
2786 DCHECK(!FLAG_enable_ool_constant_pool);
2787 return isolate->factory()->empty_constant_pool_array();
2791 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2792 // No out-of-line constant pool support.
2793 DCHECK(!FLAG_enable_ool_constant_pool);
2798 #ifdef GENERATED_CODE_COVERAGE
2799 static FILE* coverage_log = NULL;
2802 static void InitCoverageLog() {
2803 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2804 if (file_name != NULL) {
2805 coverage_log = fopen(file_name, "aw+");
2810 void LogGeneratedCodeCoverage(const char* file_line) {
2811 const char* return_address = (&file_line)[-1];
2812 char* push_insn = const_cast<char*>(return_address - 12);
2813 push_insn[0] = 0xeb; // Relative branch insn.
2814 push_insn[1] = 13; // Skip over coverage insns.
2815 if (coverage_log != NULL) {
2816 fprintf(coverage_log, "%s\n", file_line);
2817 fflush(coverage_log);
2823 } } // namespace v8::internal
2825 #endif // V8_TARGET_ARCH_IA32