1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
37 #include "src/ia32/assembler-ia32.h"
41 #if V8_TARGET_ARCH_IA32
44 #include <intrin.h> // _xgetbv()
47 #include <sys/sysctl.h>
50 #include "src/base/bits.h"
51 #include "src/base/cpu.h"
52 #include "src/disassembler.h"
53 #include "src/macro-assembler.h"
59 // -----------------------------------------------------------------------------
60 // Implementation of CpuFeatures
66 V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
68 // Check xgetbv; this uses a .byte sequence instead of the instruction
69 // directly because older assemblers do not include support for xgetbv and
70 // there is no easy way to conditionally compile based on the assembler
72 __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
73 return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
76 #define _XCR_XFEATURE_ENABLED_MASK 0
78 #endif // !V8_LIBC_MSVCRT
81 bool OSHasAVXSupport() {
83 // Mac OS X up to 10.9 has a bug where AVX transitions were indeed being
84 // caused by ISRs, so we detect that here and disable AVX in that case.
86 size_t buffer_size = arraysize(buffer);
87 int ctl_name[] = {CTL_KERN, KERN_OSRELEASE};
88 if (sysctl(ctl_name, 2, buffer, &buffer_size, nullptr, 0) != 0) {
89 V8_Fatal(__FILE__, __LINE__, "V8 failed to get kernel version");
91 // The buffer now contains a string of the form XX.YY.ZZ, where
92 // XX is the major kernel version component.
93 char* period_pos = strchr(buffer, '.');
94 DCHECK_NOT_NULL(period_pos);
96 long kernel_version_major = strtol(buffer, nullptr, 10); // NOLINT
97 if (kernel_version_major <= 13) return false;
98 #endif // V8_OS_MACOSX
99 // Check whether OS claims to support AVX.
100 uint64_t feature_mask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
101 return (feature_mask & 0x6) == 0x6;
107 void CpuFeatures::ProbeImpl(bool cross_compile) {
109 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
110 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
112 // Only use statically determined features for cross compile (snapshot).
113 if (cross_compile) return;
115 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
116 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
117 if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
119 supported_ |= 1u << AVX;
121 if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
123 supported_ |= 1u << FMA3;
125 if (strcmp(FLAG_mcpu, "auto") == 0) {
126 if (cpu.is_atom()) supported_ |= 1u << ATOM;
127 } else if (strcmp(FLAG_mcpu, "atom") == 0) {
128 supported_ |= 1u << ATOM;
133 void CpuFeatures::PrintTarget() { }
134 void CpuFeatures::PrintFeatures() {
135 printf("SSE3=%d SSE4_1=%d AVX=%d FMA3=%d ATOM=%d\n",
136 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
137 CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
138 CpuFeatures::IsSupported(ATOM));
142 // -----------------------------------------------------------------------------
143 // Implementation of Displacement
145 void Displacement::init(Label* L, Type type) {
146 DCHECK(!L->is_bound());
148 if (L->is_linked()) {
150 DCHECK(next > 0); // Displacements must be at positions > 0
152 // Ensure that we _never_ overflow the next field.
153 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
154 data_ = NextField::encode(next) | TypeField::encode(type);
158 // -----------------------------------------------------------------------------
159 // Implementation of RelocInfo
162 const int RelocInfo::kApplyMask =
163 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
164 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
165 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
168 bool RelocInfo::IsCodedSpecially() {
169 // The deserializer needs to know whether a pointer is specially coded. Being
170 // specially coded on IA32 means that it is a relative address, as used by
171 // branch instructions. These are also the ones that need changing when a
172 // code object moves.
173 return (1 << rmode_) & kApplyMask;
177 bool RelocInfo::IsInConstantPool() {
182 // Patch the code at the current PC with a call to the target address.
183 // Additional guard int3 instructions can be added if required.
184 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
185 // Call instruction takes up 5 bytes and int3 takes up one byte.
186 static const int kCallCodeSize = 5;
187 int code_size = kCallCodeSize + guard_bytes;
189 // Create a code patcher.
190 CodePatcher patcher(pc_, code_size);
192 // Add a label for checking the size of the code used for returning.
194 Label check_codesize;
195 patcher.masm()->bind(&check_codesize);
199 patcher.masm()->call(target, RelocInfo::NONE32);
201 // Check that the size of the code generated is as expected.
202 DCHECK_EQ(kCallCodeSize,
203 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
205 // Add the requested number of int3 instructions after the call.
206 DCHECK_GE(guard_bytes, 0);
207 for (int i = 0; i < guard_bytes; i++) {
208 patcher.masm()->int3();
213 // -----------------------------------------------------------------------------
214 // Implementation of Operand
216 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
218 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
221 if (base.is(esp)) set_sib(times_1, esp, base);
222 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
225 if (base.is(esp)) set_sib(times_1, esp, base);
230 if (base.is(esp)) set_sib(times_1, esp, base);
231 set_dispr(disp, rmode);
236 Operand::Operand(Register base,
240 RelocInfo::Mode rmode) {
241 DCHECK(!index.is(esp)); // illegal addressing mode
242 // [base + index*scale + disp/r]
243 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
244 // [base + index*scale]
246 set_sib(scale, index, base);
247 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
248 // [base + index*scale + disp8]
250 set_sib(scale, index, base);
253 // [base + index*scale + disp/r]
255 set_sib(scale, index, base);
256 set_dispr(disp, rmode);
261 Operand::Operand(Register index,
264 RelocInfo::Mode rmode) {
265 DCHECK(!index.is(esp)); // illegal addressing mode
266 // [index*scale + disp/r]
268 set_sib(scale, index, ebp);
269 set_dispr(disp, rmode);
273 bool Operand::is_reg(Register reg) const {
274 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
275 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
279 bool Operand::is_reg_only() const {
280 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
284 Register Operand::reg() const {
285 DCHECK(is_reg_only());
286 return Register::from_code(buf_[0] & 0x07);
290 // -----------------------------------------------------------------------------
291 // Implementation of Assembler.
293 // Emit a single byte. Must always be inlined.
298 #ifdef GENERATED_CODE_COVERAGE
299 static void InitCoverageLog();
302 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
303 : AssemblerBase(isolate, buffer, buffer_size),
304 positions_recorder_(this) {
305 // Clear the buffer in debug mode unless it was provided by the
306 // caller in which case we can't be sure it's okay to overwrite
307 // existing code in it; see CodePatcher::CodePatcher(...).
310 memset(buffer_, 0xCC, buffer_size_); // int3
314 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
316 #ifdef GENERATED_CODE_COVERAGE
322 void Assembler::GetCode(CodeDesc* desc) {
323 // Finalize code (at this point overflow() may be true, but the gap ensures
324 // that we are still not overlapping instructions and relocation info).
325 reloc_info_writer.Finish();
326 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
327 // Set up code descriptor.
328 desc->buffer = buffer_;
329 desc->buffer_size = buffer_size_;
330 desc->instr_size = pc_offset();
331 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
336 void Assembler::Align(int m) {
337 DCHECK(base::bits::IsPowerOfTwo32(m));
339 int addr = pc_offset();
340 Nop((m - (addr & mask)) & mask);
344 bool Assembler::IsNop(Address addr) {
346 while (*a == 0x66) a++;
347 if (*a == 0x90) return true;
348 if (a[0] == 0xf && a[1] == 0x1f) return true;
353 void Assembler::Nop(int bytes) {
354 EnsureSpace ensure_space(this);
356 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
418 void Assembler::CodeTargetAlign() {
419 Align(16); // Preferred alignment of jump targets on ia32.
423 void Assembler::cpuid() {
424 EnsureSpace ensure_space(this);
430 void Assembler::pushad() {
431 EnsureSpace ensure_space(this);
436 void Assembler::popad() {
437 EnsureSpace ensure_space(this);
442 void Assembler::pushfd() {
443 EnsureSpace ensure_space(this);
448 void Assembler::popfd() {
449 EnsureSpace ensure_space(this);
454 void Assembler::push(const Immediate& x) {
455 EnsureSpace ensure_space(this);
466 void Assembler::push_imm32(int32_t imm32) {
467 EnsureSpace ensure_space(this);
473 void Assembler::push(Register src) {
474 EnsureSpace ensure_space(this);
475 EMIT(0x50 | src.code());
479 void Assembler::push(const Operand& src) {
480 EnsureSpace ensure_space(this);
482 emit_operand(esi, src);
486 void Assembler::pop(Register dst) {
487 DCHECK(reloc_info_writer.last_pc() != NULL);
488 EnsureSpace ensure_space(this);
489 EMIT(0x58 | dst.code());
493 void Assembler::pop(const Operand& dst) {
494 EnsureSpace ensure_space(this);
496 emit_operand(eax, dst);
500 void Assembler::enter(const Immediate& size) {
501 EnsureSpace ensure_space(this);
508 void Assembler::leave() {
509 EnsureSpace ensure_space(this);
514 void Assembler::mov_b(Register dst, const Operand& src) {
515 CHECK(dst.is_byte_register());
516 EnsureSpace ensure_space(this);
518 emit_operand(dst, src);
522 void Assembler::mov_b(const Operand& dst, const Immediate& src) {
523 EnsureSpace ensure_space(this);
525 emit_operand(eax, dst);
526 EMIT(static_cast<int8_t>(src.x_));
530 void Assembler::mov_b(const Operand& dst, Register src) {
531 CHECK(src.is_byte_register());
532 EnsureSpace ensure_space(this);
534 emit_operand(src, dst);
538 void Assembler::mov_w(Register dst, const Operand& src) {
539 EnsureSpace ensure_space(this);
542 emit_operand(dst, src);
546 void Assembler::mov_w(const Operand& dst, Register src) {
547 EnsureSpace ensure_space(this);
550 emit_operand(src, dst);
554 void Assembler::mov_w(const Operand& dst, const Immediate& src) {
555 EnsureSpace ensure_space(this);
558 emit_operand(eax, dst);
559 EMIT(static_cast<int8_t>(src.x_ & 0xff));
560 EMIT(static_cast<int8_t>(src.x_ >> 8));
564 void Assembler::mov(Register dst, int32_t imm32) {
565 EnsureSpace ensure_space(this);
566 EMIT(0xB8 | dst.code());
571 void Assembler::mov(Register dst, const Immediate& x) {
572 EnsureSpace ensure_space(this);
573 EMIT(0xB8 | dst.code());
578 void Assembler::mov(Register dst, Handle<Object> handle) {
579 EnsureSpace ensure_space(this);
580 EMIT(0xB8 | dst.code());
585 void Assembler::mov(Register dst, const Operand& src) {
586 EnsureSpace ensure_space(this);
588 emit_operand(dst, src);
592 void Assembler::mov(Register dst, Register src) {
593 EnsureSpace ensure_space(this);
595 EMIT(0xC0 | src.code() << 3 | dst.code());
599 void Assembler::mov(const Operand& dst, const Immediate& x) {
600 EnsureSpace ensure_space(this);
602 emit_operand(eax, dst);
607 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
608 EnsureSpace ensure_space(this);
610 emit_operand(eax, dst);
615 void Assembler::mov(const Operand& dst, Register src) {
616 EnsureSpace ensure_space(this);
618 emit_operand(src, dst);
622 void Assembler::movsx_b(Register dst, const Operand& src) {
623 EnsureSpace ensure_space(this);
626 emit_operand(dst, src);
630 void Assembler::movsx_w(Register dst, const Operand& src) {
631 EnsureSpace ensure_space(this);
634 emit_operand(dst, src);
638 void Assembler::movzx_b(Register dst, const Operand& src) {
639 EnsureSpace ensure_space(this);
642 emit_operand(dst, src);
646 void Assembler::movzx_w(Register dst, const Operand& src) {
647 EnsureSpace ensure_space(this);
650 emit_operand(dst, src);
654 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
655 EnsureSpace ensure_space(this);
656 // Opcode: 0f 40 + cc /r.
659 emit_operand(dst, src);
663 void Assembler::cld() {
664 EnsureSpace ensure_space(this);
669 void Assembler::rep_movs() {
670 EnsureSpace ensure_space(this);
676 void Assembler::rep_stos() {
677 EnsureSpace ensure_space(this);
683 void Assembler::stos() {
684 EnsureSpace ensure_space(this);
689 void Assembler::xchg(Register dst, Register src) {
690 EnsureSpace ensure_space(this);
691 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
692 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
695 EMIT(0xC0 | src.code() << 3 | dst.code());
700 void Assembler::xchg(Register dst, const Operand& src) {
701 EnsureSpace ensure_space(this);
703 emit_operand(dst, src);
707 void Assembler::adc(Register dst, int32_t imm32) {
708 EnsureSpace ensure_space(this);
709 emit_arith(2, Operand(dst), Immediate(imm32));
713 void Assembler::adc(Register dst, const Operand& src) {
714 EnsureSpace ensure_space(this);
716 emit_operand(dst, src);
720 void Assembler::add(Register dst, const Operand& src) {
721 EnsureSpace ensure_space(this);
723 emit_operand(dst, src);
727 void Assembler::add(const Operand& dst, Register src) {
728 EnsureSpace ensure_space(this);
730 emit_operand(src, dst);
734 void Assembler::add(const Operand& dst, const Immediate& x) {
735 DCHECK(reloc_info_writer.last_pc() != NULL);
736 EnsureSpace ensure_space(this);
737 emit_arith(0, dst, x);
741 void Assembler::and_(Register dst, int32_t imm32) {
742 and_(dst, Immediate(imm32));
746 void Assembler::and_(Register dst, const Immediate& x) {
747 EnsureSpace ensure_space(this);
748 emit_arith(4, Operand(dst), x);
752 void Assembler::and_(Register dst, const Operand& src) {
753 EnsureSpace ensure_space(this);
755 emit_operand(dst, src);
759 void Assembler::and_(const Operand& dst, const Immediate& x) {
760 EnsureSpace ensure_space(this);
761 emit_arith(4, dst, x);
765 void Assembler::and_(const Operand& dst, Register src) {
766 EnsureSpace ensure_space(this);
768 emit_operand(src, dst);
772 void Assembler::cmpb(const Operand& op, int8_t imm8) {
773 EnsureSpace ensure_space(this);
774 if (op.is_reg(eax)) {
778 emit_operand(edi, op); // edi == 7
784 void Assembler::cmpb(const Operand& op, Register reg) {
785 CHECK(reg.is_byte_register());
786 EnsureSpace ensure_space(this);
788 emit_operand(reg, op);
792 void Assembler::cmpb(Register reg, const Operand& op) {
793 CHECK(reg.is_byte_register());
794 EnsureSpace ensure_space(this);
796 emit_operand(reg, op);
800 void Assembler::cmpw(const Operand& op, Immediate imm16) {
801 DCHECK(imm16.is_int16());
802 EnsureSpace ensure_space(this);
805 emit_operand(edi, op);
810 void Assembler::cmp(Register reg, int32_t imm32) {
811 EnsureSpace ensure_space(this);
812 emit_arith(7, Operand(reg), Immediate(imm32));
816 void Assembler::cmp(Register reg, Handle<Object> handle) {
817 EnsureSpace ensure_space(this);
818 emit_arith(7, Operand(reg), Immediate(handle));
822 void Assembler::cmp(Register reg, const Operand& op) {
823 EnsureSpace ensure_space(this);
825 emit_operand(reg, op);
829 void Assembler::cmp(const Operand& op, const Immediate& imm) {
830 EnsureSpace ensure_space(this);
831 emit_arith(7, op, imm);
835 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
836 EnsureSpace ensure_space(this);
837 emit_arith(7, op, Immediate(handle));
841 void Assembler::cmpb_al(const Operand& op) {
842 EnsureSpace ensure_space(this);
843 EMIT(0x38); // CMP r/m8, r8
844 emit_operand(eax, op); // eax has same code as register al.
848 void Assembler::cmpw_ax(const Operand& op) {
849 EnsureSpace ensure_space(this);
851 EMIT(0x39); // CMP r/m16, r16
852 emit_operand(eax, op); // eax has same code as register ax.
856 void Assembler::dec_b(Register dst) {
857 CHECK(dst.is_byte_register());
858 EnsureSpace ensure_space(this);
860 EMIT(0xC8 | dst.code());
864 void Assembler::dec_b(const Operand& dst) {
865 EnsureSpace ensure_space(this);
867 emit_operand(ecx, dst);
871 void Assembler::dec(Register dst) {
872 EnsureSpace ensure_space(this);
873 EMIT(0x48 | dst.code());
877 void Assembler::dec(const Operand& dst) {
878 EnsureSpace ensure_space(this);
880 emit_operand(ecx, dst);
884 void Assembler::cdq() {
885 EnsureSpace ensure_space(this);
890 void Assembler::idiv(const Operand& src) {
891 EnsureSpace ensure_space(this);
893 emit_operand(edi, src);
897 void Assembler::div(const Operand& src) {
898 EnsureSpace ensure_space(this);
900 emit_operand(esi, src);
904 void Assembler::imul(Register reg) {
905 EnsureSpace ensure_space(this);
907 EMIT(0xE8 | reg.code());
911 void Assembler::imul(Register dst, const Operand& src) {
912 EnsureSpace ensure_space(this);
915 emit_operand(dst, src);
919 void Assembler::imul(Register dst, Register src, int32_t imm32) {
920 imul(dst, Operand(src), imm32);
924 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
925 EnsureSpace ensure_space(this);
926 if (is_int8(imm32)) {
928 emit_operand(dst, src);
932 emit_operand(dst, src);
938 void Assembler::inc(Register dst) {
939 EnsureSpace ensure_space(this);
940 EMIT(0x40 | dst.code());
944 void Assembler::inc(const Operand& dst) {
945 EnsureSpace ensure_space(this);
947 emit_operand(eax, dst);
951 void Assembler::lea(Register dst, const Operand& src) {
952 EnsureSpace ensure_space(this);
954 emit_operand(dst, src);
958 void Assembler::mul(Register src) {
959 EnsureSpace ensure_space(this);
961 EMIT(0xE0 | src.code());
965 void Assembler::neg(Register dst) {
966 EnsureSpace ensure_space(this);
968 EMIT(0xD8 | dst.code());
972 void Assembler::neg(const Operand& dst) {
973 EnsureSpace ensure_space(this);
975 emit_operand(ebx, dst);
979 void Assembler::not_(Register dst) {
980 EnsureSpace ensure_space(this);
982 EMIT(0xD0 | dst.code());
986 void Assembler::not_(const Operand& dst) {
987 EnsureSpace ensure_space(this);
989 emit_operand(edx, dst);
993 void Assembler::or_(Register dst, int32_t imm32) {
994 EnsureSpace ensure_space(this);
995 emit_arith(1, Operand(dst), Immediate(imm32));
999 void Assembler::or_(Register dst, const Operand& src) {
1000 EnsureSpace ensure_space(this);
1002 emit_operand(dst, src);
1006 void Assembler::or_(const Operand& dst, const Immediate& x) {
1007 EnsureSpace ensure_space(this);
1008 emit_arith(1, dst, x);
1012 void Assembler::or_(const Operand& dst, Register src) {
1013 EnsureSpace ensure_space(this);
1015 emit_operand(src, dst);
1019 void Assembler::rcl(Register dst, uint8_t imm8) {
1020 EnsureSpace ensure_space(this);
1021 DCHECK(is_uint5(imm8)); // illegal shift count
1024 EMIT(0xD0 | dst.code());
1027 EMIT(0xD0 | dst.code());
1033 void Assembler::rcr(Register dst, uint8_t imm8) {
1034 EnsureSpace ensure_space(this);
1035 DCHECK(is_uint5(imm8)); // illegal shift count
1038 EMIT(0xD8 | dst.code());
1041 EMIT(0xD8 | dst.code());
1047 void Assembler::ror(const Operand& dst, uint8_t imm8) {
1048 EnsureSpace ensure_space(this);
1049 DCHECK(is_uint5(imm8)); // illegal shift count
1052 emit_operand(ecx, dst);
1055 emit_operand(ecx, dst);
1061 void Assembler::ror_cl(const Operand& dst) {
1062 EnsureSpace ensure_space(this);
1064 emit_operand(ecx, dst);
1068 void Assembler::sar(const Operand& dst, uint8_t imm8) {
1069 EnsureSpace ensure_space(this);
1070 DCHECK(is_uint5(imm8)); // illegal shift count
1073 emit_operand(edi, dst);
1076 emit_operand(edi, dst);
1082 void Assembler::sar_cl(const Operand& dst) {
1083 EnsureSpace ensure_space(this);
1085 emit_operand(edi, dst);
1089 void Assembler::sbb(Register dst, const Operand& src) {
1090 EnsureSpace ensure_space(this);
1092 emit_operand(dst, src);
1096 void Assembler::shld(Register dst, const Operand& src) {
1097 EnsureSpace ensure_space(this);
1100 emit_operand(dst, src);
1104 void Assembler::shl(const Operand& dst, uint8_t imm8) {
1105 EnsureSpace ensure_space(this);
1106 DCHECK(is_uint5(imm8)); // illegal shift count
1109 emit_operand(esp, dst);
1112 emit_operand(esp, dst);
1118 void Assembler::shl_cl(const Operand& dst) {
1119 EnsureSpace ensure_space(this);
1121 emit_operand(esp, dst);
1125 void Assembler::shrd(Register dst, const Operand& src) {
1126 EnsureSpace ensure_space(this);
1129 emit_operand(dst, src);
1133 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1134 EnsureSpace ensure_space(this);
1135 DCHECK(is_uint5(imm8)); // illegal shift count
1138 emit_operand(ebp, dst);
1141 emit_operand(ebp, dst);
1147 void Assembler::shr_cl(const Operand& dst) {
1148 EnsureSpace ensure_space(this);
1150 emit_operand(ebp, dst);
1154 void Assembler::sub(const Operand& dst, const Immediate& x) {
1155 EnsureSpace ensure_space(this);
1156 emit_arith(5, dst, x);
1160 void Assembler::sub(Register dst, const Operand& src) {
1161 EnsureSpace ensure_space(this);
1163 emit_operand(dst, src);
1167 void Assembler::sub(const Operand& dst, Register src) {
1168 EnsureSpace ensure_space(this);
1170 emit_operand(src, dst);
1174 void Assembler::test(Register reg, const Immediate& imm) {
1175 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1176 test_b(reg, imm.x_);
1180 EnsureSpace ensure_space(this);
1181 // This is not using emit_arith because test doesn't support
1182 // sign-extension of 8-bit operands.
1187 EMIT(0xC0 | reg.code());
1193 void Assembler::test(Register reg, const Operand& op) {
1194 EnsureSpace ensure_space(this);
1196 emit_operand(reg, op);
1200 void Assembler::test_b(Register reg, const Operand& op) {
1201 CHECK(reg.is_byte_register());
1202 EnsureSpace ensure_space(this);
1204 emit_operand(reg, op);
1208 void Assembler::test(const Operand& op, const Immediate& imm) {
1209 if (op.is_reg_only()) {
1210 test(op.reg(), imm);
1213 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1214 return test_b(op, imm.x_);
1216 EnsureSpace ensure_space(this);
1218 emit_operand(eax, op);
1223 void Assembler::test_b(Register reg, uint8_t imm8) {
1224 EnsureSpace ensure_space(this);
1225 // Only use test against byte for registers that have a byte
1226 // variant: eax, ebx, ecx, and edx.
1230 } else if (reg.is_byte_register()) {
1231 emit_arith_b(0xF6, 0xC0, reg, imm8);
1234 EMIT(0xC0 | reg.code());
1240 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1241 if (op.is_reg_only()) {
1242 test_b(op.reg(), imm8);
1245 EnsureSpace ensure_space(this);
1247 emit_operand(eax, op);
1252 void Assembler::xor_(Register dst, int32_t imm32) {
1253 EnsureSpace ensure_space(this);
1254 emit_arith(6, Operand(dst), Immediate(imm32));
1258 void Assembler::xor_(Register dst, const Operand& src) {
1259 EnsureSpace ensure_space(this);
1261 emit_operand(dst, src);
1265 void Assembler::xor_(const Operand& dst, Register src) {
1266 EnsureSpace ensure_space(this);
1268 emit_operand(src, dst);
1272 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1273 EnsureSpace ensure_space(this);
1274 emit_arith(6, dst, x);
1278 void Assembler::bt(const Operand& dst, Register src) {
1279 EnsureSpace ensure_space(this);
1282 emit_operand(src, dst);
1286 void Assembler::bts(const Operand& dst, Register src) {
1287 EnsureSpace ensure_space(this);
1290 emit_operand(src, dst);
1294 void Assembler::bsr(Register dst, const Operand& src) {
1295 EnsureSpace ensure_space(this);
1298 emit_operand(dst, src);
1302 void Assembler::hlt() {
1303 EnsureSpace ensure_space(this);
1308 void Assembler::int3() {
1309 EnsureSpace ensure_space(this);
1314 void Assembler::nop() {
1315 EnsureSpace ensure_space(this);
1320 void Assembler::ret(int imm16) {
1321 EnsureSpace ensure_space(this);
1322 DCHECK(is_uint16(imm16));
1328 EMIT((imm16 >> 8) & 0xFF);
1333 void Assembler::ud2() {
1334 EnsureSpace ensure_space(this);
1340 // Labels refer to positions in the (to be) generated code.
1341 // There are bound, linked, and unused labels.
1343 // Bound labels refer to known positions in the already
1344 // generated code. pos() is the position the label refers to.
1346 // Linked labels refer to unknown positions in the code
1347 // to be generated; pos() is the position of the 32bit
1348 // Displacement of the last instruction using the label.
1351 void Assembler::print(Label* L) {
1352 if (L->is_unused()) {
1353 PrintF("unused label\n");
1354 } else if (L->is_bound()) {
1355 PrintF("bound label to %d\n", L->pos());
1356 } else if (L->is_linked()) {
1358 PrintF("unbound label");
1359 while (l.is_linked()) {
1360 Displacement disp = disp_at(&l);
1361 PrintF("@ %d ", l.pos());
1367 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1372 void Assembler::bind_to(Label* L, int pos) {
1373 EnsureSpace ensure_space(this);
1374 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1375 while (L->is_linked()) {
1376 Displacement disp = disp_at(L);
1377 int fixup_pos = L->pos();
1378 if (disp.type() == Displacement::CODE_ABSOLUTE) {
1379 long_at_put(fixup_pos, reinterpret_cast<int>(buffer_ + pos));
1380 internal_reference_positions_.push_back(fixup_pos);
1381 } else if (disp.type() == Displacement::CODE_RELATIVE) {
1382 // Relative to Code* heap object pointer.
1383 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1385 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1386 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1388 // Relative address, relative to point after address.
1389 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1390 long_at_put(fixup_pos, imm32);
1394 while (L->is_near_linked()) {
1395 int fixup_pos = L->near_link_pos();
1396 int offset_to_next =
1397 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1398 DCHECK(offset_to_next <= 0);
1399 // Relative address, relative to point after address.
1400 int disp = pos - fixup_pos - sizeof(int8_t);
1401 CHECK(0 <= disp && disp <= 127);
1402 set_byte_at(fixup_pos, disp);
1403 if (offset_to_next < 0) {
1404 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1413 void Assembler::bind(Label* L) {
1414 EnsureSpace ensure_space(this);
1415 DCHECK(!L->is_bound()); // label can only be bound once
1416 bind_to(L, pc_offset());
1420 void Assembler::call(Label* L) {
1421 positions_recorder()->WriteRecordedPositions();
1422 EnsureSpace ensure_space(this);
1423 if (L->is_bound()) {
1424 const int long_size = 5;
1425 int offs = L->pos() - pc_offset();
1427 // 1110 1000 #32-bit disp.
1429 emit(offs - long_size);
1431 // 1110 1000 #32-bit disp.
1433 emit_disp(L, Displacement::OTHER);
1438 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1439 positions_recorder()->WriteRecordedPositions();
1440 EnsureSpace ensure_space(this);
1441 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1443 if (RelocInfo::IsRuntimeEntry(rmode)) {
1444 emit(reinterpret_cast<uint32_t>(entry), rmode);
1446 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1451 int Assembler::CallSize(const Operand& adr) {
1452 // Call size is 1 (opcode) + adr.len_ (operand).
1453 return 1 + adr.len_;
1457 void Assembler::call(const Operand& adr) {
1458 positions_recorder()->WriteRecordedPositions();
1459 EnsureSpace ensure_space(this);
1461 emit_operand(edx, adr);
1465 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1466 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1470 void Assembler::call(Handle<Code> code,
1471 RelocInfo::Mode rmode,
1472 TypeFeedbackId ast_id) {
1473 positions_recorder()->WriteRecordedPositions();
1474 EnsureSpace ensure_space(this);
1475 DCHECK(RelocInfo::IsCodeTarget(rmode)
1476 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1478 emit(code, rmode, ast_id);
1482 void Assembler::jmp(Label* L, Label::Distance distance) {
1483 EnsureSpace ensure_space(this);
1484 if (L->is_bound()) {
1485 const int short_size = 2;
1486 const int long_size = 5;
1487 int offs = L->pos() - pc_offset();
1489 if (is_int8(offs - short_size)) {
1490 // 1110 1011 #8-bit disp.
1492 EMIT((offs - short_size) & 0xFF);
1494 // 1110 1001 #32-bit disp.
1496 emit(offs - long_size);
1498 } else if (distance == Label::kNear) {
1502 // 1110 1001 #32-bit disp.
1504 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1509 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1510 EnsureSpace ensure_space(this);
1511 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1513 if (RelocInfo::IsRuntimeEntry(rmode)) {
1514 emit(reinterpret_cast<uint32_t>(entry), rmode);
1516 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1521 void Assembler::jmp(const Operand& adr) {
1522 EnsureSpace ensure_space(this);
1524 emit_operand(esp, adr);
1528 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1529 EnsureSpace ensure_space(this);
1530 DCHECK(RelocInfo::IsCodeTarget(rmode));
1536 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1537 EnsureSpace ensure_space(this);
1538 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1539 if (L->is_bound()) {
1540 const int short_size = 2;
1541 const int long_size = 6;
1542 int offs = L->pos() - pc_offset();
1544 if (is_int8(offs - short_size)) {
1545 // 0111 tttn #8-bit disp
1547 EMIT((offs - short_size) & 0xFF);
1549 // 0000 1111 1000 tttn #32-bit disp
1552 emit(offs - long_size);
1554 } else if (distance == Label::kNear) {
1558 // 0000 1111 1000 tttn #32-bit disp
1559 // Note: could eliminate cond. jumps to this jump if condition
1560 // is the same however, seems to be rather unlikely case.
1563 emit_disp(L, Displacement::OTHER);
1568 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1569 EnsureSpace ensure_space(this);
1570 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1571 // 0000 1111 1000 tttn #32-bit disp.
1574 if (RelocInfo::IsRuntimeEntry(rmode)) {
1575 emit(reinterpret_cast<uint32_t>(entry), rmode);
1577 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1582 void Assembler::j(Condition cc, Handle<Code> code) {
1583 EnsureSpace ensure_space(this);
1584 // 0000 1111 1000 tttn #32-bit disp
1587 emit(code, RelocInfo::CODE_TARGET);
1591 // FPU instructions.
1593 void Assembler::fld(int i) {
1594 EnsureSpace ensure_space(this);
1595 emit_farith(0xD9, 0xC0, i);
1599 void Assembler::fstp(int i) {
1600 EnsureSpace ensure_space(this);
1601 emit_farith(0xDD, 0xD8, i);
1605 void Assembler::fld1() {
1606 EnsureSpace ensure_space(this);
1612 void Assembler::fldpi() {
1613 EnsureSpace ensure_space(this);
1619 void Assembler::fldz() {
1620 EnsureSpace ensure_space(this);
1626 void Assembler::fldln2() {
1627 EnsureSpace ensure_space(this);
1633 void Assembler::fld_s(const Operand& adr) {
1634 EnsureSpace ensure_space(this);
1636 emit_operand(eax, adr);
1640 void Assembler::fld_d(const Operand& adr) {
1641 EnsureSpace ensure_space(this);
1643 emit_operand(eax, adr);
1647 void Assembler::fstp_s(const Operand& adr) {
1648 EnsureSpace ensure_space(this);
1650 emit_operand(ebx, adr);
1654 void Assembler::fst_s(const Operand& adr) {
1655 EnsureSpace ensure_space(this);
1657 emit_operand(edx, adr);
1661 void Assembler::fstp_d(const Operand& adr) {
1662 EnsureSpace ensure_space(this);
1664 emit_operand(ebx, adr);
1668 void Assembler::fst_d(const Operand& adr) {
1669 EnsureSpace ensure_space(this);
1671 emit_operand(edx, adr);
1675 void Assembler::fild_s(const Operand& adr) {
1676 EnsureSpace ensure_space(this);
1678 emit_operand(eax, adr);
1682 void Assembler::fild_d(const Operand& adr) {
1683 EnsureSpace ensure_space(this);
1685 emit_operand(ebp, adr);
1689 void Assembler::fistp_s(const Operand& adr) {
1690 EnsureSpace ensure_space(this);
1692 emit_operand(ebx, adr);
1696 void Assembler::fisttp_s(const Operand& adr) {
1697 DCHECK(IsEnabled(SSE3));
1698 EnsureSpace ensure_space(this);
1700 emit_operand(ecx, adr);
1704 void Assembler::fisttp_d(const Operand& adr) {
1705 DCHECK(IsEnabled(SSE3));
1706 EnsureSpace ensure_space(this);
1708 emit_operand(ecx, adr);
1712 void Assembler::fist_s(const Operand& adr) {
1713 EnsureSpace ensure_space(this);
1715 emit_operand(edx, adr);
1719 void Assembler::fistp_d(const Operand& adr) {
1720 EnsureSpace ensure_space(this);
1722 emit_operand(edi, adr);
1726 void Assembler::fabs() {
1727 EnsureSpace ensure_space(this);
1733 void Assembler::fchs() {
1734 EnsureSpace ensure_space(this);
1740 void Assembler::fcos() {
1741 EnsureSpace ensure_space(this);
1747 void Assembler::fsin() {
1748 EnsureSpace ensure_space(this);
1754 void Assembler::fptan() {
1755 EnsureSpace ensure_space(this);
1761 void Assembler::fyl2x() {
1762 EnsureSpace ensure_space(this);
1768 void Assembler::f2xm1() {
1769 EnsureSpace ensure_space(this);
1775 void Assembler::fscale() {
1776 EnsureSpace ensure_space(this);
1782 void Assembler::fninit() {
1783 EnsureSpace ensure_space(this);
1789 void Assembler::fadd(int i) {
1790 EnsureSpace ensure_space(this);
1791 emit_farith(0xDC, 0xC0, i);
1795 void Assembler::fadd_i(int i) {
1796 EnsureSpace ensure_space(this);
1797 emit_farith(0xD8, 0xC0, i);
1801 void Assembler::fsub(int i) {
1802 EnsureSpace ensure_space(this);
1803 emit_farith(0xDC, 0xE8, i);
1807 void Assembler::fsub_i(int i) {
1808 EnsureSpace ensure_space(this);
1809 emit_farith(0xD8, 0xE0, i);
1813 void Assembler::fisub_s(const Operand& adr) {
1814 EnsureSpace ensure_space(this);
1816 emit_operand(esp, adr);
1820 void Assembler::fmul_i(int i) {
1821 EnsureSpace ensure_space(this);
1822 emit_farith(0xD8, 0xC8, i);
1826 void Assembler::fmul(int i) {
1827 EnsureSpace ensure_space(this);
1828 emit_farith(0xDC, 0xC8, i);
1832 void Assembler::fdiv(int i) {
1833 EnsureSpace ensure_space(this);
1834 emit_farith(0xDC, 0xF8, i);
1838 void Assembler::fdiv_i(int i) {
1839 EnsureSpace ensure_space(this);
1840 emit_farith(0xD8, 0xF0, i);
1844 void Assembler::faddp(int i) {
1845 EnsureSpace ensure_space(this);
1846 emit_farith(0xDE, 0xC0, i);
1850 void Assembler::fsubp(int i) {
1851 EnsureSpace ensure_space(this);
1852 emit_farith(0xDE, 0xE8, i);
1856 void Assembler::fsubrp(int i) {
1857 EnsureSpace ensure_space(this);
1858 emit_farith(0xDE, 0xE0, i);
1862 void Assembler::fmulp(int i) {
1863 EnsureSpace ensure_space(this);
1864 emit_farith(0xDE, 0xC8, i);
1868 void Assembler::fdivp(int i) {
1869 EnsureSpace ensure_space(this);
1870 emit_farith(0xDE, 0xF8, i);
1874 void Assembler::fprem() {
1875 EnsureSpace ensure_space(this);
1881 void Assembler::fprem1() {
1882 EnsureSpace ensure_space(this);
1888 void Assembler::fxch(int i) {
1889 EnsureSpace ensure_space(this);
1890 emit_farith(0xD9, 0xC8, i);
1894 void Assembler::fincstp() {
1895 EnsureSpace ensure_space(this);
1901 void Assembler::ffree(int i) {
1902 EnsureSpace ensure_space(this);
1903 emit_farith(0xDD, 0xC0, i);
1907 void Assembler::ftst() {
1908 EnsureSpace ensure_space(this);
1914 void Assembler::fucomp(int i) {
1915 EnsureSpace ensure_space(this);
1916 emit_farith(0xDD, 0xE8, i);
1920 void Assembler::fucompp() {
1921 EnsureSpace ensure_space(this);
1927 void Assembler::fucomi(int i) {
1928 EnsureSpace ensure_space(this);
1934 void Assembler::fucomip() {
1935 EnsureSpace ensure_space(this);
1941 void Assembler::fcompp() {
1942 EnsureSpace ensure_space(this);
1948 void Assembler::fnstsw_ax() {
1949 EnsureSpace ensure_space(this);
1955 void Assembler::fwait() {
1956 EnsureSpace ensure_space(this);
1961 void Assembler::frndint() {
1962 EnsureSpace ensure_space(this);
1968 void Assembler::fnclex() {
1969 EnsureSpace ensure_space(this);
1975 void Assembler::sahf() {
1976 EnsureSpace ensure_space(this);
1981 void Assembler::setcc(Condition cc, Register reg) {
1982 DCHECK(reg.is_byte_register());
1983 EnsureSpace ensure_space(this);
1986 EMIT(0xC0 | reg.code());
1990 void Assembler::cvttss2si(Register dst, const Operand& src) {
1991 EnsureSpace ensure_space(this);
1995 emit_operand(dst, src);
1999 void Assembler::cvttsd2si(Register dst, const Operand& src) {
2000 EnsureSpace ensure_space(this);
2004 emit_operand(dst, src);
2008 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
2009 EnsureSpace ensure_space(this);
2013 emit_sse_operand(dst, src);
2017 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
2018 EnsureSpace ensure_space(this);
2022 emit_sse_operand(dst, src);
2026 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2027 EnsureSpace ensure_space(this);
2031 emit_sse_operand(dst, src);
2035 void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
2036 EnsureSpace ensure_space(this);
2040 emit_sse_operand(dst, src);
2044 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2045 EnsureSpace ensure_space(this);
2049 emit_sse_operand(dst, src);
2053 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2054 EnsureSpace ensure_space(this);
2058 emit_sse_operand(dst, src);
2062 void Assembler::subsd(XMMRegister dst, const Operand& src) {
2063 EnsureSpace ensure_space(this);
2067 emit_sse_operand(dst, src);
2071 void Assembler::divsd(XMMRegister dst, const Operand& src) {
2072 EnsureSpace ensure_space(this);
2076 emit_sse_operand(dst, src);
2080 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2081 EnsureSpace ensure_space(this);
2085 emit_sse_operand(dst, src);
2089 void Assembler::andps(XMMRegister dst, const Operand& src) {
2090 EnsureSpace ensure_space(this);
2093 emit_sse_operand(dst, src);
2097 void Assembler::orps(XMMRegister dst, const Operand& src) {
2098 EnsureSpace ensure_space(this);
2101 emit_sse_operand(dst, src);
2105 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2106 EnsureSpace ensure_space(this);
2109 emit_sse_operand(dst, src);
2113 void Assembler::addps(XMMRegister dst, const Operand& src) {
2114 EnsureSpace ensure_space(this);
2117 emit_sse_operand(dst, src);
2121 void Assembler::subps(XMMRegister dst, const Operand& src) {
2122 EnsureSpace ensure_space(this);
2125 emit_sse_operand(dst, src);
2129 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2130 EnsureSpace ensure_space(this);
2133 emit_sse_operand(dst, src);
2137 void Assembler::divps(XMMRegister dst, const Operand& src) {
2138 EnsureSpace ensure_space(this);
2141 emit_sse_operand(dst, src);
2145 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2146 EnsureSpace ensure_space(this);
2150 emit_sse_operand(dst, src);
2154 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2155 EnsureSpace ensure_space(this);
2159 emit_sse_operand(dst, src);
2163 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2164 EnsureSpace ensure_space(this);
2168 emit_sse_operand(dst, src);
2172 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2173 EnsureSpace ensure_space(this);
2177 emit_sse_operand(dst, src);
2181 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2182 DCHECK(IsEnabled(SSE4_1));
2183 EnsureSpace ensure_space(this);
2188 emit_sse_operand(dst, src);
2189 // Mask precision exeption.
2190 EMIT(static_cast<byte>(mode) | 0x8);
2194 void Assembler::movmskpd(Register dst, XMMRegister src) {
2195 EnsureSpace ensure_space(this);
2199 emit_sse_operand(dst, src);
2203 void Assembler::movmskps(Register dst, XMMRegister src) {
2204 EnsureSpace ensure_space(this);
2207 emit_sse_operand(dst, src);
2211 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2212 EnsureSpace ensure_space(this);
2216 emit_sse_operand(dst, src);
2220 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2221 EnsureSpace ensure_space(this);
2225 emit_sse_operand(dst, src);
2229 void Assembler::punpckhdq(XMMRegister dst, XMMRegister src) {
2230 EnsureSpace ensure_space(this);
2234 emit_sse_operand(dst, src);
2238 void Assembler::maxsd(XMMRegister dst, const Operand& src) {
2239 EnsureSpace ensure_space(this);
2243 emit_sse_operand(dst, src);
2247 void Assembler::minsd(XMMRegister dst, const Operand& src) {
2248 EnsureSpace ensure_space(this);
2252 emit_sse_operand(dst, src);
2256 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2257 EnsureSpace ensure_space(this);
2261 emit_sse_operand(dst, src);
2266 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2267 EnsureSpace ensure_space(this);
2270 emit_sse_operand(dst, src);
2274 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2275 DCHECK(is_uint8(imm8));
2276 EnsureSpace ensure_space(this);
2279 emit_sse_operand(dst, src);
2284 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2285 EnsureSpace ensure_space(this);
2289 emit_sse_operand(src, dst);
2293 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2294 EnsureSpace ensure_space(this);
2298 emit_sse_operand(dst, src);
2302 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2303 EnsureSpace ensure_space(this);
2307 emit_sse_operand(src, dst);
2311 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2312 EnsureSpace ensure_space(this);
2316 emit_sse_operand(dst, src);
2320 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2321 DCHECK(IsEnabled(SSE4_1));
2322 EnsureSpace ensure_space(this);
2327 emit_sse_operand(dst, src);
2331 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2332 EnsureSpace ensure_space(this);
2336 emit_sse_operand(src, dst);
2340 void Assembler::prefetch(const Operand& src, int level) {
2341 DCHECK(is_uint2(level));
2342 EnsureSpace ensure_space(this);
2345 // Emit hint number in Reg position of RegR/M.
2346 XMMRegister code = XMMRegister::from_code(level);
2347 emit_sse_operand(code, src);
2351 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2352 EnsureSpace ensure_space(this);
2353 EMIT(0xF2); // double
2355 EMIT(0x11); // store
2356 emit_sse_operand(src, dst);
2360 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2361 EnsureSpace ensure_space(this);
2362 EMIT(0xF2); // double
2365 emit_sse_operand(dst, src);
2369 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2370 EnsureSpace ensure_space(this);
2371 EMIT(0xF3); // float
2373 EMIT(0x11); // store
2374 emit_sse_operand(src, dst);
2378 void Assembler::movss(XMMRegister dst, const Operand& src) {
2379 EnsureSpace ensure_space(this);
2380 EMIT(0xF3); // float
2383 emit_sse_operand(dst, src);
2387 void Assembler::movd(XMMRegister dst, const Operand& src) {
2388 EnsureSpace ensure_space(this);
2392 emit_sse_operand(dst, src);
2396 void Assembler::movd(const Operand& dst, XMMRegister src) {
2397 EnsureSpace ensure_space(this);
2401 emit_sse_operand(src, dst);
2405 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2406 DCHECK(IsEnabled(SSE4_1));
2407 DCHECK(is_uint8(imm8));
2408 EnsureSpace ensure_space(this);
2413 emit_sse_operand(src, dst);
2418 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2419 EnsureSpace ensure_space(this);
2423 emit_sse_operand(dst, src);
2427 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2428 EnsureSpace ensure_space(this);
2432 emit_sse_operand(dst, src);
2436 void Assembler::por(XMMRegister dst, XMMRegister src) {
2437 EnsureSpace ensure_space(this);
2441 emit_sse_operand(dst, src);
2445 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2446 DCHECK(IsEnabled(SSE4_1));
2447 EnsureSpace ensure_space(this);
2452 emit_sse_operand(dst, src);
2456 void Assembler::pslld(XMMRegister reg, int8_t shift) {
2457 EnsureSpace ensure_space(this);
2461 emit_sse_operand(esi, reg); // esi == 6
2466 void Assembler::psrld(XMMRegister reg, int8_t shift) {
2467 EnsureSpace ensure_space(this);
2471 emit_sse_operand(edx, reg); // edx == 2
2476 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2477 EnsureSpace ensure_space(this);
2481 emit_sse_operand(esi, reg); // esi == 6
2486 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2487 EnsureSpace ensure_space(this);
2491 emit_sse_operand(dst, src);
2495 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2496 EnsureSpace ensure_space(this);
2500 emit_sse_operand(edx, reg); // edx == 2
2505 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2506 EnsureSpace ensure_space(this);
2510 emit_sse_operand(dst, src);
2514 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2515 EnsureSpace ensure_space(this);
2519 emit_sse_operand(dst, src);
2524 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2525 DCHECK(IsEnabled(SSE4_1));
2526 EnsureSpace ensure_space(this);
2531 emit_sse_operand(src, dst);
2536 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2537 DCHECK(IsEnabled(SSE4_1));
2538 EnsureSpace ensure_space(this);
2543 emit_sse_operand(dst, src);
2548 void Assembler::addss(XMMRegister dst, const Operand& src) {
2549 EnsureSpace ensure_space(this);
2553 emit_sse_operand(dst, src);
2557 void Assembler::subss(XMMRegister dst, const Operand& src) {
2558 EnsureSpace ensure_space(this);
2562 emit_sse_operand(dst, src);
2566 void Assembler::mulss(XMMRegister dst, const Operand& src) {
2567 EnsureSpace ensure_space(this);
2571 emit_sse_operand(dst, src);
2575 void Assembler::divss(XMMRegister dst, const Operand& src) {
2576 EnsureSpace ensure_space(this);
2580 emit_sse_operand(dst, src);
2584 void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
2585 EnsureSpace ensure_space(this);
2588 emit_sse_operand(dst, src);
2593 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
2594 const Operand& src2) {
2595 DCHECK(IsEnabled(FMA3));
2596 EnsureSpace ensure_space(this);
2597 emit_vex_prefix(src1, kLIG, k66, k0F38, kW1);
2599 emit_sse_operand(dst, src2);
2603 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
2604 const Operand& src2) {
2605 DCHECK(IsEnabled(FMA3));
2606 EnsureSpace ensure_space(this);
2607 emit_vex_prefix(src1, kLIG, k66, k0F38, kW0);
2609 emit_sse_operand(dst, src2);
2613 void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1,
2614 const Operand& src2) {
2615 DCHECK(IsEnabled(AVX));
2616 EnsureSpace ensure_space(this);
2617 emit_vex_prefix(src1, kLIG, kF2, k0F, kWIG);
2619 emit_sse_operand(dst, src2);
2623 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2624 Register ireg = { reg.code() };
2625 emit_operand(ireg, adr);
2629 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2630 EMIT(0xC0 | dst.code() << 3 | src.code());
2634 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2635 EMIT(0xC0 | dst.code() << 3 | src.code());
2639 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2640 EMIT(0xC0 | (dst.code() << 3) | src.code());
2644 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp,
2645 LeadingOpcode mm, VexW w) {
2646 if (mm != k0F || w != kW0) {
2649 EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp);
2652 EMIT(((~vreg.code()) << 3) | l | pp);
2657 void Assembler::GrowBuffer() {
2658 DCHECK(buffer_overflow());
2659 if (!own_buffer_) FATAL("external code buffer is too small");
2661 // Compute new buffer size.
2662 CodeDesc desc; // the new buffer
2663 desc.buffer_size = 2 * buffer_size_;
2665 // Some internal data structures overflow for very large buffers,
2666 // they must ensure that kMaximalBufferSize is not too large.
2667 if ((desc.buffer_size > kMaximalBufferSize) ||
2668 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2669 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2672 // Set up new buffer.
2673 desc.buffer = NewArray<byte>(desc.buffer_size);
2674 desc.instr_size = pc_offset();
2675 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2677 // Clear the buffer in debug mode. Use 'int3' instructions to make
2678 // sure to get into problems if we ever run uninitialized code.
2680 memset(desc.buffer, 0xCC, desc.buffer_size);
2684 int pc_delta = desc.buffer - buffer_;
2685 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2686 MemMove(desc.buffer, buffer_, desc.instr_size);
2687 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2691 DeleteArray(buffer_);
2692 buffer_ = desc.buffer;
2693 buffer_size_ = desc.buffer_size;
2695 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2696 reloc_info_writer.last_pc() + pc_delta);
2698 // Relocate internal references.
2699 for (auto pos : internal_reference_positions_) {
2700 int32_t* p = reinterpret_cast<int32_t*>(buffer_ + pos);
2704 DCHECK(!buffer_overflow());
2708 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2709 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2710 DCHECK(is_uint8(imm8));
2711 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
2713 EMIT(op2 | dst.code());
2718 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2719 DCHECK((0 <= sel) && (sel <= 7));
2720 Register ireg = { sel };
2722 EMIT(0x83); // using a sign-extended 8-bit immediate.
2723 emit_operand(ireg, dst);
2725 } else if (dst.is_reg(eax)) {
2726 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2729 EMIT(0x81); // using a literal 32-bit immediate.
2730 emit_operand(ireg, dst);
2736 void Assembler::emit_operand(Register reg, const Operand& adr) {
2737 const unsigned length = adr.len_;
2740 // Emit updated ModRM byte containing the given register.
2741 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2743 // Emit the rest of the encoded operand.
2744 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2747 // Emit relocation information if necessary.
2748 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2749 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2750 RecordRelocInfo(adr.rmode_);
2751 if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) { // Fixup for labels
2752 emit_label(*reinterpret_cast<Label**>(pc_));
2754 pc_ += sizeof(int32_t);
2760 void Assembler::emit_label(Label* label) {
2761 if (label->is_bound()) {
2762 internal_reference_positions_.push_back(pc_offset());
2763 emit(reinterpret_cast<uint32_t>(buffer_ + label->pos()));
2765 emit_disp(label, Displacement::CODE_ABSOLUTE);
2770 void Assembler::emit_farith(int b1, int b2, int i) {
2771 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2772 DCHECK(0 <= i && i < 8); // illegal stack offset
2778 void Assembler::db(uint8_t data) {
2779 EnsureSpace ensure_space(this);
2784 void Assembler::dd(uint32_t data) {
2785 EnsureSpace ensure_space(this);
2790 void Assembler::dd(Label* label) {
2791 EnsureSpace ensure_space(this);
2792 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2797 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2798 DCHECK(!RelocInfo::IsNone(rmode));
2799 // Don't record external references unless the heap will be serialized.
2800 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2801 !serializer_enabled() && !emit_debug_code()) {
2804 RelocInfo rinfo(pc_, rmode, data, NULL);
2805 reloc_info_writer.Write(&rinfo);
2809 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2810 // No out-of-line constant pool support.
2811 DCHECK(!FLAG_enable_ool_constant_pool);
2812 return isolate->factory()->empty_constant_pool_array();
2816 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2817 // No out-of-line constant pool support.
2818 DCHECK(!FLAG_enable_ool_constant_pool);
2823 #ifdef GENERATED_CODE_COVERAGE
2824 static FILE* coverage_log = NULL;
2827 static void InitCoverageLog() {
2828 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2829 if (file_name != NULL) {
2830 coverage_log = fopen(file_name, "aw+");
2835 void LogGeneratedCodeCoverage(const char* file_line) {
2836 const char* return_address = (&file_line)[-1];
2837 char* push_insn = const_cast<char*>(return_address - 12);
2838 push_insn[0] = 0xeb; // Relative branch insn.
2839 push_insn[1] = 13; // Skip over coverage insns.
2840 if (coverage_log != NULL) {
2841 fprintf(coverage_log, "%s\n", file_line);
2842 fflush(coverage_log);
2848 } } // namespace v8::internal
2850 #endif // V8_TARGET_ARCH_IA32