deps/v8/src/compiler/x64/instruction-codes-x64.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
   6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // X64-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V) \
  15   V(X64Add)                        \
  16   V(X64Add32)                      \
  17   V(X64And)                        \
  18   V(X64And32)                      \
  19   V(X64Cmp)                        \
  20   V(X64Cmp32)                      \
  21   V(X64Test)                       \
  22   V(X64Test32)                     \
  23   V(X64Or)                         \
  24   V(X64Or32)                       \
  25   V(X64Xor)                        \
  26   V(X64Xor32)                      \
  27   V(X64Sub)                        \
  28   V(X64Sub32)                      \
  29   V(X64Imul)                       \
  30   V(X64Imul32)                     \
  31   V(X64ImulHigh32)                 \
  32   V(X64UmulHigh32)                 \
  33   V(X64Idiv)                       \
  34   V(X64Idiv32)                     \
  35   V(X64Udiv)                       \
  36   V(X64Udiv32)                     \
  37   V(X64Not)                        \
  38   V(X64Not32)                      \
  39   V(X64Neg)                        \
  40   V(X64Neg32)                      \
  41   V(X64Shl)                        \
  42   V(X64Shl32)                      \
  43   V(X64Shr)                        \
  44   V(X64Shr32)                      \
  45   V(X64Sar)                        \
  46   V(X64Sar32)                      \
  47   V(X64Ror)                        \
  48   V(X64Ror32)                      \
  49   V(X64Lzcnt32)                    \
  50   V(SSEFloat64Cmp)                 \
  51   V(SSEFloat64Add)                 \
  52   V(SSEFloat64Sub)                 \
  53   V(SSEFloat64Mul)                 \
  54   V(SSEFloat64Div)                 \
  55   V(SSEFloat64Mod)                 \
  56   V(SSEFloat64Sqrt)                \
  57   V(SSEFloat64Round)               \
  58   V(SSEFloat64Max)                 \
  59   V(SSEFloat64Min)                 \
  60   V(SSECvtss2sd)                   \
  61   V(SSECvtsd2ss)                   \
  62   V(SSEFloat64ToInt32)             \
  63   V(SSEFloat64ToUint32)            \
  64   V(SSEInt32ToFloat64)             \
  65   V(SSEUint32ToFloat64)            \
  66   V(SSEFloat64ExtractLowWord32)    \
  67   V(SSEFloat64ExtractHighWord32)   \
  68   V(SSEFloat64InsertLowWord32)     \
  69   V(SSEFloat64InsertHighWord32)    \
  70   V(SSEFloat64LoadLowWord32)       \
  71   V(AVXFloat64Add)                 \
  72   V(AVXFloat64Sub)                 \
  73   V(AVXFloat64Mul)                 \
  74   V(AVXFloat64Div)                 \
  75   V(AVXFloat64Max)                 \
  76   V(AVXFloat64Min)                 \
  77   V(X64Movsxbl)                    \
  78   V(X64Movzxbl)                    \
  79   V(X64Movb)                       \
  80   V(X64Movsxwl)                    \
  81   V(X64Movzxwl)                    \
  82   V(X64Movw)                       \
  83   V(X64Movl)                       \
  84   V(X64Movsxlq)                    \
  85   V(X64Movq)                       \
  86   V(X64Movsd)                      \
  87   V(X64Movss)                      \
  88   V(X64Lea32)                      \
  89   V(X64Lea)                        \
  90   V(X64Dec32)                      \
  91   V(X64Inc32)                      \
  92   V(X64Push)                       \
  93   V(X64StoreWriteBarrier)          \
  94   V(X64StackCheck)
  95
  96
  97 // Addressing modes represent the "shape" of inputs to an instruction.
  98 // Many instructions support multiple addressing modes. Addressing modes
  99 // are encoded into the InstructionCode of the instruction and tell the
 100 // code generator after register allocation which assembler method to call.
 101 //
 102 // We use the following local notation for addressing modes:
 103 //
 104 // M = memory operand
 105 // R = base register
 106 // N = index register * N for N in {1, 2, 4, 8}
 107 // I = immediate displacement (32-bit signed integer)
 108
 109 #define TARGET_ADDRESSING_MODE_LIST(V) \
 110   V(MR)   /* [%r1            ] */      \
 111   V(MRI)  /* [%r1         + K] */      \
 112   V(MR1)  /* [%r1 + %r2*1    ] */      \
 113   V(MR2)  /* [%r1 + %r2*2    ] */      \
 114   V(MR4)  /* [%r1 + %r2*4    ] */      \
 115   V(MR8)  /* [%r1 + %r2*8    ] */      \
 116   V(MR1I) /* [%r1 + %r2*1 + K] */      \
 117   V(MR2I) /* [%r1 + %r2*2 + K] */      \
 118   V(MR4I) /* [%r1 + %r2*3 + K] */      \
 119   V(MR8I) /* [%r1 + %r2*4 + K] */      \
 120   V(M1)   /* [      %r2*1    ] */      \
 121   V(M2)   /* [      %r2*2    ] */      \
 122   V(M4)   /* [      %r2*4    ] */      \
 123   V(M8)   /* [      %r2*8    ] */      \
 124   V(M1I)  /* [      %r2*1 + K] */      \
 125   V(M2I)  /* [      %r2*2 + K] */      \
 126   V(M4I)  /* [      %r2*4 + K] */      \
 127   V(M8I)  /* [      %r2*8 + K] */
 128
 129 }  // namespace compiler
 130 }  // namespace internal
 131 }  // namespace v8
 132
 133 #endif  // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_