1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
12 // PPC-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
17 V(PPC_AndComplement32) \
18 V(PPC_AndComplement64) \
21 V(PPC_OrComplement32) \
22 V(PPC_OrComplement64) \
29 V(PPC_ShiftRightAlg32) \
30 V(PPC_ShiftRightAlg64) \
35 V(PPC_RotLeftAndMask32) \
36 V(PPC_RotLeftAndClear64) \
37 V(PPC_RotLeftAndClearLeft64) \
38 V(PPC_RotLeftAndClearRight64) \
40 V(PPC_AddWithOverflow32) \
44 V(PPC_SubWithOverflow32) \
68 V(PPC_TruncateFloat64) \
76 V(PPC_ExtendSignWord8) \
77 V(PPC_ExtendSignWord16) \
78 V(PPC_ExtendSignWord32) \
79 V(PPC_Uint32ToUint64) \
81 V(PPC_Int32ToFloat64) \
82 V(PPC_Uint32ToFloat64) \
83 V(PPC_Float32ToFloat64) \
84 V(PPC_Float64ToInt32) \
85 V(PPC_Float64ToUint32) \
86 V(PPC_Float64ToFloat32) \
100 V(PPC_StoreFloat64) \
101 V(PPC_StoreWriteBarrier)
104 // Addressing modes represent the "shape" of inputs to an instruction.
105 // Many instructions support multiple addressing modes. Addressing modes
106 // are encoded into the InstructionCode of the instruction and tell the
107 // code generator after register allocation which assembler method to call.
109 // We use the following local notation for addressing modes:
112 // O = register or stack slot
113 // D = double register
114 // I = immediate (handle, external, int32)
115 // MRI = [register + immediate]
116 // MRR = [register + register]
117 #define TARGET_ADDRESSING_MODE_LIST(V) \
118 V(MRI) /* [%r0 + K] */ \
119 V(MRR) /* [%r0 + %r1] */
121 } // namespace compiler
122 } // namespace internal
125 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_