deps/v8/src/compiler/mips64/instruction-codes-mips64.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
   6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // MIPS64-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V)  \
  15   V(Mips64Add)                      \
  16   V(Mips64Dadd)                     \
  17   V(Mips64Sub)                      \
  18   V(Mips64Dsub)                     \
  19   V(Mips64Mul)                      \
  20   V(Mips64MulHigh)                  \
  21   V(Mips64MulHighU)                 \
  22   V(Mips64Dmul)                     \
  23   V(Mips64Div)                      \
  24   V(Mips64Ddiv)                     \
  25   V(Mips64DivU)                     \
  26   V(Mips64DdivU)                    \
  27   V(Mips64Mod)                      \
  28   V(Mips64Dmod)                     \
  29   V(Mips64ModU)                     \
  30   V(Mips64DmodU)                    \
  31   V(Mips64And)                      \
  32   V(Mips64Or)                       \
  33   V(Mips64Xor)                      \
  34   V(Mips64Clz)                      \
  35   V(Mips64Shl)                      \
  36   V(Mips64Shr)                      \
  37   V(Mips64Sar)                      \
  38   V(Mips64Ext)                      \
  39   V(Mips64Dext)                     \
  40   V(Mips64Dshl)                     \
  41   V(Mips64Dshr)                     \
  42   V(Mips64Dsar)                     \
  43   V(Mips64Ror)                      \
  44   V(Mips64Dror)                     \
  45   V(Mips64Mov)                      \
  46   V(Mips64Tst)                      \
  47   V(Mips64Cmp)                      \
  48   V(Mips64CmpD)                     \
  49   V(Mips64AddD)                     \
  50   V(Mips64SubD)                     \
  51   V(Mips64MulD)                     \
  52   V(Mips64DivD)                     \
  53   V(Mips64ModD)                     \
  54   V(Mips64SqrtD)                    \
  55   V(Mips64Float64RoundDown)         \
  56   V(Mips64Float64RoundTruncate)     \
  57   V(Mips64Float64RoundUp)           \
  58   V(Mips64CvtSD)                    \
  59   V(Mips64CvtDS)                    \
  60   V(Mips64TruncWD)                  \
  61   V(Mips64TruncUwD)                 \
  62   V(Mips64CvtDW)                    \
  63   V(Mips64CvtDUw)                   \
  64   V(Mips64Lb)                       \
  65   V(Mips64Lbu)                      \
  66   V(Mips64Sb)                       \
  67   V(Mips64Lh)                       \
  68   V(Mips64Lhu)                      \
  69   V(Mips64Sh)                       \
  70   V(Mips64Ld)                       \
  71   V(Mips64Lw)                       \
  72   V(Mips64Sw)                       \
  73   V(Mips64Sd)                       \
  74   V(Mips64Lwc1)                     \
  75   V(Mips64Swc1)                     \
  76   V(Mips64Ldc1)                     \
  77   V(Mips64Sdc1)                     \
  78   V(Mips64Float64ExtractLowWord32)  \
  79   V(Mips64Float64ExtractHighWord32) \
  80   V(Mips64Float64InsertLowWord32)   \
  81   V(Mips64Float64InsertHighWord32)  \
  82   V(Mips64Push)                     \
  83   V(Mips64StoreToStackSlot)         \
  84   V(Mips64StackClaim)               \
  85   V(Mips64StoreWriteBarrier)
  86
  87
  88 // Addressing modes represent the "shape" of inputs to an instruction.
  89 // Many instructions support multiple addressing modes. Addressing modes
  90 // are encoded into the InstructionCode of the instruction and tell the
  91 // code generator after register allocation which assembler method to call.
  92 //
  93 // We use the following local notation for addressing modes:
  94 //
  95 // R = register
  96 // O = register or stack slot
  97 // D = double register
  98 // I = immediate (handle, external, int32)
  99 // MRI = [register + immediate]
 100 // MRR = [register + register]
 101 // TODO(plind): Add the new r6 address modes.
 102 #define TARGET_ADDRESSING_MODE_LIST(V) \
 103   V(MRI) /* [%r0 + K] */               \
 104   V(MRR) /* [%r0 + %r1] */
 105
 106
 107 }  // namespace compiler
 108 }  // namespace internal
 109 }  // namespace v8
 110
 111 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_