1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
12 // MIPS-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
44 V(MipsFloat64RoundDown) \
45 V(MipsFloat64RoundTruncate) \
46 V(MipsFloat64RoundUp) \
65 V(MipsFloat64ExtractLowWord32) \
66 V(MipsFloat64ExtractHighWord32) \
67 V(MipsFloat64InsertLowWord32) \
68 V(MipsFloat64InsertHighWord32) \
70 V(MipsStoreToStackSlot) \
72 V(MipsStoreWriteBarrier)
75 // Addressing modes represent the "shape" of inputs to an instruction.
76 // Many instructions support multiple addressing modes. Addressing modes
77 // are encoded into the InstructionCode of the instruction and tell the
78 // code generator after register allocation which assembler method to call.
80 // We use the following local notation for addressing modes:
83 // O = register or stack slot
84 // D = double register
85 // I = immediate (handle, external, int32)
86 // MRI = [register + immediate]
87 // MRR = [register + register]
88 // TODO(plind): Add the new r6 address modes.
89 #define TARGET_ADDRESSING_MODE_LIST(V) \
90 V(MRI) /* [%r0 + K] */ \
91 V(MRR) /* [%r0 + %r1] */
94 } // namespace compiler
95 } // namespace internal
98 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_