deps/v8/src/compiler/mips/instruction-codes-mips.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
   6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // MIPS-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V) \
  15   V(MipsAdd)                       \
  16   V(MipsAddOvf)                    \
  17   V(MipsSub)                       \
  18   V(MipsSubOvf)                    \
  19   V(MipsMul)                       \
  20   V(MipsMulHigh)                   \
  21   V(MipsMulHighU)                  \
  22   V(MipsDiv)                       \
  23   V(MipsDivU)                      \
  24   V(MipsMod)                       \
  25   V(MipsModU)                      \
  26   V(MipsAnd)                       \
  27   V(MipsOr)                        \
  28   V(MipsXor)                       \
  29   V(MipsShl)                       \
  30   V(MipsShr)                       \
  31   V(MipsSar)                       \
  32   V(MipsRor)                       \
  33   V(MipsMov)                       \
  34   V(MipsTst)                       \
  35   V(MipsCmp)                       \
  36   V(MipsCmpD)                      \
  37   V(MipsAddD)                      \
  38   V(MipsSubD)                      \
  39   V(MipsMulD)                      \
  40   V(MipsDivD)                      \
  41   V(MipsModD)                      \
  42   V(MipsSqrtD)                     \
  43   V(MipsFloat64Floor)              \
  44   V(MipsFloat64Ceil)               \
  45   V(MipsFloat64RoundTruncate)      \
  46   V(MipsCvtSD)                     \
  47   V(MipsCvtDS)                     \
  48   V(MipsTruncWD)                   \
  49   V(MipsTruncUwD)                  \
  50   V(MipsCvtDW)                     \
  51   V(MipsCvtDUw)                    \
  52   V(MipsLb)                        \
  53   V(MipsLbu)                       \
  54   V(MipsSb)                        \
  55   V(MipsLh)                        \
  56   V(MipsLhu)                       \
  57   V(MipsSh)                        \
  58   V(MipsLw)                        \
  59   V(MipsSw)                        \
  60   V(MipsLwc1)                      \
  61   V(MipsSwc1)                      \
  62   V(MipsLdc1)                      \
  63   V(MipsSdc1)                      \
  64   V(MipsPush)                      \
  65   V(MipsStoreToStackSlot)          \
  66   V(MipsStackClaim)                \
  67   V(MipsStoreWriteBarrier)
  68
  69
  70 // Addressing modes represent the "shape" of inputs to an instruction.
  71 // Many instructions support multiple addressing modes. Addressing modes
  72 // are encoded into the InstructionCode of the instruction and tell the
  73 // code generator after register allocation which assembler method to call.
  74 //
  75 // We use the following local notation for addressing modes:
  76 //
  77 // R = register
  78 // O = register or stack slot
  79 // D = double register
  80 // I = immediate (handle, external, int32)
  81 // MRI = [register + immediate]
  82 // MRR = [register + register]
  83 // TODO(plind): Add the new r6 address modes.
  84 #define TARGET_ADDRESSING_MODE_LIST(V) \
  85   V(MRI) /* [%r0 + K] */               \
  86   V(MRR) /* [%r0 + %r1] */
  87
  88
  89 }  // namespace compiler
  90 }  // namespace internal
  91 }  // namespace v8
  92
  93 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_