deps/v8/src/compiler/instruction-codes.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_
   6 #define V8_COMPILER_INSTRUCTION_CODES_H_
   7
   8 #include <iosfwd>
   9
  10 #if V8_TARGET_ARCH_ARM
  11 #include "src/compiler/arm/instruction-codes-arm.h"
  12 #elif V8_TARGET_ARCH_ARM64
  13 #include "src/compiler/arm64/instruction-codes-arm64.h"
  14 #elif V8_TARGET_ARCH_IA32
  15 #include "src/compiler/ia32/instruction-codes-ia32.h"
  16 #elif V8_TARGET_ARCH_MIPS
  17 #include "src/compiler/mips/instruction-codes-mips.h"
  18 #elif V8_TARGET_ARCH_MIPS64
  19 #include "src/compiler/mips64/instruction-codes-mips64.h"
  20 #elif V8_TARGET_ARCH_X64
  21 #include "src/compiler/x64/instruction-codes-x64.h"
  22 #elif V8_TARGET_ARCH_PPC
  23 #include "src/compiler/ppc/instruction-codes-ppc.h"
  24 #else
  25 #define TARGET_ARCH_OPCODE_LIST(V)
  26 #define TARGET_ADDRESSING_MODE_LIST(V)
  27 #endif
  28 #include "src/utils.h"
  29
  30 namespace v8 {
  31 namespace internal {
  32 namespace compiler {
  33
  34 // Target-specific opcodes that specify which assembly sequence to emit.
  35 // Most opcodes specify a single instruction.
  36 #define ARCH_OPCODE_LIST(V) \
  37   V(ArchCallCodeObject)     \
  38   V(ArchCallJSFunction)     \
  39   V(ArchJmp)                \
  40   V(ArchLookupSwitch)       \
  41   V(ArchTableSwitch)        \
  42   V(ArchNop)                \
  43   V(ArchDeoptimize)         \
  44   V(ArchRet)                \
  45   V(ArchStackPointer)       \
  46   V(ArchTruncateDoubleToI)  \
  47   V(CheckedLoadInt8)        \
  48   V(CheckedLoadUint8)       \
  49   V(CheckedLoadInt16)       \
  50   V(CheckedLoadUint16)      \
  51   V(CheckedLoadWord32)      \
  52   V(CheckedLoadFloat32)     \
  53   V(CheckedLoadFloat64)     \
  54   V(CheckedStoreWord8)      \
  55   V(CheckedStoreWord16)     \
  56   V(CheckedStoreWord32)     \
  57   V(CheckedStoreFloat32)    \
  58   V(CheckedStoreFloat64)    \
  59   TARGET_ARCH_OPCODE_LIST(V)
  60
  61 enum ArchOpcode {
  62 #define DECLARE_ARCH_OPCODE(Name) k##Name,
  63   ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE)
  64 #undef DECLARE_ARCH_OPCODE
  65 #define COUNT_ARCH_OPCODE(Name) +1
  66   kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE)
  67 #undef COUNT_ARCH_OPCODE
  68 };
  69
  70 std::ostream& operator<<(std::ostream& os, const ArchOpcode& ao);
  71
  72 // Addressing modes represent the "shape" of inputs to an instruction.
  73 // Many instructions support multiple addressing modes. Addressing modes
  74 // are encoded into the InstructionCode of the instruction and tell the
  75 // code generator after register allocation which assembler method to call.
  76 #define ADDRESSING_MODE_LIST(V) \
  77   V(None)                       \
  78   TARGET_ADDRESSING_MODE_LIST(V)
  79
  80 enum AddressingMode {
  81 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name,
  82   ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE)
  83 #undef DECLARE_ADDRESSING_MODE
  84 #define COUNT_ADDRESSING_MODE(Name) +1
  85   kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE)
  86 #undef COUNT_ADDRESSING_MODE
  87 };
  88
  89 std::ostream& operator<<(std::ostream& os, const AddressingMode& am);
  90
  91 // The mode of the flags continuation (see below).
  92 enum FlagsMode { kFlags_none = 0, kFlags_branch = 1, kFlags_set = 2 };
  93
  94 std::ostream& operator<<(std::ostream& os, const FlagsMode& fm);
  95
  96 // The condition of flags continuation (see below).
  97 enum FlagsCondition {
  98   kEqual,
  99   kNotEqual,
 100   kSignedLessThan,
 101   kSignedGreaterThanOrEqual,
 102   kSignedLessThanOrEqual,
 103   kSignedGreaterThan,
 104   kUnsignedLessThan,
 105   kUnsignedGreaterThanOrEqual,
 106   kUnsignedLessThanOrEqual,
 107   kUnsignedGreaterThan,
 108   kUnorderedEqual,
 109   kUnorderedNotEqual,
 110   kOverflow,
 111   kNotOverflow
 112 };
 113
 114 inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) {
 115   return static_cast<FlagsCondition>(condition ^ 1);
 116 }
 117
 118 std::ostream& operator<<(std::ostream& os, const FlagsCondition& fc);
 119
 120 // The InstructionCode is an opaque, target-specific integer that encodes
 121 // what code to emit for an instruction in the code generator. It is not
 122 // interesting to the register allocator, as the inputs and flags on the
 123 // instructions specify everything of interest.
 124 typedef int32_t InstructionCode;
 125
 126 // Helpers for encoding / decoding InstructionCode into the fields needed
 127 // for code generation. We encode the instruction, addressing mode, and flags
 128 // continuation into a single InstructionCode which is stored as part of
 129 // the instruction.
 130 typedef BitField<ArchOpcode, 0, 7> ArchOpcodeField;
 131 typedef BitField<AddressingMode, 7, 5> AddressingModeField;
 132 typedef BitField<FlagsMode, 12, 2> FlagsModeField;
 133 typedef BitField<FlagsCondition, 14, 4> FlagsConditionField;
 134 typedef BitField<int, 14, 18> MiscField;
 135
 136 }  // namespace compiler
 137 }  // namespace internal
 138 }  // namespace v8
 139
 140 #endif  // V8_COMPILER_INSTRUCTION_CODES_H_