1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
12 // IA32-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
42 V(SSEFloat64RoundTruncate) \
45 V(SSEFloat64ToInt32) \
46 V(SSEFloat64ToUint32) \
47 V(SSEInt32ToFloat64) \
48 V(SSEUint32ToFloat64) \
64 V(IA32StoreWriteBarrier)
67 // Addressing modes represent the "shape" of inputs to an instruction.
68 // Many instructions support multiple addressing modes. Addressing modes
69 // are encoded into the InstructionCode of the instruction and tell the
70 // code generator after register allocation which assembler method to call.
72 // We use the following local notation for addressing modes:
76 // N = index register * N for N in {1, 2, 4, 8}
77 // I = immediate displacement (int32_t)
79 #define TARGET_ADDRESSING_MODE_LIST(V) \
81 V(MRI) /* [%r1 + K] */ \
82 V(MR1) /* [%r1 + %r2*1 ] */ \
83 V(MR2) /* [%r1 + %r2*2 ] */ \
84 V(MR4) /* [%r1 + %r2*4 ] */ \
85 V(MR8) /* [%r1 + %r2*8 ] */ \
86 V(MR1I) /* [%r1 + %r2*1 + K] */ \
87 V(MR2I) /* [%r1 + %r2*2 + K] */ \
88 V(MR4I) /* [%r1 + %r2*3 + K] */ \
89 V(MR8I) /* [%r1 + %r2*4 + K] */ \
90 V(M1) /* [ %r2*1 ] */ \
91 V(M2) /* [ %r2*2 ] */ \
92 V(M4) /* [ %r2*4 ] */ \
93 V(M8) /* [ %r2*8 ] */ \
94 V(M1I) /* [ %r2*1 + K] */ \
95 V(M2I) /* [ %r2*2 + K] */ \
96 V(M4I) /* [ %r2*4 + K] */ \
97 V(M8I) /* [ %r2*8 + K] */ \
100 } // namespace compiler
101 } // namespace internal
104 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_