deps/v8/src/compiler/ia32/instruction-codes-ia32.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
   6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // IA32-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V) \
  15   V(IA32Add)                       \
  16   V(IA32And)                       \
  17   V(IA32Cmp)                       \
  18   V(IA32Test)                      \
  19   V(IA32Or)                        \
  20   V(IA32Xor)                       \
  21   V(IA32Sub)                       \
  22   V(IA32Imul)                      \
  23   V(IA32ImulHigh)                  \
  24   V(IA32UmulHigh)                  \
  25   V(IA32Idiv)                      \
  26   V(IA32Udiv)                      \
  27   V(IA32Not)                       \
  28   V(IA32Neg)                       \
  29   V(IA32Shl)                       \
  30   V(IA32Shr)                       \
  31   V(IA32Sar)                       \
  32   V(IA32Ror)                       \
  33   V(IA32Lzcnt)                     \
  34   V(SSEFloat64Cmp)                 \
  35   V(SSEFloat64Add)                 \
  36   V(SSEFloat64Sub)                 \
  37   V(SSEFloat64Mul)                 \
  38   V(SSEFloat64Div)                 \
  39   V(SSEFloat64Mod)                 \
  40   V(SSEFloat64Max)                 \
  41   V(SSEFloat64Min)                 \
  42   V(SSEFloat64Sqrt)                \
  43   V(SSEFloat64Round)               \
  44   V(SSECvtss2sd)                   \
  45   V(SSECvtsd2ss)                   \
  46   V(SSEFloat64ToInt32)             \
  47   V(SSEFloat64ToUint32)            \
  48   V(SSEInt32ToFloat64)             \
  49   V(SSEUint32ToFloat64)            \
  50   V(SSEFloat64ExtractLowWord32)    \
  51   V(SSEFloat64ExtractHighWord32)   \
  52   V(SSEFloat64InsertLowWord32)     \
  53   V(SSEFloat64InsertHighWord32)    \
  54   V(SSEFloat64LoadLowWord32)       \
  55   V(AVXFloat64Add)                 \
  56   V(AVXFloat64Sub)                 \
  57   V(AVXFloat64Mul)                 \
  58   V(AVXFloat64Div)                 \
  59   V(AVXFloat64Max)                 \
  60   V(AVXFloat64Min)                 \
  61   V(IA32Movsxbl)                   \
  62   V(IA32Movzxbl)                   \
  63   V(IA32Movb)                      \
  64   V(IA32Movsxwl)                   \
  65   V(IA32Movzxwl)                   \
  66   V(IA32Movw)                      \
  67   V(IA32Movl)                      \
  68   V(IA32Movss)                     \
  69   V(IA32Movsd)                     \
  70   V(IA32Lea)                       \
  71   V(IA32Push)                      \
  72   V(IA32StoreWriteBarrier)         \
  73   V(IA32StackCheck)
  74
  75
  76 // Addressing modes represent the "shape" of inputs to an instruction.
  77 // Many instructions support multiple addressing modes. Addressing modes
  78 // are encoded into the InstructionCode of the instruction and tell the
  79 // code generator after register allocation which assembler method to call.
  80 //
  81 // We use the following local notation for addressing modes:
  82 //
  83 // M = memory operand
  84 // R = base register
  85 // N = index register * N for N in {1, 2, 4, 8}
  86 // I = immediate displacement (int32_t)
  87
  88 #define TARGET_ADDRESSING_MODE_LIST(V) \
  89   V(MR)   /* [%r1            ] */      \
  90   V(MRI)  /* [%r1         + K] */      \
  91   V(MR1)  /* [%r1 + %r2*1    ] */      \
  92   V(MR2)  /* [%r1 + %r2*2    ] */      \
  93   V(MR4)  /* [%r1 + %r2*4    ] */      \
  94   V(MR8)  /* [%r1 + %r2*8    ] */      \
  95   V(MR1I) /* [%r1 + %r2*1 + K] */      \
  96   V(MR2I) /* [%r1 + %r2*2 + K] */      \
  97   V(MR4I) /* [%r1 + %r2*3 + K] */      \
  98   V(MR8I) /* [%r1 + %r2*4 + K] */      \
  99   V(M1)   /* [      %r2*1    ] */      \
 100   V(M2)   /* [      %r2*2    ] */      \
 101   V(M4)   /* [      %r2*4    ] */      \
 102   V(M8)   /* [      %r2*8    ] */      \
 103   V(M1I)  /* [      %r2*1 + K] */      \
 104   V(M2I)  /* [      %r2*2 + K] */      \
 105   V(M4I)  /* [      %r2*4 + K] */      \
 106   V(M8I)  /* [      %r2*8 + K] */      \
 107   V(MI)   /* [              K] */
 108
 109 }  // namespace compiler
 110 }  // namespace internal
 111 }  // namespace v8
 112
 113 #endif  // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_