deps/v8/src/compiler/arm/instruction-codes-arm.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
   6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // ARM-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V) \
  15   V(ArmAdd)                        \
  16   V(ArmAnd)                        \
  17   V(ArmBic)                        \
  18   V(ArmClz)                        \
  19   V(ArmCmp)                        \
  20   V(ArmCmn)                        \
  21   V(ArmTst)                        \
  22   V(ArmTeq)                        \
  23   V(ArmOrr)                        \
  24   V(ArmEor)                        \
  25   V(ArmSub)                        \
  26   V(ArmRsb)                        \
  27   V(ArmMul)                        \
  28   V(ArmMla)                        \
  29   V(ArmMls)                        \
  30   V(ArmSmmul)                      \
  31   V(ArmSmmla)                      \
  32   V(ArmUmull)                      \
  33   V(ArmSdiv)                       \
  34   V(ArmUdiv)                       \
  35   V(ArmMov)                        \
  36   V(ArmMvn)                        \
  37   V(ArmBfc)                        \
  38   V(ArmUbfx)                       \
  39   V(ArmSxtb)                       \
  40   V(ArmSxth)                       \
  41   V(ArmSxtab)                      \
  42   V(ArmSxtah)                      \
  43   V(ArmUxtb)                       \
  44   V(ArmUxth)                       \
  45   V(ArmUxtab)                      \
  46   V(ArmUxtah)                      \
  47   V(ArmVcmpF64)                    \
  48   V(ArmVaddF64)                    \
  49   V(ArmVsubF64)                    \
  50   V(ArmVmulF64)                    \
  51   V(ArmVmlaF64)                    \
  52   V(ArmVmlsF64)                    \
  53   V(ArmVdivF64)                    \
  54   V(ArmVmodF64)                    \
  55   V(ArmVnegF64)                    \
  56   V(ArmVsqrtF64)                   \
  57   V(ArmVrintmF64)                  \
  58   V(ArmVrintpF64)                  \
  59   V(ArmVrintzF64)                  \
  60   V(ArmVrintaF64)                  \
  61   V(ArmVcvtF32F64)                 \
  62   V(ArmVcvtF64F32)                 \
  63   V(ArmVcvtF64S32)                 \
  64   V(ArmVcvtF64U32)                 \
  65   V(ArmVcvtS32F64)                 \
  66   V(ArmVcvtU32F64)                 \
  67   V(ArmVmovLowU32F64)              \
  68   V(ArmVmovLowF64U32)              \
  69   V(ArmVmovHighU32F64)             \
  70   V(ArmVmovHighF64U32)             \
  71   V(ArmVmovF64U32U32)              \
  72   V(ArmVldrF32)                    \
  73   V(ArmVstrF32)                    \
  74   V(ArmVldrF64)                    \
  75   V(ArmVstrF64)                    \
  76   V(ArmLdrb)                       \
  77   V(ArmLdrsb)                      \
  78   V(ArmStrb)                       \
  79   V(ArmLdrh)                       \
  80   V(ArmLdrsh)                      \
  81   V(ArmStrh)                       \
  82   V(ArmLdr)                        \
  83   V(ArmStr)                        \
  84   V(ArmPush)                       \
  85   V(ArmStoreWriteBarrier)
  86
  87
  88 // Addressing modes represent the "shape" of inputs to an instruction.
  89 // Many instructions support multiple addressing modes. Addressing modes
  90 // are encoded into the InstructionCode of the instruction and tell the
  91 // code generator after register allocation which assembler method to call.
  92 #define TARGET_ADDRESSING_MODE_LIST(V)  \
  93   V(Offset_RI)        /* [%r0 + K] */   \
  94   V(Offset_RR)        /* [%r0 + %r1] */ \
  95   V(Operand2_I)       /* K */           \
  96   V(Operand2_R)       /* %r0 */         \
  97   V(Operand2_R_ASR_I) /* %r0 ASR K */   \
  98   V(Operand2_R_LSL_I) /* %r0 LSL K */   \
  99   V(Operand2_R_LSR_I) /* %r0 LSR K */   \
 100   V(Operand2_R_ROR_I) /* %r0 ROR K */   \
 101   V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
 102   V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
 103   V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
 104   V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
 105
 106 }  // namespace compiler
 107 }  // namespace internal
 108 }  // namespace v8
 109
 110 #endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_