1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_
8 #include "src/arm64/assembler-arm64.h"
9 #include "src/assembler.h"
10 #include "src/debug.h"
17 bool CpuFeatures::SupportsCrankshaft() { return true; }
20 void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) {
21 // On arm64 only internal references need extra work.
22 DCHECK(RelocInfo::IsInternalReference(rmode_));
24 // Absolute code pointer inside code object moves with the code object.
25 intptr_t* p = reinterpret_cast<intptr_t*>(pc_);
26 *p += delta; // Relocate entry.
30 void RelocInfo::set_target_address(Address target,
31 WriteBarrierMode write_barrier_mode,
32 ICacheFlushMode icache_flush_mode) {
33 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
34 Assembler::set_target_address_at(pc_, host_, target, icache_flush_mode);
35 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL &&
36 IsCodeTarget(rmode_)) {
37 Object* target_code = Code::GetCodeFromTargetAddress(target);
38 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
39 host(), this, HeapObject::cast(target_code));
44 inline unsigned CPURegister::code() const {
50 inline CPURegister::RegisterType CPURegister::type() const {
51 DCHECK(IsValidOrNone());
56 inline RegList CPURegister::Bit() const {
57 DCHECK(reg_code < (sizeof(RegList) * kBitsPerByte));
58 return IsValid() ? 1UL << reg_code : 0;
62 inline unsigned CPURegister::SizeInBits() const {
68 inline int CPURegister::SizeInBytes() const {
70 DCHECK(SizeInBits() % 8 == 0);
75 inline bool CPURegister::Is32Bits() const {
77 return reg_size == 32;
81 inline bool CPURegister::Is64Bits() const {
83 return reg_size == 64;
87 inline bool CPURegister::IsValid() const {
88 if (IsValidRegister() || IsValidFPRegister()) {
98 inline bool CPURegister::IsValidRegister() const {
99 return IsRegister() &&
100 ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) &&
101 ((reg_code < kNumberOfRegisters) || (reg_code == kSPRegInternalCode));
105 inline bool CPURegister::IsValidFPRegister() const {
106 return IsFPRegister() &&
107 ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) &&
108 (reg_code < kNumberOfFPRegisters);
112 inline bool CPURegister::IsNone() const {
113 // kNoRegister types should always have size 0 and code 0.
114 DCHECK((reg_type != kNoRegister) || (reg_code == 0));
115 DCHECK((reg_type != kNoRegister) || (reg_size == 0));
117 return reg_type == kNoRegister;
121 inline bool CPURegister::Is(const CPURegister& other) const {
122 DCHECK(IsValidOrNone() && other.IsValidOrNone());
123 return Aliases(other) && (reg_size == other.reg_size);
127 inline bool CPURegister::Aliases(const CPURegister& other) const {
128 DCHECK(IsValidOrNone() && other.IsValidOrNone());
129 return (reg_code == other.reg_code) && (reg_type == other.reg_type);
133 inline bool CPURegister::IsRegister() const {
134 return reg_type == kRegister;
138 inline bool CPURegister::IsFPRegister() const {
139 return reg_type == kFPRegister;
143 inline bool CPURegister::IsSameSizeAndType(const CPURegister& other) const {
144 return (reg_size == other.reg_size) && (reg_type == other.reg_type);
148 inline bool CPURegister::IsValidOrNone() const {
149 return IsValid() || IsNone();
153 inline bool CPURegister::IsZero() const {
155 return IsRegister() && (reg_code == kZeroRegCode);
159 inline bool CPURegister::IsSP() const {
161 return IsRegister() && (reg_code == kSPRegInternalCode);
165 inline void CPURegList::Combine(const CPURegList& other) {
167 DCHECK(other.type() == type_);
168 DCHECK(other.RegisterSizeInBits() == size_);
169 list_ |= other.list();
173 inline void CPURegList::Remove(const CPURegList& other) {
175 if (other.type() == type_) {
176 list_ &= ~other.list();
181 inline void CPURegList::Combine(const CPURegister& other) {
182 DCHECK(other.type() == type_);
183 DCHECK(other.SizeInBits() == size_);
184 Combine(other.code());
188 inline void CPURegList::Remove(const CPURegister& other1,
189 const CPURegister& other2,
190 const CPURegister& other3,
191 const CPURegister& other4) {
192 if (!other1.IsNone() && (other1.type() == type_)) Remove(other1.code());
193 if (!other2.IsNone() && (other2.type() == type_)) Remove(other2.code());
194 if (!other3.IsNone() && (other3.type() == type_)) Remove(other3.code());
195 if (!other4.IsNone() && (other4.type() == type_)) Remove(other4.code());
199 inline void CPURegList::Combine(int code) {
201 DCHECK(CPURegister::Create(code, size_, type_).IsValid());
202 list_ |= (1UL << code);
206 inline void CPURegList::Remove(int code) {
208 DCHECK(CPURegister::Create(code, size_, type_).IsValid());
209 list_ &= ~(1UL << code);
213 inline Register Register::XRegFromCode(unsigned code) {
214 if (code == kSPRegInternalCode) {
217 DCHECK(code < kNumberOfRegisters);
218 return Register::Create(code, kXRegSizeInBits);
223 inline Register Register::WRegFromCode(unsigned code) {
224 if (code == kSPRegInternalCode) {
227 DCHECK(code < kNumberOfRegisters);
228 return Register::Create(code, kWRegSizeInBits);
233 inline FPRegister FPRegister::SRegFromCode(unsigned code) {
234 DCHECK(code < kNumberOfFPRegisters);
235 return FPRegister::Create(code, kSRegSizeInBits);
239 inline FPRegister FPRegister::DRegFromCode(unsigned code) {
240 DCHECK(code < kNumberOfFPRegisters);
241 return FPRegister::Create(code, kDRegSizeInBits);
245 inline Register CPURegister::W() const {
246 DCHECK(IsValidRegister());
247 return Register::WRegFromCode(reg_code);
251 inline Register CPURegister::X() const {
252 DCHECK(IsValidRegister());
253 return Register::XRegFromCode(reg_code);
257 inline FPRegister CPURegister::S() const {
258 DCHECK(IsValidFPRegister());
259 return FPRegister::SRegFromCode(reg_code);
263 inline FPRegister CPURegister::D() const {
264 DCHECK(IsValidFPRegister());
265 return FPRegister::DRegFromCode(reg_code);
270 // Default initializer is for int types
272 struct ImmediateInitializer {
273 static const bool kIsIntType = true;
274 static inline RelocInfo::Mode rmode_for(T) {
275 return sizeof(T) == 8 ? RelocInfo::NONE64 : RelocInfo::NONE32;
277 static inline int64_t immediate_for(T t) {
278 STATIC_ASSERT(sizeof(T) <= 8);
285 struct ImmediateInitializer<Smi*> {
286 static const bool kIsIntType = false;
287 static inline RelocInfo::Mode rmode_for(Smi* t) {
288 return RelocInfo::NONE64;
290 static inline int64_t immediate_for(Smi* t) {;
291 return reinterpret_cast<int64_t>(t);
297 struct ImmediateInitializer<ExternalReference> {
298 static const bool kIsIntType = false;
299 static inline RelocInfo::Mode rmode_for(ExternalReference t) {
300 return RelocInfo::EXTERNAL_REFERENCE;
302 static inline int64_t immediate_for(ExternalReference t) {;
303 return reinterpret_cast<int64_t>(t.address());
309 Immediate::Immediate(Handle<T> value) {
310 InitializeHandle(value);
315 Immediate::Immediate(T t)
316 : value_(ImmediateInitializer<T>::immediate_for(t)),
317 rmode_(ImmediateInitializer<T>::rmode_for(t)) {}
321 Immediate::Immediate(T t, RelocInfo::Mode rmode)
322 : value_(ImmediateInitializer<T>::immediate_for(t)),
324 STATIC_ASSERT(ImmediateInitializer<T>::kIsIntType);
330 Operand::Operand(Handle<T> value) : immediate_(value), reg_(NoReg) {}
334 Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
338 Operand::Operand(T t, RelocInfo::Mode rmode)
339 : immediate_(t, rmode),
343 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
348 shift_amount_(shift_amount) {
349 DCHECK(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
350 DCHECK(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
355 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
360 shift_amount_(shift_amount) {
361 DCHECK(reg.IsValid());
362 DCHECK(shift_amount <= 4);
365 // Extend modes SXTX and UXTX require a 64-bit register.
366 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
370 bool Operand::IsImmediate() const {
371 return reg_.Is(NoReg);
375 bool Operand::IsShiftedRegister() const {
376 return reg_.IsValid() && (shift_ != NO_SHIFT);
380 bool Operand::IsExtendedRegister() const {
381 return reg_.IsValid() && (extend_ != NO_EXTEND);
385 bool Operand::IsZero() const {
387 return ImmediateValue() == 0;
389 return reg().IsZero();
394 Operand Operand::ToExtendedRegister() const {
395 DCHECK(IsShiftedRegister());
396 DCHECK((shift_ == LSL) && (shift_amount_ <= 4));
397 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
401 Immediate Operand::immediate() const {
402 DCHECK(IsImmediate());
407 int64_t Operand::ImmediateValue() const {
408 DCHECK(IsImmediate());
409 return immediate_.value();
413 Register Operand::reg() const {
414 DCHECK(IsShiftedRegister() || IsExtendedRegister());
419 Shift Operand::shift() const {
420 DCHECK(IsShiftedRegister());
425 Extend Operand::extend() const {
426 DCHECK(IsExtendedRegister());
431 unsigned Operand::shift_amount() const {
432 DCHECK(IsShiftedRegister() || IsExtendedRegister());
433 return shift_amount_;
437 Operand Operand::UntagSmi(Register smi) {
438 STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift +
440 DCHECK(smi.Is64Bits());
441 return Operand(smi, ASR, kSmiShift);
445 Operand Operand::UntagSmiAndScale(Register smi, int scale) {
446 STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift +
448 DCHECK(smi.Is64Bits());
449 DCHECK((scale >= 0) && (scale <= (64 - kSmiValueSize)));
450 if (scale > kSmiShift) {
451 return Operand(smi, LSL, scale - kSmiShift);
452 } else if (scale < kSmiShift) {
453 return Operand(smi, ASR, kSmiShift - scale);
459 MemOperand::MemOperand()
460 : base_(NoReg), regoffset_(NoReg), offset_(0), addrmode_(Offset),
461 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
465 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
466 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
467 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
468 DCHECK(base.Is64Bits() && !base.IsZero());
472 MemOperand::MemOperand(Register base,
475 unsigned shift_amount)
476 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
477 shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) {
478 DCHECK(base.Is64Bits() && !base.IsZero());
479 DCHECK(!regoffset.IsSP());
480 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
482 // SXTX extend mode requires a 64-bit offset register.
483 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
487 MemOperand::MemOperand(Register base,
490 unsigned shift_amount)
491 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
492 shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
493 DCHECK(base.Is64Bits() && !base.IsZero());
494 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
495 DCHECK(shift == LSL);
499 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
500 : base_(base), addrmode_(addrmode) {
501 DCHECK(base.Is64Bits() && !base.IsZero());
503 if (offset.IsImmediate()) {
504 offset_ = offset.ImmediateValue();
507 } else if (offset.IsShiftedRegister()) {
508 DCHECK(addrmode == Offset);
510 regoffset_ = offset.reg();
511 shift_ = offset.shift();
512 shift_amount_ = offset.shift_amount();
517 // These assertions match those in the shifted-register constructor.
518 DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());
519 DCHECK(shift_ == LSL);
521 DCHECK(offset.IsExtendedRegister());
522 DCHECK(addrmode == Offset);
524 regoffset_ = offset.reg();
525 extend_ = offset.extend();
526 shift_amount_ = offset.shift_amount();
531 // These assertions match those in the extended-register constructor.
532 DCHECK(!regoffset_.IsSP());
533 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
534 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
538 bool MemOperand::IsImmediateOffset() const {
539 return (addrmode_ == Offset) && regoffset_.Is(NoReg);
543 bool MemOperand::IsRegisterOffset() const {
544 return (addrmode_ == Offset) && !regoffset_.Is(NoReg);
548 bool MemOperand::IsPreIndex() const {
549 return addrmode_ == PreIndex;
553 bool MemOperand::IsPostIndex() const {
554 return addrmode_ == PostIndex;
557 Operand MemOperand::OffsetAsOperand() const {
558 if (IsImmediateOffset()) {
561 DCHECK(IsRegisterOffset());
562 if (extend() == NO_EXTEND) {
563 return Operand(regoffset(), shift(), shift_amount());
565 return Operand(regoffset(), extend(), shift_amount());
571 void Assembler::Unreachable() {
573 debug("UNREACHABLE", __LINE__, BREAK);
575 // Crash by branching to 0. lr now points near the fault.
581 Address Assembler::target_pointer_address_at(Address pc) {
582 Instruction* instr = reinterpret_cast<Instruction*>(pc);
583 DCHECK(instr->IsLdrLiteralX());
584 return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
588 // Read/Modify the code target address in the branch/call instruction at pc.
589 Address Assembler::target_address_at(Address pc,
590 ConstantPoolArray* constant_pool) {
591 return Memory::Address_at(target_pointer_address_at(pc));
595 Address Assembler::target_address_at(Address pc, Code* code) {
596 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
597 return target_address_at(pc, constant_pool);
601 Address Assembler::target_address_from_return_address(Address pc) {
602 // Returns the address of the call target from the return address that will
603 // be returned to after a call.
604 // Call sequence on ARM64 is:
605 // ldr ip0, #... @ load from literal pool
607 Address candidate = pc - 2 * kInstructionSize;
608 Instruction* instr = reinterpret_cast<Instruction*>(candidate);
610 DCHECK(instr->IsLdrLiteralX());
615 Address Assembler::break_address_from_return_address(Address pc) {
616 return pc - Assembler::kPatchDebugBreakSlotReturnOffset;
620 Address Assembler::return_address_from_call_start(Address pc) {
621 // The call, generated by MacroAssembler::Call, is one of two possible
624 // Without relocation:
625 // movz temp, #(target & 0x000000000000ffff)
626 // movk temp, #(target & 0x00000000ffff0000)
627 // movk temp, #(target & 0x0000ffff00000000)
634 // The return address is immediately after the blr instruction in both cases,
635 // so it can be found by adding the call size to the address at the start of
636 // the call sequence.
637 STATIC_ASSERT(Assembler::kCallSizeWithoutRelocation == 4 * kInstructionSize);
638 STATIC_ASSERT(Assembler::kCallSizeWithRelocation == 2 * kInstructionSize);
640 Instruction* instr = reinterpret_cast<Instruction*>(pc);
641 if (instr->IsMovz()) {
642 // Verify the instruction sequence.
643 DCHECK(instr->following(1)->IsMovk());
644 DCHECK(instr->following(2)->IsMovk());
645 DCHECK(instr->following(3)->IsBranchAndLinkToRegister());
646 return pc + Assembler::kCallSizeWithoutRelocation;
648 // Verify the instruction sequence.
649 DCHECK(instr->IsLdrLiteralX());
650 DCHECK(instr->following(1)->IsBranchAndLinkToRegister());
651 return pc + Assembler::kCallSizeWithRelocation;
656 void Assembler::deserialization_set_special_target_at(
657 Address constant_pool_entry, Code* code, Address target) {
658 Memory::Address_at(constant_pool_entry) = target;
662 void Assembler::deserialization_set_target_internal_reference_at(
663 Address pc, Address target, RelocInfo::Mode mode) {
664 Memory::Address_at(pc) = target;
668 void Assembler::set_target_address_at(Address pc,
669 ConstantPoolArray* constant_pool,
671 ICacheFlushMode icache_flush_mode) {
672 Memory::Address_at(target_pointer_address_at(pc)) = target;
673 // Intuitively, we would think it is necessary to always flush the
674 // instruction cache after patching a target address in the code as follows:
675 // CpuFeatures::FlushICache(pc, sizeof(target));
676 // However, on ARM, an instruction is actually patched in the case of
677 // embedded constants of the form:
678 // ldr ip, [pc, #...]
679 // since the instruction accessing this address in the constant pool remains
680 // unchanged, a flush is not required.
684 void Assembler::set_target_address_at(Address pc,
687 ICacheFlushMode icache_flush_mode) {
688 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
689 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
693 int RelocInfo::target_address_size() {
698 Address RelocInfo::target_address() {
699 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
700 return Assembler::target_address_at(pc_, host_);
704 Address RelocInfo::target_address_address() {
705 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
706 || rmode_ == EMBEDDED_OBJECT
707 || rmode_ == EXTERNAL_REFERENCE);
708 return Assembler::target_pointer_address_at(pc_);
712 Address RelocInfo::constant_pool_entry_address() {
713 DCHECK(IsInConstantPool());
714 return Assembler::target_pointer_address_at(pc_);
718 Object* RelocInfo::target_object() {
719 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
720 return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_));
724 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
725 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
726 return Handle<Object>(reinterpret_cast<Object**>(
727 Assembler::target_address_at(pc_, host_)));
731 void RelocInfo::set_target_object(Object* target,
732 WriteBarrierMode write_barrier_mode,
733 ICacheFlushMode icache_flush_mode) {
734 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
735 Assembler::set_target_address_at(pc_, host_,
736 reinterpret_cast<Address>(target),
738 if (write_barrier_mode == UPDATE_WRITE_BARRIER &&
740 target->IsHeapObject()) {
741 host()->GetHeap()->incremental_marking()->RecordWrite(
742 host(), &Memory::Object_at(pc_), HeapObject::cast(target));
747 Address RelocInfo::target_external_reference() {
748 DCHECK(rmode_ == EXTERNAL_REFERENCE);
749 return Assembler::target_address_at(pc_, host_);
753 Address RelocInfo::target_internal_reference() {
754 DCHECK(rmode_ == INTERNAL_REFERENCE);
755 return Memory::Address_at(pc_);
759 Address RelocInfo::target_internal_reference_address() {
760 DCHECK(rmode_ == INTERNAL_REFERENCE);
761 return reinterpret_cast<Address>(pc_);
765 Address RelocInfo::target_runtime_entry(Assembler* origin) {
766 DCHECK(IsRuntimeEntry(rmode_));
767 return target_address();
771 void RelocInfo::set_target_runtime_entry(Address target,
772 WriteBarrierMode write_barrier_mode,
773 ICacheFlushMode icache_flush_mode) {
774 DCHECK(IsRuntimeEntry(rmode_));
775 if (target_address() != target) {
776 set_target_address(target, write_barrier_mode, icache_flush_mode);
781 Handle<Cell> RelocInfo::target_cell_handle() {
783 Cell *null_cell = NULL;
784 return Handle<Cell>(null_cell);
788 Cell* RelocInfo::target_cell() {
789 DCHECK(rmode_ == RelocInfo::CELL);
790 return Cell::FromValueAddress(Memory::Address_at(pc_));
794 void RelocInfo::set_target_cell(Cell* cell,
795 WriteBarrierMode write_barrier_mode,
796 ICacheFlushMode icache_flush_mode) {
801 static const int kNoCodeAgeSequenceLength = 5 * kInstructionSize;
802 static const int kCodeAgeStubEntryOffset = 3 * kInstructionSize;
805 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
806 UNREACHABLE(); // This should never be reached on ARM64.
807 return Handle<Object>();
811 Code* RelocInfo::code_age_stub() {
812 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
813 // Read the stub entry point from the code age sequence.
814 Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
815 return Code::GetCodeFromTargetAddress(Memory::Address_at(stub_entry_address));
819 void RelocInfo::set_code_age_stub(Code* stub,
820 ICacheFlushMode icache_flush_mode) {
821 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
822 DCHECK(!Code::IsYoungSequence(stub->GetIsolate(), pc_));
823 // Overwrite the stub entry point in the code age sequence. This is loaded as
824 // a literal so there is no need to call FlushICache here.
825 Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
826 Memory::Address_at(stub_entry_address) = stub->instruction_start();
830 Address RelocInfo::call_address() {
831 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
832 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
833 // For the above sequences the Relocinfo points to the load literal loading
835 return Assembler::target_address_at(pc_, host_);
839 void RelocInfo::set_call_address(Address target) {
840 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
841 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
842 Assembler::set_target_address_at(pc_, host_, target);
843 if (host() != NULL) {
844 Object* target_code = Code::GetCodeFromTargetAddress(target);
845 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
846 host(), this, HeapObject::cast(target_code));
851 void RelocInfo::WipeOut() {
852 DCHECK(IsEmbeddedObject(rmode_) || IsCodeTarget(rmode_) ||
853 IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) ||
854 IsInternalReference(rmode_));
855 if (IsInternalReference(rmode_)) {
856 Memory::Address_at(pc_) = NULL;
858 Assembler::set_target_address_at(pc_, host_, NULL);
863 bool RelocInfo::IsPatchedReturnSequence() {
864 // The sequence must be:
865 // ldr ip0, [pc, #offset]
867 // See arm64/debug-arm64.cc BreakLocation::SetDebugBreakAtReturn().
868 Instruction* i1 = reinterpret_cast<Instruction*>(pc_);
869 Instruction* i2 = i1->following();
870 return i1->IsLdrLiteralX() && (i1->Rt() == ip0.code()) &&
871 i2->IsBranchAndLinkToRegister() && (i2->Rn() == ip0.code());
875 bool RelocInfo::IsPatchedDebugBreakSlotSequence() {
876 Instruction* current_instr = reinterpret_cast<Instruction*>(pc_);
877 return !current_instr->IsNop(Assembler::DEBUG_BREAK_NOP);
881 void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
882 RelocInfo::Mode mode = rmode();
883 if (mode == RelocInfo::EMBEDDED_OBJECT) {
884 visitor->VisitEmbeddedPointer(this);
885 } else if (RelocInfo::IsCodeTarget(mode)) {
886 visitor->VisitCodeTarget(this);
887 } else if (mode == RelocInfo::CELL) {
888 visitor->VisitCell(this);
889 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
890 visitor->VisitExternalReference(this);
891 } else if (mode == RelocInfo::INTERNAL_REFERENCE) {
892 visitor->VisitInternalReference(this);
893 } else if (((RelocInfo::IsJSReturn(mode) &&
894 IsPatchedReturnSequence()) ||
895 (RelocInfo::IsDebugBreakSlot(mode) &&
896 IsPatchedDebugBreakSlotSequence())) &&
897 isolate->debug()->has_break_points()) {
898 visitor->VisitDebugTarget(this);
899 } else if (RelocInfo::IsRuntimeEntry(mode)) {
900 visitor->VisitRuntimeEntry(this);
905 template<typename StaticVisitor>
906 void RelocInfo::Visit(Heap* heap) {
907 RelocInfo::Mode mode = rmode();
908 if (mode == RelocInfo::EMBEDDED_OBJECT) {
909 StaticVisitor::VisitEmbeddedPointer(heap, this);
910 } else if (RelocInfo::IsCodeTarget(mode)) {
911 StaticVisitor::VisitCodeTarget(heap, this);
912 } else if (mode == RelocInfo::CELL) {
913 StaticVisitor::VisitCell(heap, this);
914 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
915 StaticVisitor::VisitExternalReference(this);
916 } else if (mode == RelocInfo::INTERNAL_REFERENCE) {
917 StaticVisitor::VisitInternalReference(this);
918 } else if (heap->isolate()->debug()->has_break_points() &&
919 ((RelocInfo::IsJSReturn(mode) &&
920 IsPatchedReturnSequence()) ||
921 (RelocInfo::IsDebugBreakSlot(mode) &&
922 IsPatchedDebugBreakSlotSequence()))) {
923 StaticVisitor::VisitDebugTarget(heap, this);
924 } else if (RelocInfo::IsRuntimeEntry(mode)) {
925 StaticVisitor::VisitRuntimeEntry(this);
930 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
931 DCHECK(rt.IsValid());
932 if (rt.IsRegister()) {
933 return rt.Is64Bits() ? LDR_x : LDR_w;
935 DCHECK(rt.IsFPRegister());
936 return rt.Is64Bits() ? LDR_d : LDR_s;
941 LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
942 const CPURegister& rt2) {
943 DCHECK(AreSameSizeAndType(rt, rt2));
945 if (rt.IsRegister()) {
946 return rt.Is64Bits() ? LDP_x : LDP_w;
948 DCHECK(rt.IsFPRegister());
949 return rt.Is64Bits() ? LDP_d : LDP_s;
954 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
955 DCHECK(rt.IsValid());
956 if (rt.IsRegister()) {
957 return rt.Is64Bits() ? STR_x : STR_w;
959 DCHECK(rt.IsFPRegister());
960 return rt.Is64Bits() ? STR_d : STR_s;
965 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
966 const CPURegister& rt2) {
967 DCHECK(AreSameSizeAndType(rt, rt2));
969 if (rt.IsRegister()) {
970 return rt.Is64Bits() ? STP_x : STP_w;
972 DCHECK(rt.IsFPRegister());
973 return rt.Is64Bits() ? STP_d : STP_s;
978 LoadStorePairNonTemporalOp Assembler::LoadPairNonTemporalOpFor(
979 const CPURegister& rt, const CPURegister& rt2) {
980 DCHECK(AreSameSizeAndType(rt, rt2));
982 if (rt.IsRegister()) {
983 return rt.Is64Bits() ? LDNP_x : LDNP_w;
985 DCHECK(rt.IsFPRegister());
986 return rt.Is64Bits() ? LDNP_d : LDNP_s;
991 LoadStorePairNonTemporalOp Assembler::StorePairNonTemporalOpFor(
992 const CPURegister& rt, const CPURegister& rt2) {
993 DCHECK(AreSameSizeAndType(rt, rt2));
995 if (rt.IsRegister()) {
996 return rt.Is64Bits() ? STNP_x : STNP_w;
998 DCHECK(rt.IsFPRegister());
999 return rt.Is64Bits() ? STNP_d : STNP_s;
1004 LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
1005 if (rt.IsRegister()) {
1006 return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit;
1008 DCHECK(rt.IsFPRegister());
1009 return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit;
1014 int Assembler::LinkAndGetInstructionOffsetTo(Label* label) {
1015 DCHECK(kStartOfLabelLinkChain == 0);
1016 int offset = LinkAndGetByteOffsetTo(label);
1017 DCHECK(IsAligned(offset, kInstructionSize));
1018 return offset >> kInstructionSizeLog2;
1022 Instr Assembler::Flags(FlagsUpdate S) {
1023 if (S == SetFlags) {
1024 return 1 << FlagsUpdate_offset;
1025 } else if (S == LeaveFlags) {
1026 return 0 << FlagsUpdate_offset;
1033 Instr Assembler::Cond(Condition cond) {
1034 return cond << Condition_offset;
1038 Instr Assembler::ImmPCRelAddress(int imm21) {
1039 CHECK(is_int21(imm21));
1040 Instr imm = static_cast<Instr>(truncate_to_int21(imm21));
1041 Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset;
1042 Instr immlo = imm << ImmPCRelLo_offset;
1043 return (immhi & ImmPCRelHi_mask) | (immlo & ImmPCRelLo_mask);
1047 Instr Assembler::ImmUncondBranch(int imm26) {
1048 CHECK(is_int26(imm26));
1049 return truncate_to_int26(imm26) << ImmUncondBranch_offset;
1053 Instr Assembler::ImmCondBranch(int imm19) {
1054 CHECK(is_int19(imm19));
1055 return truncate_to_int19(imm19) << ImmCondBranch_offset;
1059 Instr Assembler::ImmCmpBranch(int imm19) {
1060 CHECK(is_int19(imm19));
1061 return truncate_to_int19(imm19) << ImmCmpBranch_offset;
1065 Instr Assembler::ImmTestBranch(int imm14) {
1066 CHECK(is_int14(imm14));
1067 return truncate_to_int14(imm14) << ImmTestBranch_offset;
1071 Instr Assembler::ImmTestBranchBit(unsigned bit_pos) {
1072 DCHECK(is_uint6(bit_pos));
1073 // Subtract five from the shift offset, as we need bit 5 from bit_pos.
1074 unsigned b5 = bit_pos << (ImmTestBranchBit5_offset - 5);
1075 unsigned b40 = bit_pos << ImmTestBranchBit40_offset;
1076 b5 &= ImmTestBranchBit5_mask;
1077 b40 &= ImmTestBranchBit40_mask;
1082 Instr Assembler::SF(Register rd) {
1083 return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
1087 Instr Assembler::ImmAddSub(int64_t imm) {
1088 DCHECK(IsImmAddSub(imm));
1089 if (is_uint12(imm)) { // No shift required.
1090 return imm << ImmAddSub_offset;
1092 return ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
1097 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1098 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1099 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1101 return imms << ImmS_offset;
1105 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
1106 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1107 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1109 DCHECK(is_uint6(immr));
1110 return immr << ImmR_offset;
1114 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1115 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1116 DCHECK(is_uint6(imms));
1117 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1119 return imms << ImmSetBits_offset;
1123 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
1124 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1125 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1126 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1128 return immr << ImmRotate_offset;
1132 Instr Assembler::ImmLLiteral(int imm19) {
1133 CHECK(is_int19(imm19));
1134 return truncate_to_int19(imm19) << ImmLLiteral_offset;
1138 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
1139 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1140 DCHECK((reg_size == kXRegSizeInBits) || (bitn == 0));
1142 return bitn << BitN_offset;
1146 Instr Assembler::ShiftDP(Shift shift) {
1147 DCHECK(shift == LSL || shift == LSR || shift == ASR || shift == ROR);
1148 return shift << ShiftDP_offset;
1152 Instr Assembler::ImmDPShift(unsigned amount) {
1153 DCHECK(is_uint6(amount));
1154 return amount << ImmDPShift_offset;
1158 Instr Assembler::ExtendMode(Extend extend) {
1159 return extend << ExtendMode_offset;
1163 Instr Assembler::ImmExtendShift(unsigned left_shift) {
1164 DCHECK(left_shift <= 4);
1165 return left_shift << ImmExtendShift_offset;
1169 Instr Assembler::ImmCondCmp(unsigned imm) {
1170 DCHECK(is_uint5(imm));
1171 return imm << ImmCondCmp_offset;
1175 Instr Assembler::Nzcv(StatusFlags nzcv) {
1176 return ((nzcv >> Flags_offset) & 0xf) << Nzcv_offset;
1180 Instr Assembler::ImmLSUnsigned(int imm12) {
1181 DCHECK(is_uint12(imm12));
1182 return imm12 << ImmLSUnsigned_offset;
1186 Instr Assembler::ImmLS(int imm9) {
1187 DCHECK(is_int9(imm9));
1188 return truncate_to_int9(imm9) << ImmLS_offset;
1192 Instr Assembler::ImmLSPair(int imm7, LSDataSize size) {
1193 DCHECK(((imm7 >> size) << size) == imm7);
1194 int scaled_imm7 = imm7 >> size;
1195 DCHECK(is_int7(scaled_imm7));
1196 return truncate_to_int7(scaled_imm7) << ImmLSPair_offset;
1200 Instr Assembler::ImmShiftLS(unsigned shift_amount) {
1201 DCHECK(is_uint1(shift_amount));
1202 return shift_amount << ImmShiftLS_offset;
1206 Instr Assembler::ImmException(int imm16) {
1207 DCHECK(is_uint16(imm16));
1208 return imm16 << ImmException_offset;
1212 Instr Assembler::ImmSystemRegister(int imm15) {
1213 DCHECK(is_uint15(imm15));
1214 return imm15 << ImmSystemRegister_offset;
1218 Instr Assembler::ImmHint(int imm7) {
1219 DCHECK(is_uint7(imm7));
1220 return imm7 << ImmHint_offset;
1224 Instr Assembler::ImmBarrierDomain(int imm2) {
1225 DCHECK(is_uint2(imm2));
1226 return imm2 << ImmBarrierDomain_offset;
1230 Instr Assembler::ImmBarrierType(int imm2) {
1231 DCHECK(is_uint2(imm2));
1232 return imm2 << ImmBarrierType_offset;
1236 LSDataSize Assembler::CalcLSDataSize(LoadStoreOp op) {
1237 DCHECK((SizeLS_offset + SizeLS_width) == (kInstructionSize * 8));
1238 return static_cast<LSDataSize>(op >> SizeLS_offset);
1242 Instr Assembler::ImmMoveWide(uint64_t imm) {
1243 DCHECK(is_uint16(imm));
1244 return imm << ImmMoveWide_offset;
1248 Instr Assembler::ShiftMoveWide(int64_t shift) {
1249 DCHECK(is_uint2(shift));
1250 return shift << ShiftMoveWide_offset;
1254 Instr Assembler::FPType(FPRegister fd) {
1255 return fd.Is64Bits() ? FP64 : FP32;
1259 Instr Assembler::FPScale(unsigned scale) {
1260 DCHECK(is_uint6(scale));
1261 return scale << FPScale_offset;
1265 const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
1266 return reg.Is64Bits() ? xzr : wzr;
1270 inline void Assembler::CheckBufferSpace() {
1271 DCHECK(pc_ < (buffer_ + buffer_size_));
1272 if (buffer_space() < kGap) {
1278 inline void Assembler::CheckBuffer() {
1280 if (pc_offset() >= next_veneer_pool_check_) {
1281 CheckVeneerPool(false, true);
1283 if (pc_offset() >= next_constant_pool_check_) {
1284 CheckConstPool(false, true);
1289 TypeFeedbackId Assembler::RecordedAstId() {
1290 DCHECK(!recorded_ast_id_.IsNone());
1291 return recorded_ast_id_;
1295 void Assembler::ClearRecordedAstId() {
1296 recorded_ast_id_ = TypeFeedbackId::None();
1300 } } // namespace v8::internal
1302 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_