1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_
8 #include "src/arm64/assembler-arm64.h"
9 #include "src/assembler.h"
10 #include "src/debug.h"
17 bool CpuFeatures::SupportsCrankshaft() { return true; }
20 void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) {
25 void RelocInfo::set_target_address(Address target,
26 WriteBarrierMode write_barrier_mode,
27 ICacheFlushMode icache_flush_mode) {
28 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
29 Assembler::set_target_address_at(pc_, host_, target, icache_flush_mode);
30 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL &&
31 IsCodeTarget(rmode_)) {
32 Object* target_code = Code::GetCodeFromTargetAddress(target);
33 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
34 host(), this, HeapObject::cast(target_code));
39 inline unsigned CPURegister::code() const {
45 inline CPURegister::RegisterType CPURegister::type() const {
46 DCHECK(IsValidOrNone());
51 inline RegList CPURegister::Bit() const {
52 DCHECK(reg_code < (sizeof(RegList) * kBitsPerByte));
53 return IsValid() ? 1UL << reg_code : 0;
57 inline unsigned CPURegister::SizeInBits() const {
63 inline int CPURegister::SizeInBytes() const {
65 DCHECK(SizeInBits() % 8 == 0);
70 inline bool CPURegister::Is32Bits() const {
72 return reg_size == 32;
76 inline bool CPURegister::Is64Bits() const {
78 return reg_size == 64;
82 inline bool CPURegister::IsValid() const {
83 if (IsValidRegister() || IsValidFPRegister()) {
93 inline bool CPURegister::IsValidRegister() const {
94 return IsRegister() &&
95 ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) &&
96 ((reg_code < kNumberOfRegisters) || (reg_code == kSPRegInternalCode));
100 inline bool CPURegister::IsValidFPRegister() const {
101 return IsFPRegister() &&
102 ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) &&
103 (reg_code < kNumberOfFPRegisters);
107 inline bool CPURegister::IsNone() const {
108 // kNoRegister types should always have size 0 and code 0.
109 DCHECK((reg_type != kNoRegister) || (reg_code == 0));
110 DCHECK((reg_type != kNoRegister) || (reg_size == 0));
112 return reg_type == kNoRegister;
116 inline bool CPURegister::Is(const CPURegister& other) const {
117 DCHECK(IsValidOrNone() && other.IsValidOrNone());
118 return Aliases(other) && (reg_size == other.reg_size);
122 inline bool CPURegister::Aliases(const CPURegister& other) const {
123 DCHECK(IsValidOrNone() && other.IsValidOrNone());
124 return (reg_code == other.reg_code) && (reg_type == other.reg_type);
128 inline bool CPURegister::IsRegister() const {
129 return reg_type == kRegister;
133 inline bool CPURegister::IsFPRegister() const {
134 return reg_type == kFPRegister;
138 inline bool CPURegister::IsSameSizeAndType(const CPURegister& other) const {
139 return (reg_size == other.reg_size) && (reg_type == other.reg_type);
143 inline bool CPURegister::IsValidOrNone() const {
144 return IsValid() || IsNone();
148 inline bool CPURegister::IsZero() const {
150 return IsRegister() && (reg_code == kZeroRegCode);
154 inline bool CPURegister::IsSP() const {
156 return IsRegister() && (reg_code == kSPRegInternalCode);
160 inline void CPURegList::Combine(const CPURegList& other) {
162 DCHECK(other.type() == type_);
163 DCHECK(other.RegisterSizeInBits() == size_);
164 list_ |= other.list();
168 inline void CPURegList::Remove(const CPURegList& other) {
170 if (other.type() == type_) {
171 list_ &= ~other.list();
176 inline void CPURegList::Combine(const CPURegister& other) {
177 DCHECK(other.type() == type_);
178 DCHECK(other.SizeInBits() == size_);
179 Combine(other.code());
183 inline void CPURegList::Remove(const CPURegister& other1,
184 const CPURegister& other2,
185 const CPURegister& other3,
186 const CPURegister& other4) {
187 if (!other1.IsNone() && (other1.type() == type_)) Remove(other1.code());
188 if (!other2.IsNone() && (other2.type() == type_)) Remove(other2.code());
189 if (!other3.IsNone() && (other3.type() == type_)) Remove(other3.code());
190 if (!other4.IsNone() && (other4.type() == type_)) Remove(other4.code());
194 inline void CPURegList::Combine(int code) {
196 DCHECK(CPURegister::Create(code, size_, type_).IsValid());
197 list_ |= (1UL << code);
201 inline void CPURegList::Remove(int code) {
203 DCHECK(CPURegister::Create(code, size_, type_).IsValid());
204 list_ &= ~(1UL << code);
208 inline Register Register::XRegFromCode(unsigned code) {
209 if (code == kSPRegInternalCode) {
212 DCHECK(code < kNumberOfRegisters);
213 return Register::Create(code, kXRegSizeInBits);
218 inline Register Register::WRegFromCode(unsigned code) {
219 if (code == kSPRegInternalCode) {
222 DCHECK(code < kNumberOfRegisters);
223 return Register::Create(code, kWRegSizeInBits);
228 inline FPRegister FPRegister::SRegFromCode(unsigned code) {
229 DCHECK(code < kNumberOfFPRegisters);
230 return FPRegister::Create(code, kSRegSizeInBits);
234 inline FPRegister FPRegister::DRegFromCode(unsigned code) {
235 DCHECK(code < kNumberOfFPRegisters);
236 return FPRegister::Create(code, kDRegSizeInBits);
240 inline Register CPURegister::W() const {
241 DCHECK(IsValidRegister());
242 return Register::WRegFromCode(reg_code);
246 inline Register CPURegister::X() const {
247 DCHECK(IsValidRegister());
248 return Register::XRegFromCode(reg_code);
252 inline FPRegister CPURegister::S() const {
253 DCHECK(IsValidFPRegister());
254 return FPRegister::SRegFromCode(reg_code);
258 inline FPRegister CPURegister::D() const {
259 DCHECK(IsValidFPRegister());
260 return FPRegister::DRegFromCode(reg_code);
265 // Default initializer is for int types
267 struct ImmediateInitializer {
268 static const bool kIsIntType = true;
269 static inline RelocInfo::Mode rmode_for(T) {
270 return sizeof(T) == 8 ? RelocInfo::NONE64 : RelocInfo::NONE32;
272 static inline int64_t immediate_for(T t) {
273 STATIC_ASSERT(sizeof(T) <= 8);
280 struct ImmediateInitializer<Smi*> {
281 static const bool kIsIntType = false;
282 static inline RelocInfo::Mode rmode_for(Smi* t) {
283 return RelocInfo::NONE64;
285 static inline int64_t immediate_for(Smi* t) {;
286 return reinterpret_cast<int64_t>(t);
292 struct ImmediateInitializer<ExternalReference> {
293 static const bool kIsIntType = false;
294 static inline RelocInfo::Mode rmode_for(ExternalReference t) {
295 return RelocInfo::EXTERNAL_REFERENCE;
297 static inline int64_t immediate_for(ExternalReference t) {;
298 return reinterpret_cast<int64_t>(t.address());
304 Immediate::Immediate(Handle<T> value) {
305 InitializeHandle(value);
310 Immediate::Immediate(T t)
311 : value_(ImmediateInitializer<T>::immediate_for(t)),
312 rmode_(ImmediateInitializer<T>::rmode_for(t)) {}
316 Immediate::Immediate(T t, RelocInfo::Mode rmode)
317 : value_(ImmediateInitializer<T>::immediate_for(t)),
319 STATIC_ASSERT(ImmediateInitializer<T>::kIsIntType);
325 Operand::Operand(Handle<T> value) : immediate_(value), reg_(NoReg) {}
329 Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
333 Operand::Operand(T t, RelocInfo::Mode rmode)
334 : immediate_(t, rmode),
338 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
343 shift_amount_(shift_amount) {
344 DCHECK(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
345 DCHECK(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
350 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
355 shift_amount_(shift_amount) {
356 DCHECK(reg.IsValid());
357 DCHECK(shift_amount <= 4);
360 // Extend modes SXTX and UXTX require a 64-bit register.
361 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
365 bool Operand::IsImmediate() const {
366 return reg_.Is(NoReg);
370 bool Operand::IsShiftedRegister() const {
371 return reg_.IsValid() && (shift_ != NO_SHIFT);
375 bool Operand::IsExtendedRegister() const {
376 return reg_.IsValid() && (extend_ != NO_EXTEND);
380 bool Operand::IsZero() const {
382 return ImmediateValue() == 0;
384 return reg().IsZero();
389 Operand Operand::ToExtendedRegister() const {
390 DCHECK(IsShiftedRegister());
391 DCHECK((shift_ == LSL) && (shift_amount_ <= 4));
392 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
396 Immediate Operand::immediate() const {
397 DCHECK(IsImmediate());
402 int64_t Operand::ImmediateValue() const {
403 DCHECK(IsImmediate());
404 return immediate_.value();
408 Register Operand::reg() const {
409 DCHECK(IsShiftedRegister() || IsExtendedRegister());
414 Shift Operand::shift() const {
415 DCHECK(IsShiftedRegister());
420 Extend Operand::extend() const {
421 DCHECK(IsExtendedRegister());
426 unsigned Operand::shift_amount() const {
427 DCHECK(IsShiftedRegister() || IsExtendedRegister());
428 return shift_amount_;
432 Operand Operand::UntagSmi(Register smi) {
433 STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift +
435 DCHECK(smi.Is64Bits());
436 return Operand(smi, ASR, kSmiShift);
440 Operand Operand::UntagSmiAndScale(Register smi, int scale) {
441 STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift +
443 DCHECK(smi.Is64Bits());
444 DCHECK((scale >= 0) && (scale <= (64 - kSmiValueSize)));
445 if (scale > kSmiShift) {
446 return Operand(smi, LSL, scale - kSmiShift);
447 } else if (scale < kSmiShift) {
448 return Operand(smi, ASR, kSmiShift - scale);
454 MemOperand::MemOperand()
455 : base_(NoReg), regoffset_(NoReg), offset_(0), addrmode_(Offset),
456 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
460 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
461 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
462 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
463 DCHECK(base.Is64Bits() && !base.IsZero());
467 MemOperand::MemOperand(Register base,
470 unsigned shift_amount)
471 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
472 shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) {
473 DCHECK(base.Is64Bits() && !base.IsZero());
474 DCHECK(!regoffset.IsSP());
475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
477 // SXTX extend mode requires a 64-bit offset register.
478 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
482 MemOperand::MemOperand(Register base,
485 unsigned shift_amount)
486 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
487 shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
488 DCHECK(base.Is64Bits() && !base.IsZero());
489 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
490 DCHECK(shift == LSL);
494 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
495 : base_(base), addrmode_(addrmode) {
496 DCHECK(base.Is64Bits() && !base.IsZero());
498 if (offset.IsImmediate()) {
499 offset_ = offset.ImmediateValue();
502 } else if (offset.IsShiftedRegister()) {
503 DCHECK(addrmode == Offset);
505 regoffset_ = offset.reg();
506 shift_ = offset.shift();
507 shift_amount_ = offset.shift_amount();
512 // These assertions match those in the shifted-register constructor.
513 DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());
514 DCHECK(shift_ == LSL);
516 DCHECK(offset.IsExtendedRegister());
517 DCHECK(addrmode == Offset);
519 regoffset_ = offset.reg();
520 extend_ = offset.extend();
521 shift_amount_ = offset.shift_amount();
526 // These assertions match those in the extended-register constructor.
527 DCHECK(!regoffset_.IsSP());
528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
529 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
533 bool MemOperand::IsImmediateOffset() const {
534 return (addrmode_ == Offset) && regoffset_.Is(NoReg);
538 bool MemOperand::IsRegisterOffset() const {
539 return (addrmode_ == Offset) && !regoffset_.Is(NoReg);
543 bool MemOperand::IsPreIndex() const {
544 return addrmode_ == PreIndex;
548 bool MemOperand::IsPostIndex() const {
549 return addrmode_ == PostIndex;
552 Operand MemOperand::OffsetAsOperand() const {
553 if (IsImmediateOffset()) {
556 DCHECK(IsRegisterOffset());
557 if (extend() == NO_EXTEND) {
558 return Operand(regoffset(), shift(), shift_amount());
560 return Operand(regoffset(), extend(), shift_amount());
566 void Assembler::Unreachable() {
568 debug("UNREACHABLE", __LINE__, BREAK);
570 // Crash by branching to 0. lr now points near the fault.
576 Address Assembler::target_pointer_address_at(Address pc) {
577 Instruction* instr = reinterpret_cast<Instruction*>(pc);
578 DCHECK(instr->IsLdrLiteralX());
579 return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
583 // Read/Modify the code target address in the branch/call instruction at pc.
584 Address Assembler::target_address_at(Address pc,
585 ConstantPoolArray* constant_pool) {
586 return Memory::Address_at(target_pointer_address_at(pc));
590 Address Assembler::target_address_at(Address pc, Code* code) {
591 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
592 return target_address_at(pc, constant_pool);
596 Address Assembler::target_address_from_return_address(Address pc) {
597 // Returns the address of the call target from the return address that will
598 // be returned to after a call.
599 // Call sequence on ARM64 is:
600 // ldr ip0, #... @ load from literal pool
602 Address candidate = pc - 2 * kInstructionSize;
603 Instruction* instr = reinterpret_cast<Instruction*>(candidate);
605 DCHECK(instr->IsLdrLiteralX());
610 Address Assembler::break_address_from_return_address(Address pc) {
611 return pc - Assembler::kPatchDebugBreakSlotReturnOffset;
615 Address Assembler::return_address_from_call_start(Address pc) {
616 // The call, generated by MacroAssembler::Call, is one of two possible
619 // Without relocation:
620 // movz temp, #(target & 0x000000000000ffff)
621 // movk temp, #(target & 0x00000000ffff0000)
622 // movk temp, #(target & 0x0000ffff00000000)
629 // The return address is immediately after the blr instruction in both cases,
630 // so it can be found by adding the call size to the address at the start of
631 // the call sequence.
632 STATIC_ASSERT(Assembler::kCallSizeWithoutRelocation == 4 * kInstructionSize);
633 STATIC_ASSERT(Assembler::kCallSizeWithRelocation == 2 * kInstructionSize);
635 Instruction* instr = reinterpret_cast<Instruction*>(pc);
636 if (instr->IsMovz()) {
637 // Verify the instruction sequence.
638 DCHECK(instr->following(1)->IsMovk());
639 DCHECK(instr->following(2)->IsMovk());
640 DCHECK(instr->following(3)->IsBranchAndLinkToRegister());
641 return pc + Assembler::kCallSizeWithoutRelocation;
643 // Verify the instruction sequence.
644 DCHECK(instr->IsLdrLiteralX());
645 DCHECK(instr->following(1)->IsBranchAndLinkToRegister());
646 return pc + Assembler::kCallSizeWithRelocation;
651 void Assembler::deserialization_set_special_target_at(
652 Address constant_pool_entry, Code* code, Address target) {
653 Memory::Address_at(constant_pool_entry) = target;
657 void Assembler::set_target_address_at(Address pc,
658 ConstantPoolArray* constant_pool,
660 ICacheFlushMode icache_flush_mode) {
661 Memory::Address_at(target_pointer_address_at(pc)) = target;
662 // Intuitively, we would think it is necessary to always flush the
663 // instruction cache after patching a target address in the code as follows:
664 // CpuFeatures::FlushICache(pc, sizeof(target));
665 // However, on ARM, an instruction is actually patched in the case of
666 // embedded constants of the form:
667 // ldr ip, [pc, #...]
668 // since the instruction accessing this address in the constant pool remains
669 // unchanged, a flush is not required.
673 void Assembler::set_target_address_at(Address pc,
676 ICacheFlushMode icache_flush_mode) {
677 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
678 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
682 int RelocInfo::target_address_size() {
687 Address RelocInfo::target_address() {
688 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
689 return Assembler::target_address_at(pc_, host_);
693 Address RelocInfo::target_address_address() {
694 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
695 || rmode_ == EMBEDDED_OBJECT
696 || rmode_ == EXTERNAL_REFERENCE);
697 return Assembler::target_pointer_address_at(pc_);
701 Address RelocInfo::constant_pool_entry_address() {
702 DCHECK(IsInConstantPool());
703 return Assembler::target_pointer_address_at(pc_);
707 Object* RelocInfo::target_object() {
708 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
709 return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_));
713 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
714 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
715 return Handle<Object>(reinterpret_cast<Object**>(
716 Assembler::target_address_at(pc_, host_)));
720 void RelocInfo::set_target_object(Object* target,
721 WriteBarrierMode write_barrier_mode,
722 ICacheFlushMode icache_flush_mode) {
723 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
724 Assembler::set_target_address_at(pc_, host_,
725 reinterpret_cast<Address>(target),
727 if (write_barrier_mode == UPDATE_WRITE_BARRIER &&
729 target->IsHeapObject()) {
730 host()->GetHeap()->incremental_marking()->RecordWrite(
731 host(), &Memory::Object_at(pc_), HeapObject::cast(target));
736 Address RelocInfo::target_reference() {
737 DCHECK(rmode_ == EXTERNAL_REFERENCE);
738 return Assembler::target_address_at(pc_, host_);
742 Address RelocInfo::target_runtime_entry(Assembler* origin) {
743 DCHECK(IsRuntimeEntry(rmode_));
744 return target_address();
748 void RelocInfo::set_target_runtime_entry(Address target,
749 WriteBarrierMode write_barrier_mode,
750 ICacheFlushMode icache_flush_mode) {
751 DCHECK(IsRuntimeEntry(rmode_));
752 if (target_address() != target) {
753 set_target_address(target, write_barrier_mode, icache_flush_mode);
758 Handle<Cell> RelocInfo::target_cell_handle() {
760 Cell *null_cell = NULL;
761 return Handle<Cell>(null_cell);
765 Cell* RelocInfo::target_cell() {
766 DCHECK(rmode_ == RelocInfo::CELL);
767 return Cell::FromValueAddress(Memory::Address_at(pc_));
771 void RelocInfo::set_target_cell(Cell* cell,
772 WriteBarrierMode write_barrier_mode,
773 ICacheFlushMode icache_flush_mode) {
778 static const int kNoCodeAgeSequenceLength = 5 * kInstructionSize;
779 static const int kCodeAgeStubEntryOffset = 3 * kInstructionSize;
782 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
783 UNREACHABLE(); // This should never be reached on ARM64.
784 return Handle<Object>();
788 Code* RelocInfo::code_age_stub() {
789 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
790 // Read the stub entry point from the code age sequence.
791 Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
792 return Code::GetCodeFromTargetAddress(Memory::Address_at(stub_entry_address));
796 void RelocInfo::set_code_age_stub(Code* stub,
797 ICacheFlushMode icache_flush_mode) {
798 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
799 DCHECK(!Code::IsYoungSequence(stub->GetIsolate(), pc_));
800 // Overwrite the stub entry point in the code age sequence. This is loaded as
801 // a literal so there is no need to call FlushICache here.
802 Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
803 Memory::Address_at(stub_entry_address) = stub->instruction_start();
807 Address RelocInfo::call_address() {
808 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
809 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
810 // For the above sequences the Relocinfo points to the load literal loading
812 return Assembler::target_address_at(pc_, host_);
816 void RelocInfo::set_call_address(Address target) {
817 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
818 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
819 Assembler::set_target_address_at(pc_, host_, target);
820 if (host() != NULL) {
821 Object* target_code = Code::GetCodeFromTargetAddress(target);
822 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
823 host(), this, HeapObject::cast(target_code));
828 void RelocInfo::WipeOut() {
829 DCHECK(IsEmbeddedObject(rmode_) ||
830 IsCodeTarget(rmode_) ||
831 IsRuntimeEntry(rmode_) ||
832 IsExternalReference(rmode_));
833 Assembler::set_target_address_at(pc_, host_, NULL);
837 bool RelocInfo::IsPatchedReturnSequence() {
838 // The sequence must be:
839 // ldr ip0, [pc, #offset]
841 // See arm64/debug-arm64.cc BreakLocationIterator::SetDebugBreakAtReturn().
842 Instruction* i1 = reinterpret_cast<Instruction*>(pc_);
843 Instruction* i2 = i1->following();
844 return i1->IsLdrLiteralX() && (i1->Rt() == ip0.code()) &&
845 i2->IsBranchAndLinkToRegister() && (i2->Rn() == ip0.code());
849 bool RelocInfo::IsPatchedDebugBreakSlotSequence() {
850 Instruction* current_instr = reinterpret_cast<Instruction*>(pc_);
851 return !current_instr->IsNop(Assembler::DEBUG_BREAK_NOP);
855 void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
856 RelocInfo::Mode mode = rmode();
857 if (mode == RelocInfo::EMBEDDED_OBJECT) {
858 visitor->VisitEmbeddedPointer(this);
859 } else if (RelocInfo::IsCodeTarget(mode)) {
860 visitor->VisitCodeTarget(this);
861 } else if (mode == RelocInfo::CELL) {
862 visitor->VisitCell(this);
863 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
864 visitor->VisitExternalReference(this);
865 } else if (((RelocInfo::IsJSReturn(mode) &&
866 IsPatchedReturnSequence()) ||
867 (RelocInfo::IsDebugBreakSlot(mode) &&
868 IsPatchedDebugBreakSlotSequence())) &&
869 isolate->debug()->has_break_points()) {
870 visitor->VisitDebugTarget(this);
871 } else if (RelocInfo::IsRuntimeEntry(mode)) {
872 visitor->VisitRuntimeEntry(this);
877 template<typename StaticVisitor>
878 void RelocInfo::Visit(Heap* heap) {
879 RelocInfo::Mode mode = rmode();
880 if (mode == RelocInfo::EMBEDDED_OBJECT) {
881 StaticVisitor::VisitEmbeddedPointer(heap, this);
882 } else if (RelocInfo::IsCodeTarget(mode)) {
883 StaticVisitor::VisitCodeTarget(heap, this);
884 } else if (mode == RelocInfo::CELL) {
885 StaticVisitor::VisitCell(heap, this);
886 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
887 StaticVisitor::VisitExternalReference(this);
888 } else if (heap->isolate()->debug()->has_break_points() &&
889 ((RelocInfo::IsJSReturn(mode) &&
890 IsPatchedReturnSequence()) ||
891 (RelocInfo::IsDebugBreakSlot(mode) &&
892 IsPatchedDebugBreakSlotSequence()))) {
893 StaticVisitor::VisitDebugTarget(heap, this);
894 } else if (RelocInfo::IsRuntimeEntry(mode)) {
895 StaticVisitor::VisitRuntimeEntry(this);
900 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
901 DCHECK(rt.IsValid());
902 if (rt.IsRegister()) {
903 return rt.Is64Bits() ? LDR_x : LDR_w;
905 DCHECK(rt.IsFPRegister());
906 return rt.Is64Bits() ? LDR_d : LDR_s;
911 LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
912 const CPURegister& rt2) {
913 DCHECK(AreSameSizeAndType(rt, rt2));
915 if (rt.IsRegister()) {
916 return rt.Is64Bits() ? LDP_x : LDP_w;
918 DCHECK(rt.IsFPRegister());
919 return rt.Is64Bits() ? LDP_d : LDP_s;
924 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
925 DCHECK(rt.IsValid());
926 if (rt.IsRegister()) {
927 return rt.Is64Bits() ? STR_x : STR_w;
929 DCHECK(rt.IsFPRegister());
930 return rt.Is64Bits() ? STR_d : STR_s;
935 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
936 const CPURegister& rt2) {
937 DCHECK(AreSameSizeAndType(rt, rt2));
939 if (rt.IsRegister()) {
940 return rt.Is64Bits() ? STP_x : STP_w;
942 DCHECK(rt.IsFPRegister());
943 return rt.Is64Bits() ? STP_d : STP_s;
948 LoadStorePairNonTemporalOp Assembler::LoadPairNonTemporalOpFor(
949 const CPURegister& rt, const CPURegister& rt2) {
950 DCHECK(AreSameSizeAndType(rt, rt2));
952 if (rt.IsRegister()) {
953 return rt.Is64Bits() ? LDNP_x : LDNP_w;
955 DCHECK(rt.IsFPRegister());
956 return rt.Is64Bits() ? LDNP_d : LDNP_s;
961 LoadStorePairNonTemporalOp Assembler::StorePairNonTemporalOpFor(
962 const CPURegister& rt, const CPURegister& rt2) {
963 DCHECK(AreSameSizeAndType(rt, rt2));
965 if (rt.IsRegister()) {
966 return rt.Is64Bits() ? STNP_x : STNP_w;
968 DCHECK(rt.IsFPRegister());
969 return rt.Is64Bits() ? STNP_d : STNP_s;
974 LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
975 if (rt.IsRegister()) {
976 return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit;
978 DCHECK(rt.IsFPRegister());
979 return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit;
984 int Assembler::LinkAndGetInstructionOffsetTo(Label* label) {
985 DCHECK(kStartOfLabelLinkChain == 0);
986 int offset = LinkAndGetByteOffsetTo(label);
987 DCHECK(IsAligned(offset, kInstructionSize));
988 return offset >> kInstructionSizeLog2;
992 Instr Assembler::Flags(FlagsUpdate S) {
994 return 1 << FlagsUpdate_offset;
995 } else if (S == LeaveFlags) {
996 return 0 << FlagsUpdate_offset;
1003 Instr Assembler::Cond(Condition cond) {
1004 return cond << Condition_offset;
1008 Instr Assembler::ImmPCRelAddress(int imm21) {
1009 CHECK(is_int21(imm21));
1010 Instr imm = static_cast<Instr>(truncate_to_int21(imm21));
1011 Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset;
1012 Instr immlo = imm << ImmPCRelLo_offset;
1013 return (immhi & ImmPCRelHi_mask) | (immlo & ImmPCRelLo_mask);
1017 Instr Assembler::ImmUncondBranch(int imm26) {
1018 CHECK(is_int26(imm26));
1019 return truncate_to_int26(imm26) << ImmUncondBranch_offset;
1023 Instr Assembler::ImmCondBranch(int imm19) {
1024 CHECK(is_int19(imm19));
1025 return truncate_to_int19(imm19) << ImmCondBranch_offset;
1029 Instr Assembler::ImmCmpBranch(int imm19) {
1030 CHECK(is_int19(imm19));
1031 return truncate_to_int19(imm19) << ImmCmpBranch_offset;
1035 Instr Assembler::ImmTestBranch(int imm14) {
1036 CHECK(is_int14(imm14));
1037 return truncate_to_int14(imm14) << ImmTestBranch_offset;
1041 Instr Assembler::ImmTestBranchBit(unsigned bit_pos) {
1042 DCHECK(is_uint6(bit_pos));
1043 // Subtract five from the shift offset, as we need bit 5 from bit_pos.
1044 unsigned b5 = bit_pos << (ImmTestBranchBit5_offset - 5);
1045 unsigned b40 = bit_pos << ImmTestBranchBit40_offset;
1046 b5 &= ImmTestBranchBit5_mask;
1047 b40 &= ImmTestBranchBit40_mask;
1052 Instr Assembler::SF(Register rd) {
1053 return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
1057 Instr Assembler::ImmAddSub(int64_t imm) {
1058 DCHECK(IsImmAddSub(imm));
1059 if (is_uint12(imm)) { // No shift required.
1060 return imm << ImmAddSub_offset;
1062 return ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
1067 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1068 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1069 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1071 return imms << ImmS_offset;
1075 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
1076 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1077 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1079 DCHECK(is_uint6(immr));
1080 return immr << ImmR_offset;
1084 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1085 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1086 DCHECK(is_uint6(imms));
1087 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1089 return imms << ImmSetBits_offset;
1093 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
1094 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1095 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1096 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1098 return immr << ImmRotate_offset;
1102 Instr Assembler::ImmLLiteral(int imm19) {
1103 CHECK(is_int19(imm19));
1104 return truncate_to_int19(imm19) << ImmLLiteral_offset;
1108 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
1109 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1110 DCHECK((reg_size == kXRegSizeInBits) || (bitn == 0));
1112 return bitn << BitN_offset;
1116 Instr Assembler::ShiftDP(Shift shift) {
1117 DCHECK(shift == LSL || shift == LSR || shift == ASR || shift == ROR);
1118 return shift << ShiftDP_offset;
1122 Instr Assembler::ImmDPShift(unsigned amount) {
1123 DCHECK(is_uint6(amount));
1124 return amount << ImmDPShift_offset;
1128 Instr Assembler::ExtendMode(Extend extend) {
1129 return extend << ExtendMode_offset;
1133 Instr Assembler::ImmExtendShift(unsigned left_shift) {
1134 DCHECK(left_shift <= 4);
1135 return left_shift << ImmExtendShift_offset;
1139 Instr Assembler::ImmCondCmp(unsigned imm) {
1140 DCHECK(is_uint5(imm));
1141 return imm << ImmCondCmp_offset;
1145 Instr Assembler::Nzcv(StatusFlags nzcv) {
1146 return ((nzcv >> Flags_offset) & 0xf) << Nzcv_offset;
1150 Instr Assembler::ImmLSUnsigned(int imm12) {
1151 DCHECK(is_uint12(imm12));
1152 return imm12 << ImmLSUnsigned_offset;
1156 Instr Assembler::ImmLS(int imm9) {
1157 DCHECK(is_int9(imm9));
1158 return truncate_to_int9(imm9) << ImmLS_offset;
1162 Instr Assembler::ImmLSPair(int imm7, LSDataSize size) {
1163 DCHECK(((imm7 >> size) << size) == imm7);
1164 int scaled_imm7 = imm7 >> size;
1165 DCHECK(is_int7(scaled_imm7));
1166 return truncate_to_int7(scaled_imm7) << ImmLSPair_offset;
1170 Instr Assembler::ImmShiftLS(unsigned shift_amount) {
1171 DCHECK(is_uint1(shift_amount));
1172 return shift_amount << ImmShiftLS_offset;
1176 Instr Assembler::ImmException(int imm16) {
1177 DCHECK(is_uint16(imm16));
1178 return imm16 << ImmException_offset;
1182 Instr Assembler::ImmSystemRegister(int imm15) {
1183 DCHECK(is_uint15(imm15));
1184 return imm15 << ImmSystemRegister_offset;
1188 Instr Assembler::ImmHint(int imm7) {
1189 DCHECK(is_uint7(imm7));
1190 return imm7 << ImmHint_offset;
1194 Instr Assembler::ImmBarrierDomain(int imm2) {
1195 DCHECK(is_uint2(imm2));
1196 return imm2 << ImmBarrierDomain_offset;
1200 Instr Assembler::ImmBarrierType(int imm2) {
1201 DCHECK(is_uint2(imm2));
1202 return imm2 << ImmBarrierType_offset;
1206 LSDataSize Assembler::CalcLSDataSize(LoadStoreOp op) {
1207 DCHECK((SizeLS_offset + SizeLS_width) == (kInstructionSize * 8));
1208 return static_cast<LSDataSize>(op >> SizeLS_offset);
1212 Instr Assembler::ImmMoveWide(uint64_t imm) {
1213 DCHECK(is_uint16(imm));
1214 return imm << ImmMoveWide_offset;
1218 Instr Assembler::ShiftMoveWide(int64_t shift) {
1219 DCHECK(is_uint2(shift));
1220 return shift << ShiftMoveWide_offset;
1224 Instr Assembler::FPType(FPRegister fd) {
1225 return fd.Is64Bits() ? FP64 : FP32;
1229 Instr Assembler::FPScale(unsigned scale) {
1230 DCHECK(is_uint6(scale));
1231 return scale << FPScale_offset;
1235 const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
1236 return reg.Is64Bits() ? xzr : wzr;
1240 inline void Assembler::CheckBufferSpace() {
1241 DCHECK(pc_ < (buffer_ + buffer_size_));
1242 if (buffer_space() < kGap) {
1248 inline void Assembler::CheckBuffer() {
1250 if (pc_offset() >= next_veneer_pool_check_) {
1251 CheckVeneerPool(false, true);
1253 if (pc_offset() >= next_constant_pool_check_) {
1254 CheckConstPool(false, true);
1259 TypeFeedbackId Assembler::RecordedAstId() {
1260 DCHECK(!recorded_ast_id_.IsNone());
1261 return recorded_ast_id_;
1265 void Assembler::ClearRecordedAstId() {
1266 recorded_ast_id_ = TypeFeedbackId::None();
1270 } } // namespace v8::internal
1272 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_