1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
11 #if V8_TARGET_ARCH_ARM
13 #include "src/arm/constants-arm.h"
14 #include "src/arm/simulator-arm.h"
15 #include "src/assembler.h"
16 #include "src/base/bits.h"
17 #include "src/codegen.h"
18 #include "src/disasm.h"
20 #if defined(USE_SIMULATOR)
22 // Only build the simulator if not compiling for real ARM hardware.
26 // This macro provides a platform independent use of sscanf. The reason for
27 // SScanF not being implemented in a platform independent way through
28 // ::v8::internal::OS in the same way as SNPrintF is that the
29 // Windows C Run-Time Library does not provide vsscanf.
30 #define SScanF sscanf // NOLINT
32 // The ArmDebugger class is used by the simulator while debugging simulated ARM
36 explicit ArmDebugger(Simulator* sim) : sim_(sim) { }
39 void Stop(Instruction* instr);
43 static const Instr kBreakpointInstr =
44 (al | (7*B25) | (1*B24) | kBreakpoint);
45 static const Instr kNopInstr = (al | (13*B21));
49 int32_t GetRegisterValue(int regnum);
50 double GetRegisterPairDoubleValue(int regnum);
51 double GetVFPDoubleRegisterValue(int regnum);
52 bool GetValue(const char* desc, int32_t* value);
53 bool GetVFPSingleValue(const char* desc, float* value);
54 bool GetVFPDoubleValue(const char* desc, double* value);
56 // Set or delete a breakpoint. Returns true if successful.
57 bool SetBreakpoint(Instruction* breakpc);
58 bool DeleteBreakpoint(Instruction* breakpc);
60 // Undo and redo all breakpoints. This is needed to bracket disassembly and
61 // execution to skip past breakpoints when run from the debugger.
62 void UndoBreakpoints();
63 void RedoBreakpoints();
67 ArmDebugger::~ArmDebugger() {
72 #ifdef GENERATED_CODE_COVERAGE
73 static FILE* coverage_log = NULL;
76 static void InitializeCoverage() {
77 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
78 if (file_name != NULL) {
79 coverage_log = fopen(file_name, "aw+");
84 void ArmDebugger::Stop(Instruction* instr) {
86 uint32_t code = instr->SvcValue() & kStopCodeMask;
87 // Retrieve the encoded address, which comes just after this stop.
89 reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize);
90 char* msg = *msg_address;
93 // Update this stop description.
94 if (isWatchedStop(code) && !watched_stops_[code].desc) {
95 watched_stops_[code].desc = msg;
98 if (strlen(msg) > 0) {
99 if (coverage_log != NULL) {
100 fprintf(coverage_log, "%s\n", msg);
101 fflush(coverage_log);
103 // Overwrite the instruction and address with nops.
104 instr->SetInstructionBits(kNopInstr);
105 reinterpret_cast<Instruction*>(msg_address)->SetInstructionBits(kNopInstr);
107 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
110 #else // ndef GENERATED_CODE_COVERAGE
112 static void InitializeCoverage() {
116 void ArmDebugger::Stop(Instruction* instr) {
117 // Get the stop code.
118 uint32_t code = instr->SvcValue() & kStopCodeMask;
119 // Retrieve the encoded address, which comes just after this stop.
120 char* msg = *reinterpret_cast<char**>(sim_->get_pc()
121 + Instruction::kInstrSize);
122 // Update this stop description.
123 if (sim_->isWatchedStop(code) && !sim_->watched_stops_[code].desc) {
124 sim_->watched_stops_[code].desc = msg;
126 // Print the stop message and code if it is not the default code.
127 if (code != kMaxStopCode) {
128 PrintF("Simulator hit stop %u: %s\n", code, msg);
130 PrintF("Simulator hit %s\n", msg);
132 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
138 int32_t ArmDebugger::GetRegisterValue(int regnum) {
139 if (regnum == kPCRegister) {
140 return sim_->get_pc();
142 return sim_->get_register(regnum);
147 double ArmDebugger::GetRegisterPairDoubleValue(int regnum) {
148 return sim_->get_double_from_register_pair(regnum);
152 double ArmDebugger::GetVFPDoubleRegisterValue(int regnum) {
153 return sim_->get_double_from_d_register(regnum);
157 bool ArmDebugger::GetValue(const char* desc, int32_t* value) {
158 int regnum = Registers::Number(desc);
159 if (regnum != kNoRegister) {
160 *value = GetRegisterValue(regnum);
163 if (strncmp(desc, "0x", 2) == 0) {
164 return SScanF(desc + 2, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
166 return SScanF(desc, "%u", reinterpret_cast<uint32_t*>(value)) == 1;
173 bool ArmDebugger::GetVFPSingleValue(const char* desc, float* value) {
175 int regnum = VFPRegisters::Number(desc, &is_double);
176 if (regnum != kNoRegister && !is_double) {
177 *value = sim_->get_float_from_s_register(regnum);
184 bool ArmDebugger::GetVFPDoubleValue(const char* desc, double* value) {
186 int regnum = VFPRegisters::Number(desc, &is_double);
187 if (regnum != kNoRegister && is_double) {
188 *value = sim_->get_double_from_d_register(regnum);
195 bool ArmDebugger::SetBreakpoint(Instruction* breakpc) {
196 // Check if a breakpoint can be set. If not return without any side-effects.
197 if (sim_->break_pc_ != NULL) {
201 // Set the breakpoint.
202 sim_->break_pc_ = breakpc;
203 sim_->break_instr_ = breakpc->InstructionBits();
204 // Not setting the breakpoint instruction in the code itself. It will be set
205 // when the debugger shell continues.
210 bool ArmDebugger::DeleteBreakpoint(Instruction* breakpc) {
211 if (sim_->break_pc_ != NULL) {
212 sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
215 sim_->break_pc_ = NULL;
216 sim_->break_instr_ = 0;
221 void ArmDebugger::UndoBreakpoints() {
222 if (sim_->break_pc_ != NULL) {
223 sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
228 void ArmDebugger::RedoBreakpoints() {
229 if (sim_->break_pc_ != NULL) {
230 sim_->break_pc_->SetInstructionBits(kBreakpointInstr);
235 void ArmDebugger::Debug() {
236 intptr_t last_pc = -1;
239 #define COMMAND_SIZE 63
243 #define XSTR(a) STR(a)
245 char cmd[COMMAND_SIZE + 1];
246 char arg1[ARG_SIZE + 1];
247 char arg2[ARG_SIZE + 1];
248 char* argv[3] = { cmd, arg1, arg2 };
250 // make sure to have a proper terminating character if reaching the limit
251 cmd[COMMAND_SIZE] = 0;
255 // Undo all set breakpoints while running in the debugger shell. This will
256 // make them invisible to all commands.
259 while (!done && !sim_->has_bad_pc()) {
260 if (last_pc != sim_->get_pc()) {
261 disasm::NameConverter converter;
262 disasm::Disassembler dasm(converter);
263 // use a reasonably large buffer
264 v8::internal::EmbeddedVector<char, 256> buffer;
265 dasm.InstructionDecode(buffer,
266 reinterpret_cast<byte*>(sim_->get_pc()));
267 PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start());
268 last_pc = sim_->get_pc();
270 char* line = ReadLine("sim> ");
274 char* last_input = sim_->last_debugger_input();
275 if (strcmp(line, "\n") == 0 && last_input != NULL) {
278 // Ownership is transferred to sim_;
279 sim_->set_last_debugger_input(line);
281 // Use sscanf to parse the individual parts of the command line. At the
282 // moment no command expects more than two parameters.
283 int argc = SScanF(line,
284 "%" XSTR(COMMAND_SIZE) "s "
285 "%" XSTR(ARG_SIZE) "s "
286 "%" XSTR(ARG_SIZE) "s",
288 if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
289 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
290 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
291 // Execute the one instruction we broke at with breakpoints disabled.
292 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
293 // Leave the debugger shell.
295 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
296 if (argc == 2 || (argc == 3 && strcmp(arg2, "fp") == 0)) {
300 if (strcmp(arg1, "all") == 0) {
301 for (int i = 0; i < kNumRegisters; i++) {
302 value = GetRegisterValue(i);
303 PrintF("%3s: 0x%08x %10d", Registers::Name(i), value, value);
304 if ((argc == 3 && strcmp(arg2, "fp") == 0) &&
307 dvalue = GetRegisterPairDoubleValue(i);
308 PrintF(" (%f)\n", dvalue);
313 for (int i = 0; i < DwVfpRegister::NumRegisters(); i++) {
314 dvalue = GetVFPDoubleRegisterValue(i);
315 uint64_t as_words = bit_cast<uint64_t>(dvalue);
316 PrintF("%3s: %f 0x%08x %08x\n",
317 VFPRegisters::Name(i, true),
319 static_cast<uint32_t>(as_words >> 32),
320 static_cast<uint32_t>(as_words & 0xffffffff));
323 if (GetValue(arg1, &value)) {
324 PrintF("%s: 0x%08x %d \n", arg1, value, value);
325 } else if (GetVFPSingleValue(arg1, &svalue)) {
326 uint32_t as_word = bit_cast<uint32_t>(svalue);
327 PrintF("%s: %f 0x%08x\n", arg1, svalue, as_word);
328 } else if (GetVFPDoubleValue(arg1, &dvalue)) {
329 uint64_t as_words = bit_cast<uint64_t>(dvalue);
330 PrintF("%s: %f 0x%08x %08x\n",
333 static_cast<uint32_t>(as_words >> 32),
334 static_cast<uint32_t>(as_words & 0xffffffff));
336 PrintF("%s unrecognized\n", arg1);
340 PrintF("print <register>\n");
342 } else if ((strcmp(cmd, "po") == 0)
343 || (strcmp(cmd, "printobject") == 0)) {
347 if (GetValue(arg1, &value)) {
348 Object* obj = reinterpret_cast<Object*>(value);
349 os << arg1 << ": \n";
354 os << Brief(obj) << "\n";
357 os << arg1 << " unrecognized\n";
360 PrintF("printobject <value>\n");
362 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
367 if (strcmp(cmd, "stack") == 0) {
368 cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp));
371 if (!GetValue(arg1, &value)) {
372 PrintF("%s unrecognized\n", arg1);
375 cur = reinterpret_cast<int32_t*>(value);
380 if (argc == next_arg) {
383 if (!GetValue(argv[next_arg], &words)) {
390 PrintF(" 0x%08x: 0x%08x %10d",
391 reinterpret_cast<intptr_t>(cur), *cur, *cur);
392 HeapObject* obj = reinterpret_cast<HeapObject*>(*cur);
394 Heap* current_heap = v8::internal::Isolate::Current()->heap();
395 if (((value & 1) == 0) || current_heap->Contains(obj)) {
397 if ((value & 1) == 0) {
398 PrintF("smi %d", value / 2);
407 } else if (strcmp(cmd, "disasm") == 0 || strcmp(cmd, "di") == 0) {
408 disasm::NameConverter converter;
409 disasm::Disassembler dasm(converter);
410 // use a reasonably large buffer
411 v8::internal::EmbeddedVector<char, 256> buffer;
418 cur = reinterpret_cast<byte*>(sim_->get_pc());
419 end = cur + (10 * Instruction::kInstrSize);
420 } else if (argc == 2) {
421 int regnum = Registers::Number(arg1);
422 if (regnum != kNoRegister || strncmp(arg1, "0x", 2) == 0) {
423 // The argument is an address or a register name.
425 if (GetValue(arg1, &value)) {
426 cur = reinterpret_cast<byte*>(value);
427 // Disassemble 10 instructions at <arg1>.
428 end = cur + (10 * Instruction::kInstrSize);
431 // The argument is the number of instructions.
433 if (GetValue(arg1, &value)) {
434 cur = reinterpret_cast<byte*>(sim_->get_pc());
435 // Disassemble <arg1> instructions.
436 end = cur + (value * Instruction::kInstrSize);
442 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
443 cur = reinterpret_cast<byte*>(value1);
444 end = cur + (value2 * Instruction::kInstrSize);
450 cur += dasm.InstructionDecode(buffer, cur);
451 PrintF(" 0x%08x %s\n",
452 reinterpret_cast<intptr_t>(prev), buffer.start());
454 } else if (strcmp(cmd, "gdb") == 0) {
455 PrintF("relinquishing control to gdb\n");
456 v8::base::OS::DebugBreak();
457 PrintF("regaining control from gdb\n");
458 } else if (strcmp(cmd, "break") == 0) {
461 if (GetValue(arg1, &value)) {
462 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
463 PrintF("setting breakpoint failed\n");
466 PrintF("%s unrecognized\n", arg1);
469 PrintF("break <address>\n");
471 } else if (strcmp(cmd, "del") == 0) {
472 if (!DeleteBreakpoint(NULL)) {
473 PrintF("deleting breakpoint failed\n");
475 } else if (strcmp(cmd, "flags") == 0) {
476 PrintF("N flag: %d; ", sim_->n_flag_);
477 PrintF("Z flag: %d; ", sim_->z_flag_);
478 PrintF("C flag: %d; ", sim_->c_flag_);
479 PrintF("V flag: %d\n", sim_->v_flag_);
480 PrintF("INVALID OP flag: %d; ", sim_->inv_op_vfp_flag_);
481 PrintF("DIV BY ZERO flag: %d; ", sim_->div_zero_vfp_flag_);
482 PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_);
483 PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_);
484 PrintF("INEXACT flag: %d;\n", sim_->inexact_vfp_flag_);
485 } else if (strcmp(cmd, "stop") == 0) {
487 intptr_t stop_pc = sim_->get_pc() - 2 * Instruction::kInstrSize;
488 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc);
489 Instruction* msg_address =
490 reinterpret_cast<Instruction*>(stop_pc + Instruction::kInstrSize);
491 if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) {
492 // Remove the current stop.
493 if (sim_->isStopInstruction(stop_instr)) {
494 stop_instr->SetInstructionBits(kNopInstr);
495 msg_address->SetInstructionBits(kNopInstr);
497 PrintF("Not at debugger stop.\n");
499 } else if (argc == 3) {
500 // Print information about all/the specified breakpoint(s).
501 if (strcmp(arg1, "info") == 0) {
502 if (strcmp(arg2, "all") == 0) {
503 PrintF("Stop information:\n");
504 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
505 sim_->PrintStopInfo(i);
507 } else if (GetValue(arg2, &value)) {
508 sim_->PrintStopInfo(value);
510 PrintF("Unrecognized argument.\n");
512 } else if (strcmp(arg1, "enable") == 0) {
513 // Enable all/the specified breakpoint(s).
514 if (strcmp(arg2, "all") == 0) {
515 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
518 } else if (GetValue(arg2, &value)) {
519 sim_->EnableStop(value);
521 PrintF("Unrecognized argument.\n");
523 } else if (strcmp(arg1, "disable") == 0) {
524 // Disable all/the specified breakpoint(s).
525 if (strcmp(arg2, "all") == 0) {
526 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
527 sim_->DisableStop(i);
529 } else if (GetValue(arg2, &value)) {
530 sim_->DisableStop(value);
532 PrintF("Unrecognized argument.\n");
536 PrintF("Wrong usage. Use help command for more information.\n");
538 } else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) {
539 ::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim;
540 PrintF("Trace of executed instructions is %s\n",
541 ::v8::internal::FLAG_trace_sim ? "on" : "off");
542 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
544 PrintF(" continue execution (alias 'c')\n");
546 PrintF(" step one instruction (alias 'si')\n");
547 PrintF("print <register>\n");
548 PrintF(" print register content (alias 'p')\n");
549 PrintF(" use register name 'all' to print all registers\n");
550 PrintF(" add argument 'fp' to print register pair double values\n");
551 PrintF("printobject <register>\n");
552 PrintF(" print an object from a register (alias 'po')\n");
554 PrintF(" print flags\n");
555 PrintF("stack [<words>]\n");
556 PrintF(" dump stack content, default dump 10 words)\n");
557 PrintF("mem <address> [<words>]\n");
558 PrintF(" dump memory content, default dump 10 words)\n");
559 PrintF("disasm [<instructions>]\n");
560 PrintF("disasm [<address/register>]\n");
561 PrintF("disasm [[<address/register>] <instructions>]\n");
562 PrintF(" disassemble code, default is 10 instructions\n");
563 PrintF(" from pc (alias 'di')\n");
565 PrintF(" enter gdb\n");
566 PrintF("break <address>\n");
567 PrintF(" set a break point on the address\n");
569 PrintF(" delete the breakpoint\n");
570 PrintF("trace (alias 't')\n");
571 PrintF(" toogle the tracing of all executed statements\n");
572 PrintF("stop feature:\n");
573 PrintF(" Description:\n");
574 PrintF(" Stops are debug instructions inserted by\n");
575 PrintF(" the Assembler::stop() function.\n");
576 PrintF(" When hitting a stop, the Simulator will\n");
577 PrintF(" stop and and give control to the ArmDebugger.\n");
578 PrintF(" The first %d stop codes are watched:\n",
579 Simulator::kNumOfWatchedStops);
580 PrintF(" - They can be enabled / disabled: the Simulator\n");
581 PrintF(" will / won't stop when hitting them.\n");
582 PrintF(" - The Simulator keeps track of how many times they \n");
583 PrintF(" are met. (See the info command.) Going over a\n");
584 PrintF(" disabled stop still increases its counter. \n");
585 PrintF(" Commands:\n");
586 PrintF(" stop info all/<code> : print infos about number <code>\n");
587 PrintF(" or all stop(s).\n");
588 PrintF(" stop enable/disable all/<code> : enables / disables\n");
589 PrintF(" all or number <code> stop(s)\n");
590 PrintF(" stop unstop\n");
591 PrintF(" ignore the stop instruction at the current location\n");
592 PrintF(" from now on\n");
594 PrintF("Unknown command: %s\n", cmd);
599 // Add all the breakpoints back to stop execution and enter the debugger
611 static bool ICacheMatch(void* one, void* two) {
612 DCHECK((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
613 DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
618 static uint32_t ICacheHash(void* key) {
619 return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
623 static bool AllOnOnePage(uintptr_t start, int size) {
624 intptr_t start_page = (start & ~CachePage::kPageMask);
625 intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
626 return start_page == end_page;
630 void Simulator::set_last_debugger_input(char* input) {
631 DeleteArray(last_debugger_input_);
632 last_debugger_input_ = input;
636 void Simulator::FlushICache(v8::internal::HashMap* i_cache,
639 intptr_t start = reinterpret_cast<intptr_t>(start_addr);
640 int intra_line = (start & CachePage::kLineMask);
643 size = ((size - 1) | CachePage::kLineMask) + 1;
644 int offset = (start & CachePage::kPageMask);
645 while (!AllOnOnePage(start, size - 1)) {
646 int bytes_to_flush = CachePage::kPageSize - offset;
647 FlushOnePage(i_cache, start, bytes_to_flush);
648 start += bytes_to_flush;
649 size -= bytes_to_flush;
650 DCHECK_EQ(0, start & CachePage::kPageMask);
654 FlushOnePage(i_cache, start, size);
659 CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
660 v8::internal::HashMap::Entry* entry = i_cache->Lookup(page,
663 if (entry->value == NULL) {
664 CachePage* new_page = new CachePage();
665 entry->value = new_page;
667 return reinterpret_cast<CachePage*>(entry->value);
671 // Flush from start up to and not including start + size.
672 void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
675 DCHECK(size <= CachePage::kPageSize);
676 DCHECK(AllOnOnePage(start, size - 1));
677 DCHECK((start & CachePage::kLineMask) == 0);
678 DCHECK((size & CachePage::kLineMask) == 0);
679 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
680 int offset = (start & CachePage::kPageMask);
681 CachePage* cache_page = GetCachePage(i_cache, page);
682 char* valid_bytemap = cache_page->ValidityByte(offset);
683 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
687 void Simulator::CheckICache(v8::internal::HashMap* i_cache,
688 Instruction* instr) {
689 intptr_t address = reinterpret_cast<intptr_t>(instr);
690 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
691 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
692 int offset = (address & CachePage::kPageMask);
693 CachePage* cache_page = GetCachePage(i_cache, page);
694 char* cache_valid_byte = cache_page->ValidityByte(offset);
695 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
696 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
698 // Check that the data in memory matches the contents of the I-cache.
700 memcmp(reinterpret_cast<void*>(instr),
701 cache_page->CachedData(offset), Instruction::kInstrSize));
703 // Cache miss. Load memory into the cache.
704 memcpy(cached_line, line, CachePage::kLineLength);
705 *cache_valid_byte = CachePage::LINE_VALID;
710 void Simulator::Initialize(Isolate* isolate) {
711 if (isolate->simulator_initialized()) return;
712 isolate->set_simulator_initialized(true);
713 ::v8::internal::ExternalReference::set_redirector(isolate,
714 &RedirectExternalReference);
718 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) {
719 i_cache_ = isolate_->simulator_i_cache();
720 if (i_cache_ == NULL) {
721 i_cache_ = new v8::internal::HashMap(&ICacheMatch);
722 isolate_->set_simulator_i_cache(i_cache_);
725 // Set up simulator support first. Some of this information is needed to
726 // setup the architecture state.
727 size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack
728 stack_ = reinterpret_cast<char*>(malloc(stack_size));
729 pc_modified_ = false;
734 // Set up architecture state.
735 // All registers are initialized to zero to start with.
736 for (int i = 0; i < num_registers; i++) {
744 // Initializing VFP registers.
745 // All registers are initialized to zero to start with
746 // even though s_registers_ & d_registers_ share the same
747 // physical registers in the target.
748 for (int i = 0; i < num_d_registers * 2; i++) {
749 vfp_registers_[i] = 0;
751 n_flag_FPSCR_ = false;
752 z_flag_FPSCR_ = false;
753 c_flag_FPSCR_ = false;
754 v_flag_FPSCR_ = false;
755 FPSCR_rounding_mode_ = RN;
756 FPSCR_default_NaN_mode_ = false;
758 inv_op_vfp_flag_ = false;
759 div_zero_vfp_flag_ = false;
760 overflow_vfp_flag_ = false;
761 underflow_vfp_flag_ = false;
762 inexact_vfp_flag_ = false;
764 // The sp is initialized to point to the bottom (high address) of the
765 // allocated stack area. To be safe in potential stack underflows we leave
766 // some buffer below.
767 registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size - 64;
768 // The lr and pc are initialized to a known bad value that will cause an
769 // access violation if the simulator ever tries to execute it.
770 registers_[pc] = bad_lr;
771 registers_[lr] = bad_lr;
772 InitializeCoverage();
774 last_debugger_input_ = NULL;
778 Simulator::~Simulator() {
782 // When the generated code calls an external reference we need to catch that in
783 // the simulator. The external reference will be a function compiled for the
784 // host architecture. We need to call that function instead of trying to
785 // execute it with the simulator. We do that by redirecting the external
786 // reference to a svc (Supervisor Call) instruction that is handled by
787 // the simulator. We write the original destination of the jump just at a known
788 // offset from the svc instruction so the simulator knows what to call.
791 Redirection(void* external_function, ExternalReference::Type type)
792 : external_function_(external_function),
793 swi_instruction_(al | (0xf*B24) | kCallRtRedirected),
796 Isolate* isolate = Isolate::Current();
797 next_ = isolate->simulator_redirection();
798 Simulator::current(isolate)->
799 FlushICache(isolate->simulator_i_cache(),
800 reinterpret_cast<void*>(&swi_instruction_),
801 Instruction::kInstrSize);
802 isolate->set_simulator_redirection(this);
805 void* address_of_swi_instruction() {
806 return reinterpret_cast<void*>(&swi_instruction_);
809 void* external_function() { return external_function_; }
810 ExternalReference::Type type() { return type_; }
812 static Redirection* Get(void* external_function,
813 ExternalReference::Type type) {
814 Isolate* isolate = Isolate::Current();
815 Redirection* current = isolate->simulator_redirection();
816 for (; current != NULL; current = current->next_) {
817 if (current->external_function_ == external_function) {
818 DCHECK_EQ(current->type(), type);
822 return new Redirection(external_function, type);
825 static Redirection* FromSwiInstruction(Instruction* swi_instruction) {
826 char* addr_of_swi = reinterpret_cast<char*>(swi_instruction);
827 char* addr_of_redirection =
828 addr_of_swi - OFFSET_OF(Redirection, swi_instruction_);
829 return reinterpret_cast<Redirection*>(addr_of_redirection);
832 static void* ReverseRedirection(int32_t reg) {
833 Redirection* redirection = FromSwiInstruction(
834 reinterpret_cast<Instruction*>(reinterpret_cast<void*>(reg)));
835 return redirection->external_function();
839 void* external_function_;
840 uint32_t swi_instruction_;
841 ExternalReference::Type type_;
846 void* Simulator::RedirectExternalReference(void* external_function,
847 ExternalReference::Type type) {
848 Redirection* redirection = Redirection::Get(external_function, type);
849 return redirection->address_of_swi_instruction();
853 // Get the active Simulator for the current thread.
854 Simulator* Simulator::current(Isolate* isolate) {
855 v8::internal::Isolate::PerIsolateThreadData* isolate_data =
856 isolate->FindOrAllocatePerThreadDataForThisThread();
857 DCHECK(isolate_data != NULL);
859 Simulator* sim = isolate_data->simulator();
861 // TODO(146): delete the simulator object when a thread/isolate goes away.
862 sim = new Simulator(isolate);
863 isolate_data->set_simulator(sim);
869 // Sets the register in the architecture state. It will also deal with updating
870 // Simulator internal state for special registers such as PC.
871 void Simulator::set_register(int reg, int32_t value) {
872 DCHECK((reg >= 0) && (reg < num_registers));
876 registers_[reg] = value;
880 // Get the register from the architecture state. This function does handle
881 // the special case of accessing the PC register.
882 int32_t Simulator::get_register(int reg) const {
883 DCHECK((reg >= 0) && (reg < num_registers));
884 // Stupid code added to avoid bug in GCC.
885 // See: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43949
886 if (reg >= num_registers) return 0;
888 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
892 double Simulator::get_double_from_register_pair(int reg) {
893 DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
896 // Read the bits from the unsigned integer register_[] array
897 // into the double precision floating point value and return it.
898 char buffer[2 * sizeof(vfp_registers_[0])];
899 memcpy(buffer, ®isters_[reg], 2 * sizeof(registers_[0]));
900 memcpy(&dm_val, buffer, 2 * sizeof(registers_[0]));
905 void Simulator::set_register_pair_from_double(int reg, double* value) {
906 DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
907 memcpy(registers_ + reg, value, sizeof(*value));
911 void Simulator::set_dw_register(int dreg, const int* dbl) {
912 DCHECK((dreg >= 0) && (dreg < num_d_registers));
913 registers_[dreg] = dbl[0];
914 registers_[dreg + 1] = dbl[1];
918 void Simulator::get_d_register(int dreg, uint64_t* value) {
919 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
920 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
924 void Simulator::set_d_register(int dreg, const uint64_t* value) {
925 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
926 memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value));
930 void Simulator::get_d_register(int dreg, uint32_t* value) {
931 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
932 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value) * 2);
936 void Simulator::set_d_register(int dreg, const uint32_t* value) {
937 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
938 memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value) * 2);
942 void Simulator::get_q_register(int qreg, uint64_t* value) {
943 DCHECK((qreg >= 0) && (qreg < num_q_registers));
944 memcpy(value, vfp_registers_ + qreg * 4, sizeof(*value) * 2);
948 void Simulator::set_q_register(int qreg, const uint64_t* value) {
949 DCHECK((qreg >= 0) && (qreg < num_q_registers));
950 memcpy(vfp_registers_ + qreg * 4, value, sizeof(*value) * 2);
954 void Simulator::get_q_register(int qreg, uint32_t* value) {
955 DCHECK((qreg >= 0) && (qreg < num_q_registers));
956 memcpy(value, vfp_registers_ + qreg * 4, sizeof(*value) * 4);
960 void Simulator::set_q_register(int qreg, const uint32_t* value) {
961 DCHECK((qreg >= 0) && (qreg < num_q_registers));
962 memcpy(vfp_registers_ + qreg * 4, value, sizeof(*value) * 4);
966 // Raw access to the PC register.
967 void Simulator::set_pc(int32_t value) {
969 registers_[pc] = value;
973 bool Simulator::has_bad_pc() const {
974 return ((registers_[pc] == bad_lr) || (registers_[pc] == end_sim_pc));
978 // Raw access to the PC register without the special adjustment when reading.
979 int32_t Simulator::get_pc() const {
980 return registers_[pc];
984 // Getting from and setting into VFP registers.
985 void Simulator::set_s_register(int sreg, unsigned int value) {
986 DCHECK((sreg >= 0) && (sreg < num_s_registers));
987 vfp_registers_[sreg] = value;
991 unsigned int Simulator::get_s_register(int sreg) const {
992 DCHECK((sreg >= 0) && (sreg < num_s_registers));
993 return vfp_registers_[sreg];
997 template<class InputType, int register_size>
998 void Simulator::SetVFPRegister(int reg_index, const InputType& value) {
999 DCHECK(reg_index >= 0);
1000 if (register_size == 1) DCHECK(reg_index < num_s_registers);
1001 if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
1003 char buffer[register_size * sizeof(vfp_registers_[0])];
1004 memcpy(buffer, &value, register_size * sizeof(vfp_registers_[0]));
1005 memcpy(&vfp_registers_[reg_index * register_size], buffer,
1006 register_size * sizeof(vfp_registers_[0]));
1010 template<class ReturnType, int register_size>
1011 ReturnType Simulator::GetFromVFPRegister(int reg_index) {
1012 DCHECK(reg_index >= 0);
1013 if (register_size == 1) DCHECK(reg_index < num_s_registers);
1014 if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
1016 ReturnType value = 0;
1017 char buffer[register_size * sizeof(vfp_registers_[0])];
1018 memcpy(buffer, &vfp_registers_[register_size * reg_index],
1019 register_size * sizeof(vfp_registers_[0]));
1020 memcpy(&value, buffer, register_size * sizeof(vfp_registers_[0]));
1025 // Runtime FP routines take:
1026 // - two double arguments
1027 // - one double argument and zero or one integer arguments.
1028 // All are consructed here from r0-r3 or d0, d1 and r0.
1029 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
1030 if (use_eabi_hardfloat()) {
1031 *x = get_double_from_d_register(0);
1032 *y = get_double_from_d_register(1);
1033 *z = get_register(0);
1035 // Registers 0 and 1 -> x.
1036 *x = get_double_from_register_pair(0);
1037 // Register 2 and 3 -> y.
1038 *y = get_double_from_register_pair(2);
1040 *z = get_register(2);
1045 // The return value is either in r0/r1 or d0.
1046 void Simulator::SetFpResult(const double& result) {
1047 if (use_eabi_hardfloat()) {
1048 char buffer[2 * sizeof(vfp_registers_[0])];
1049 memcpy(buffer, &result, sizeof(buffer));
1050 // Copy result to d0.
1051 memcpy(vfp_registers_, buffer, sizeof(buffer));
1053 char buffer[2 * sizeof(registers_[0])];
1054 memcpy(buffer, &result, sizeof(buffer));
1055 // Copy result to r0 and r1.
1056 memcpy(registers_, buffer, sizeof(buffer));
1061 void Simulator::TrashCallerSaveRegisters() {
1062 // We don't trash the registers with the return value.
1063 registers_[2] = 0x50Bad4U;
1064 registers_[3] = 0x50Bad4U;
1065 registers_[12] = 0x50Bad4U;
1069 // Some Operating Systems allow unaligned access on ARMv7 targets. We
1070 // assume that unaligned accesses are not allowed unless the v8 build system
1071 // defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero.
1072 // The following statements below describes the behavior of the ARM CPUs
1073 // that don't support unaligned access.
1074 // Some ARM platforms raise an interrupt on detecting unaligned access.
1075 // On others it does a funky rotation thing. For now we
1076 // simply disallow unaligned reads. Note that simulator runs have the runtime
1077 // system running directly on the host system and only generated code is
1078 // executed in the simulator. Since the host is typically IA32 we will not
1079 // get the correct ARM-like behaviour on unaligned accesses for those ARM
1080 // targets that don't support unaligned loads and stores.
1083 int Simulator::ReadW(int32_t addr, Instruction* instr) {
1084 if (FLAG_enable_unaligned_accesses || (addr & 3) == 0) {
1085 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
1088 PrintF("Unaligned read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
1090 reinterpret_cast<intptr_t>(instr));
1097 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
1098 if (FLAG_enable_unaligned_accesses || (addr & 3) == 0) {
1099 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
1102 PrintF("Unaligned write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
1104 reinterpret_cast<intptr_t>(instr));
1110 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
1111 if (FLAG_enable_unaligned_accesses || (addr & 1) == 0) {
1112 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
1115 PrintF("Unaligned unsigned halfword read at 0x%08x, pc=0x%08"
1118 reinterpret_cast<intptr_t>(instr));
1125 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
1126 if (FLAG_enable_unaligned_accesses || (addr & 1) == 0) {
1127 int16_t* ptr = reinterpret_cast<int16_t*>(addr);
1130 PrintF("Unaligned signed halfword read at 0x%08x\n", addr);
1137 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
1138 if (FLAG_enable_unaligned_accesses || (addr & 1) == 0) {
1139 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
1142 PrintF("Unaligned unsigned halfword write at 0x%08x, pc=0x%08"
1145 reinterpret_cast<intptr_t>(instr));
1151 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
1152 if (FLAG_enable_unaligned_accesses || (addr & 1) == 0) {
1153 int16_t* ptr = reinterpret_cast<int16_t*>(addr);
1156 PrintF("Unaligned halfword write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
1158 reinterpret_cast<intptr_t>(instr));
1164 uint8_t Simulator::ReadBU(int32_t addr) {
1165 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
1170 int8_t Simulator::ReadB(int32_t addr) {
1171 int8_t* ptr = reinterpret_cast<int8_t*>(addr);
1176 void Simulator::WriteB(int32_t addr, uint8_t value) {
1177 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
1182 void Simulator::WriteB(int32_t addr, int8_t value) {
1183 int8_t* ptr = reinterpret_cast<int8_t*>(addr);
1188 int32_t* Simulator::ReadDW(int32_t addr) {
1189 if (FLAG_enable_unaligned_accesses || (addr & 3) == 0) {
1190 int32_t* ptr = reinterpret_cast<int32_t*>(addr);
1193 PrintF("Unaligned read at 0x%08x\n", addr);
1200 void Simulator::WriteDW(int32_t addr, int32_t value1, int32_t value2) {
1201 if (FLAG_enable_unaligned_accesses || (addr & 3) == 0) {
1202 int32_t* ptr = reinterpret_cast<int32_t*>(addr);
1206 PrintF("Unaligned write at 0x%08x\n", addr);
1212 // Returns the limit of the stack area to enable checking for stack overflows.
1213 uintptr_t Simulator::StackLimit() const {
1214 // Leave a safety margin of 1024 bytes to prevent overrunning the stack when
1216 return reinterpret_cast<uintptr_t>(stack_) + 1024;
1220 // Unsupported instructions use Format to print an error and stop execution.
1221 void Simulator::Format(Instruction* instr, const char* format) {
1222 PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
1223 reinterpret_cast<intptr_t>(instr), format);
1228 // Checks if the current instruction should be executed based on its
1230 bool Simulator::ConditionallyExecute(Instruction* instr) {
1231 switch (instr->ConditionField()) {
1232 case eq: return z_flag_;
1233 case ne: return !z_flag_;
1234 case cs: return c_flag_;
1235 case cc: return !c_flag_;
1236 case mi: return n_flag_;
1237 case pl: return !n_flag_;
1238 case vs: return v_flag_;
1239 case vc: return !v_flag_;
1240 case hi: return c_flag_ && !z_flag_;
1241 case ls: return !c_flag_ || z_flag_;
1242 case ge: return n_flag_ == v_flag_;
1243 case lt: return n_flag_ != v_flag_;
1244 case gt: return !z_flag_ && (n_flag_ == v_flag_);
1245 case le: return z_flag_ || (n_flag_ != v_flag_);
1246 case al: return true;
1247 default: UNREACHABLE();
1253 // Calculate and set the Negative and Zero flags.
1254 void Simulator::SetNZFlags(int32_t val) {
1255 n_flag_ = (val < 0);
1256 z_flag_ = (val == 0);
1260 // Set the Carry flag.
1261 void Simulator::SetCFlag(bool val) {
1266 // Set the oVerflow flag.
1267 void Simulator::SetVFlag(bool val) {
1272 // Calculate C flag value for additions.
1273 bool Simulator::CarryFrom(int32_t left, int32_t right, int32_t carry) {
1274 uint32_t uleft = static_cast<uint32_t>(left);
1275 uint32_t uright = static_cast<uint32_t>(right);
1276 uint32_t urest = 0xffffffffU - uleft;
1278 return (uright > urest) ||
1279 (carry && (((uright + 1) > urest) || (uright > (urest - 1))));
1283 // Calculate C flag value for subtractions.
1284 bool Simulator::BorrowFrom(int32_t left, int32_t right) {
1285 uint32_t uleft = static_cast<uint32_t>(left);
1286 uint32_t uright = static_cast<uint32_t>(right);
1288 return (uright > uleft);
1292 // Calculate V flag value for additions and subtractions.
1293 bool Simulator::OverflowFrom(int32_t alu_out,
1294 int32_t left, int32_t right, bool addition) {
1297 // operands have the same sign
1298 overflow = ((left >= 0 && right >= 0) || (left < 0 && right < 0))
1299 // and operands and result have different sign
1300 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
1302 // operands have different signs
1303 overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
1304 // and first operand and result have different signs
1305 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
1311 // Support for VFP comparisons.
1312 void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
1313 if (std::isnan(val1) || std::isnan(val2)) {
1314 n_flag_FPSCR_ = false;
1315 z_flag_FPSCR_ = false;
1316 c_flag_FPSCR_ = true;
1317 v_flag_FPSCR_ = true;
1318 // All non-NaN cases.
1319 } else if (val1 == val2) {
1320 n_flag_FPSCR_ = false;
1321 z_flag_FPSCR_ = true;
1322 c_flag_FPSCR_ = true;
1323 v_flag_FPSCR_ = false;
1324 } else if (val1 < val2) {
1325 n_flag_FPSCR_ = true;
1326 z_flag_FPSCR_ = false;
1327 c_flag_FPSCR_ = false;
1328 v_flag_FPSCR_ = false;
1330 // Case when (val1 > val2).
1331 n_flag_FPSCR_ = false;
1332 z_flag_FPSCR_ = false;
1333 c_flag_FPSCR_ = true;
1334 v_flag_FPSCR_ = false;
1339 void Simulator::Copy_FPSCR_to_APSR() {
1340 n_flag_ = n_flag_FPSCR_;
1341 z_flag_ = z_flag_FPSCR_;
1342 c_flag_ = c_flag_FPSCR_;
1343 v_flag_ = v_flag_FPSCR_;
1347 // Addressing Mode 1 - Data-processing operands:
1348 // Get the value based on the shifter_operand with register.
1349 int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
1350 ShiftOp shift = instr->ShiftField();
1351 int shift_amount = instr->ShiftAmountValue();
1352 int32_t result = get_register(instr->RmValue());
1353 if (instr->Bit(4) == 0) {
1355 if ((shift == ROR) && (shift_amount == 0)) {
1358 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
1363 if (shift_amount == 0) {
1365 result = 0xffffffff;
1372 result >>= (shift_amount - 1);
1373 *carry_out = (result & 1) == 1;
1380 if (shift_amount == 0) {
1381 *carry_out = c_flag_;
1383 result <<= (shift_amount - 1);
1384 *carry_out = (result < 0);
1391 if (shift_amount == 0) {
1393 *carry_out = c_flag_;
1395 uint32_t uresult = static_cast<uint32_t>(result);
1396 uresult >>= (shift_amount - 1);
1397 *carry_out = (uresult & 1) == 1;
1399 result = static_cast<int32_t>(uresult);
1405 if (shift_amount == 0) {
1406 *carry_out = c_flag_;
1408 uint32_t left = static_cast<uint32_t>(result) >> shift_amount;
1409 uint32_t right = static_cast<uint32_t>(result) << (32 - shift_amount);
1410 result = right | left;
1411 *carry_out = (static_cast<uint32_t>(result) >> 31) != 0;
1423 int rs = instr->RsValue();
1424 shift_amount = get_register(rs) &0xff;
1427 if (shift_amount == 0) {
1428 *carry_out = c_flag_;
1429 } else if (shift_amount < 32) {
1430 result >>= (shift_amount - 1);
1431 *carry_out = (result & 1) == 1;
1434 DCHECK(shift_amount >= 32);
1437 result = 0xffffffff;
1447 if (shift_amount == 0) {
1448 *carry_out = c_flag_;
1449 } else if (shift_amount < 32) {
1450 result <<= (shift_amount - 1);
1451 *carry_out = (result < 0);
1453 } else if (shift_amount == 32) {
1454 *carry_out = (result & 1) == 1;
1457 DCHECK(shift_amount > 32);
1465 if (shift_amount == 0) {
1466 *carry_out = c_flag_;
1467 } else if (shift_amount < 32) {
1468 uint32_t uresult = static_cast<uint32_t>(result);
1469 uresult >>= (shift_amount - 1);
1470 *carry_out = (uresult & 1) == 1;
1472 result = static_cast<int32_t>(uresult);
1473 } else if (shift_amount == 32) {
1474 *carry_out = (result < 0);
1484 if (shift_amount == 0) {
1485 *carry_out = c_flag_;
1487 uint32_t left = static_cast<uint32_t>(result) >> shift_amount;
1488 uint32_t right = static_cast<uint32_t>(result) << (32 - shift_amount);
1489 result = right | left;
1490 *carry_out = (static_cast<uint32_t>(result) >> 31) != 0;
1505 // Addressing Mode 1 - Data-processing operands:
1506 // Get the value based on the shifter_operand with immediate.
1507 int32_t Simulator::GetImm(Instruction* instr, bool* carry_out) {
1508 int rotate = instr->RotateValue() * 2;
1509 int immed8 = instr->Immed8Value();
1510 int imm = base::bits::RotateRight32(immed8, rotate);
1511 *carry_out = (rotate == 0) ? c_flag_ : (imm < 0);
1516 static int count_bits(int bit_vector) {
1518 while (bit_vector != 0) {
1519 if ((bit_vector & 1) != 0) {
1528 int32_t Simulator::ProcessPU(Instruction* instr,
1531 intptr_t* start_address,
1532 intptr_t* end_address) {
1533 int rn = instr->RnValue();
1534 int32_t rn_val = get_register(rn);
1535 switch (instr->PUField()) {
1541 *start_address = rn_val;
1542 *end_address = rn_val + (num_regs * reg_size) - reg_size;
1543 rn_val = rn_val + (num_regs * reg_size);
1547 *start_address = rn_val - (num_regs * reg_size);
1548 *end_address = rn_val - reg_size;
1549 rn_val = *start_address;
1553 *start_address = rn_val + reg_size;
1554 *end_address = rn_val + (num_regs * reg_size);
1555 rn_val = *end_address;
1567 // Addressing Mode 4 - Load and Store Multiple
1568 void Simulator::HandleRList(Instruction* instr, bool load) {
1569 int rlist = instr->RlistValue();
1570 int num_regs = count_bits(rlist);
1572 intptr_t start_address = 0;
1573 intptr_t end_address = 0;
1575 ProcessPU(instr, num_regs, kPointerSize, &start_address, &end_address);
1577 intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
1578 // Catch null pointers a little earlier.
1579 DCHECK(start_address > 8191 || start_address < 0);
1581 while (rlist != 0) {
1582 if ((rlist & 1) != 0) {
1584 set_register(reg, *address);
1586 *address = get_register(reg);
1593 DCHECK(end_address == ((intptr_t)address) - 4);
1594 if (instr->HasW()) {
1595 set_register(instr->RnValue(), rn_val);
1600 // Addressing Mode 6 - Load and Store Multiple Coprocessor registers.
1601 void Simulator::HandleVList(Instruction* instr) {
1602 VFPRegPrecision precision =
1603 (instr->SzValue() == 0) ? kSinglePrecision : kDoublePrecision;
1604 int operand_size = (precision == kSinglePrecision) ? 4 : 8;
1606 bool load = (instr->VLValue() == 0x1);
1610 vd = instr->VFPDRegValue(precision);
1611 if (precision == kSinglePrecision) {
1612 num_regs = instr->Immed8Value();
1614 num_regs = instr->Immed8Value() / 2;
1617 intptr_t start_address = 0;
1618 intptr_t end_address = 0;
1620 ProcessPU(instr, num_regs, operand_size, &start_address, &end_address);
1622 intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
1623 for (int reg = vd; reg < vd + num_regs; reg++) {
1624 if (precision == kSinglePrecision) {
1626 set_s_register_from_sinteger(
1627 reg, ReadW(reinterpret_cast<int32_t>(address), instr));
1629 WriteW(reinterpret_cast<int32_t>(address),
1630 get_sinteger_from_s_register(reg), instr);
1636 ReadW(reinterpret_cast<int32_t>(address), instr),
1637 ReadW(reinterpret_cast<int32_t>(address + 1), instr)
1639 set_d_register(reg, reinterpret_cast<uint32_t*>(data));
1642 get_d_register(reg, data);
1643 WriteW(reinterpret_cast<int32_t>(address), data[0], instr);
1644 WriteW(reinterpret_cast<int32_t>(address + 1), data[1], instr);
1649 DCHECK(reinterpret_cast<intptr_t>(address) - operand_size == end_address);
1650 if (instr->HasW()) {
1651 set_register(instr->RnValue(), rn_val);
1656 // Calls into the V8 runtime are based on this very simple interface.
1657 // Note: To be able to return two values from some calls the code in runtime.cc
1658 // uses the ObjectPair which is essentially two 32-bit values stuffed into a
1659 // 64-bit value. With the code below we assume that all runtime calls return
1660 // 64 bits of result. If they don't, the r1 result register contains a bogus
1661 // value, which is fine because it is caller-saved.
1662 typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0,
1669 // These prototypes handle the four types of FP calls.
1670 typedef int64_t (*SimulatorRuntimeCompareCall)(double darg0, double darg1);
1671 typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1);
1672 typedef double (*SimulatorRuntimeFPCall)(double darg0);
1673 typedef double (*SimulatorRuntimeFPIntCall)(double darg0, int32_t arg0);
1675 // This signature supports direct call in to API function native callback
1676 // (refer to InvocationCallback in v8.h).
1677 typedef void (*SimulatorRuntimeDirectApiCall)(int32_t arg0);
1678 typedef void (*SimulatorRuntimeProfilingApiCall)(int32_t arg0, void* arg1);
1680 // This signature supports direct call to accessor getter callback.
1681 typedef void (*SimulatorRuntimeDirectGetterCall)(int32_t arg0, int32_t arg1);
1682 typedef void (*SimulatorRuntimeProfilingGetterCall)(
1683 int32_t arg0, int32_t arg1, void* arg2);
1685 // Software interrupt instructions are used by the simulator to call into the
1686 // C-based V8 runtime.
1687 void Simulator::SoftwareInterrupt(Instruction* instr) {
1688 int svc = instr->SvcValue();
1690 case kCallRtRedirected: {
1691 // Check if stack is aligned. Error if not aligned is reported below to
1692 // include information on the function called.
1693 bool stack_aligned =
1695 & (::v8::internal::FLAG_sim_stack_alignment - 1)) == 0;
1696 Redirection* redirection = Redirection::FromSwiInstruction(instr);
1697 int32_t arg0 = get_register(r0);
1698 int32_t arg1 = get_register(r1);
1699 int32_t arg2 = get_register(r2);
1700 int32_t arg3 = get_register(r3);
1701 int32_t* stack_pointer = reinterpret_cast<int32_t*>(get_register(sp));
1702 int32_t arg4 = stack_pointer[0];
1703 int32_t arg5 = stack_pointer[1];
1705 (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) ||
1706 (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) ||
1707 (redirection->type() == ExternalReference::BUILTIN_FP_CALL) ||
1708 (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL);
1709 // This is dodgy but it works because the C entry stubs are never moved.
1710 // See comment in codegen-arm.cc and bug 1242173.
1711 int32_t saved_lr = get_register(lr);
1713 reinterpret_cast<intptr_t>(redirection->external_function());
1715 double dval0, dval1; // one or two double parameters
1716 int32_t ival; // zero or one integer parameters
1717 int64_t iresult = 0; // integer return value
1718 double dresult = 0; // double return value
1719 GetFpArgs(&dval0, &dval1, &ival);
1720 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1721 SimulatorRuntimeCall generic_target =
1722 reinterpret_cast<SimulatorRuntimeCall>(external);
1723 switch (redirection->type()) {
1724 case ExternalReference::BUILTIN_FP_FP_CALL:
1725 case ExternalReference::BUILTIN_COMPARE_CALL:
1726 PrintF("Call to host function at %p with args %f, %f",
1727 FUNCTION_ADDR(generic_target), dval0, dval1);
1729 case ExternalReference::BUILTIN_FP_CALL:
1730 PrintF("Call to host function at %p with arg %f",
1731 FUNCTION_ADDR(generic_target), dval0);
1733 case ExternalReference::BUILTIN_FP_INT_CALL:
1734 PrintF("Call to host function at %p with args %f, %d",
1735 FUNCTION_ADDR(generic_target), dval0, ival);
1741 if (!stack_aligned) {
1742 PrintF(" with unaligned stack %08x\n", get_register(sp));
1746 CHECK(stack_aligned);
1747 switch (redirection->type()) {
1748 case ExternalReference::BUILTIN_COMPARE_CALL: {
1749 SimulatorRuntimeCompareCall target =
1750 reinterpret_cast<SimulatorRuntimeCompareCall>(external);
1751 iresult = target(dval0, dval1);
1752 set_register(r0, static_cast<int32_t>(iresult));
1753 set_register(r1, static_cast<int32_t>(iresult >> 32));
1756 case ExternalReference::BUILTIN_FP_FP_CALL: {
1757 SimulatorRuntimeFPFPCall target =
1758 reinterpret_cast<SimulatorRuntimeFPFPCall>(external);
1759 dresult = target(dval0, dval1);
1760 SetFpResult(dresult);
1763 case ExternalReference::BUILTIN_FP_CALL: {
1764 SimulatorRuntimeFPCall target =
1765 reinterpret_cast<SimulatorRuntimeFPCall>(external);
1766 dresult = target(dval0);
1767 SetFpResult(dresult);
1770 case ExternalReference::BUILTIN_FP_INT_CALL: {
1771 SimulatorRuntimeFPIntCall target =
1772 reinterpret_cast<SimulatorRuntimeFPIntCall>(external);
1773 dresult = target(dval0, ival);
1774 SetFpResult(dresult);
1781 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1782 switch (redirection->type()) {
1783 case ExternalReference::BUILTIN_COMPARE_CALL:
1784 PrintF("Returned %08x\n", static_cast<int32_t>(iresult));
1786 case ExternalReference::BUILTIN_FP_FP_CALL:
1787 case ExternalReference::BUILTIN_FP_CALL:
1788 case ExternalReference::BUILTIN_FP_INT_CALL:
1789 PrintF("Returned %f\n", dresult);
1796 } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
1797 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1798 PrintF("Call to host function at %p args %08x",
1799 reinterpret_cast<void*>(external), arg0);
1800 if (!stack_aligned) {
1801 PrintF(" with unaligned stack %08x\n", get_register(sp));
1805 CHECK(stack_aligned);
1806 SimulatorRuntimeDirectApiCall target =
1807 reinterpret_cast<SimulatorRuntimeDirectApiCall>(external);
1810 redirection->type() == ExternalReference::PROFILING_API_CALL) {
1811 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1812 PrintF("Call to host function at %p args %08x %08x",
1813 reinterpret_cast<void*>(external), arg0, arg1);
1814 if (!stack_aligned) {
1815 PrintF(" with unaligned stack %08x\n", get_register(sp));
1819 CHECK(stack_aligned);
1820 SimulatorRuntimeProfilingApiCall target =
1821 reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external);
1822 target(arg0, Redirection::ReverseRedirection(arg1));
1824 redirection->type() == ExternalReference::DIRECT_GETTER_CALL) {
1825 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1826 PrintF("Call to host function at %p args %08x %08x",
1827 reinterpret_cast<void*>(external), arg0, arg1);
1828 if (!stack_aligned) {
1829 PrintF(" with unaligned stack %08x\n", get_register(sp));
1833 CHECK(stack_aligned);
1834 SimulatorRuntimeDirectGetterCall target =
1835 reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external);
1838 redirection->type() == ExternalReference::PROFILING_GETTER_CALL) {
1839 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1840 PrintF("Call to host function at %p args %08x %08x %08x",
1841 reinterpret_cast<void*>(external), arg0, arg1, arg2);
1842 if (!stack_aligned) {
1843 PrintF(" with unaligned stack %08x\n", get_register(sp));
1847 CHECK(stack_aligned);
1848 SimulatorRuntimeProfilingGetterCall target =
1849 reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(
1851 target(arg0, arg1, Redirection::ReverseRedirection(arg2));
1854 DCHECK(redirection->type() == ExternalReference::BUILTIN_CALL);
1855 SimulatorRuntimeCall target =
1856 reinterpret_cast<SimulatorRuntimeCall>(external);
1857 if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
1859 "Call to host function at %p "
1860 "args %08x, %08x, %08x, %08x, %08x, %08x",
1861 FUNCTION_ADDR(target),
1868 if (!stack_aligned) {
1869 PrintF(" with unaligned stack %08x\n", get_register(sp));
1873 CHECK(stack_aligned);
1874 int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5);
1875 int32_t lo_res = static_cast<int32_t>(result);
1876 int32_t hi_res = static_cast<int32_t>(result >> 32);
1877 if (::v8::internal::FLAG_trace_sim) {
1878 PrintF("Returned %08x\n", lo_res);
1880 set_register(r0, lo_res);
1881 set_register(r1, hi_res);
1883 set_register(lr, saved_lr);
1884 set_pc(get_register(lr));
1888 ArmDebugger dbg(this);
1892 // stop uses all codes greater than 1 << 23.
1894 if (svc >= (1 << 23)) {
1895 uint32_t code = svc & kStopCodeMask;
1896 if (isWatchedStop(code)) {
1897 IncreaseStopCounter(code);
1899 // Stop if it is enabled, otherwise go on jumping over the stop
1900 // and the message address.
1901 if (isEnabledStop(code)) {
1902 ArmDebugger dbg(this);
1905 set_pc(get_pc() + 2 * Instruction::kInstrSize);
1908 // This is not a valid svc code.
1917 double Simulator::canonicalizeNaN(double value) {
1918 // Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
1919 // choices" of the ARM Reference Manual.
1920 const uint64_t kDefaultNaN = V8_UINT64_C(0x7FF8000000000000);
1921 if (FPSCR_default_NaN_mode_ && std::isnan(value)) {
1922 value = bit_cast<double>(kDefaultNaN);
1928 // Stop helper functions.
1929 bool Simulator::isStopInstruction(Instruction* instr) {
1930 return (instr->Bits(27, 24) == 0xF) && (instr->SvcValue() >= kStopCode);
1934 bool Simulator::isWatchedStop(uint32_t code) {
1935 DCHECK(code <= kMaxStopCode);
1936 return code < kNumOfWatchedStops;
1940 bool Simulator::isEnabledStop(uint32_t code) {
1941 DCHECK(code <= kMaxStopCode);
1942 // Unwatched stops are always enabled.
1943 return !isWatchedStop(code) ||
1944 !(watched_stops_[code].count & kStopDisabledBit);
1948 void Simulator::EnableStop(uint32_t code) {
1949 DCHECK(isWatchedStop(code));
1950 if (!isEnabledStop(code)) {
1951 watched_stops_[code].count &= ~kStopDisabledBit;
1956 void Simulator::DisableStop(uint32_t code) {
1957 DCHECK(isWatchedStop(code));
1958 if (isEnabledStop(code)) {
1959 watched_stops_[code].count |= kStopDisabledBit;
1964 void Simulator::IncreaseStopCounter(uint32_t code) {
1965 DCHECK(code <= kMaxStopCode);
1966 DCHECK(isWatchedStop(code));
1967 if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) {
1968 PrintF("Stop counter for code %i has overflowed.\n"
1969 "Enabling this code and reseting the counter to 0.\n", code);
1970 watched_stops_[code].count = 0;
1973 watched_stops_[code].count++;
1978 // Print a stop status.
1979 void Simulator::PrintStopInfo(uint32_t code) {
1980 DCHECK(code <= kMaxStopCode);
1981 if (!isWatchedStop(code)) {
1982 PrintF("Stop not watched.");
1984 const char* state = isEnabledStop(code) ? "Enabled" : "Disabled";
1985 int32_t count = watched_stops_[code].count & ~kStopDisabledBit;
1986 // Don't print the state of unused breakpoints.
1988 if (watched_stops_[code].desc) {
1989 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n",
1990 code, code, state, count, watched_stops_[code].desc);
1992 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n",
1993 code, code, state, count);
2000 // Handle execution based on instruction types.
2002 // Instruction types 0 and 1 are both rolled into one function because they
2003 // only differ in the handling of the shifter_operand.
2004 void Simulator::DecodeType01(Instruction* instr) {
2005 int type = instr->TypeValue();
2006 if ((type == 0) && instr->IsSpecialType0()) {
2007 // multiply instruction or extra loads and stores
2008 if (instr->Bits(7, 4) == 9) {
2009 if (instr->Bit(24) == 0) {
2010 // Raw field decoding here. Multiply instructions have their Rd in
2012 int rn = instr->RnValue();
2013 int rm = instr->RmValue();
2014 int rs = instr->RsValue();
2015 int32_t rs_val = get_register(rs);
2016 int32_t rm_val = get_register(rm);
2017 if (instr->Bit(23) == 0) {
2018 if (instr->Bit(21) == 0) {
2019 // The MUL instruction description (A 4.1.33) refers to Rd as being
2020 // the destination for the operation, but it confusingly uses the
2021 // Rn field to encode it.
2022 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
2023 int rd = rn; // Remap the rn field to the Rd register.
2024 int32_t alu_out = rm_val * rs_val;
2025 set_register(rd, alu_out);
2026 if (instr->HasS()) {
2027 SetNZFlags(alu_out);
2030 int rd = instr->RdValue();
2031 int32_t acc_value = get_register(rd);
2032 if (instr->Bit(22) == 0) {
2033 // The MLA instruction description (A 4.1.28) refers to the order
2034 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2035 // Rn field to encode the Rd register and the Rd field to encode
2037 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2038 int32_t mul_out = rm_val * rs_val;
2039 int32_t result = acc_value + mul_out;
2040 set_register(rn, result);
2042 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
2043 int32_t mul_out = rm_val * rs_val;
2044 int32_t result = acc_value - mul_out;
2045 set_register(rn, result);
2049 // The signed/long multiply instructions use the terms RdHi and RdLo
2050 // when referring to the target registers. They are mapped to the Rn
2051 // and Rd fields as follows:
2053 // RdHi == Rn (This is confusingly stored in variable rd here
2054 // because the mul instruction from above uses the
2055 // Rn field to encode the Rd register. Good luck figuring
2056 // this out without reading the ARM instruction manual
2057 // at a very detailed level.)
2058 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2059 int rd_hi = rn; // Remap the rn field to the RdHi register.
2060 int rd_lo = instr->RdValue();
2063 if (instr->Bit(22) == 1) {
2064 int64_t left_op = static_cast<int32_t>(rm_val);
2065 int64_t right_op = static_cast<int32_t>(rs_val);
2066 uint64_t result = left_op * right_op;
2067 hi_res = static_cast<int32_t>(result >> 32);
2068 lo_res = static_cast<int32_t>(result & 0xffffffff);
2070 // unsigned multiply
2071 uint64_t left_op = static_cast<uint32_t>(rm_val);
2072 uint64_t right_op = static_cast<uint32_t>(rs_val);
2073 uint64_t result = left_op * right_op;
2074 hi_res = static_cast<int32_t>(result >> 32);
2075 lo_res = static_cast<int32_t>(result & 0xffffffff);
2077 set_register(rd_lo, lo_res);
2078 set_register(rd_hi, hi_res);
2079 if (instr->HasS()) {
2084 UNIMPLEMENTED(); // Not used by V8.
2087 // extra load/store instructions
2088 int rd = instr->RdValue();
2089 int rn = instr->RnValue();
2090 int32_t rn_val = get_register(rn);
2092 if (instr->Bit(22) == 0) {
2093 int rm = instr->RmValue();
2094 int32_t rm_val = get_register(rm);
2095 switch (instr->PUField()) {
2097 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2098 DCHECK(!instr->HasW());
2101 set_register(rn, rn_val);
2105 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2106 DCHECK(!instr->HasW());
2109 set_register(rn, rn_val);
2113 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2116 if (instr->HasW()) {
2117 set_register(rn, rn_val);
2122 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2125 if (instr->HasW()) {
2126 set_register(rn, rn_val);
2131 // The PU field is a 2-bit field.
2137 int32_t imm_val = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
2138 switch (instr->PUField()) {
2140 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
2141 DCHECK(!instr->HasW());
2144 set_register(rn, rn_val);
2148 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
2149 DCHECK(!instr->HasW());
2152 set_register(rn, rn_val);
2156 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
2159 if (instr->HasW()) {
2160 set_register(rn, rn_val);
2165 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
2168 if (instr->HasW()) {
2169 set_register(rn, rn_val);
2174 // The PU field is a 2-bit field.
2180 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
2181 DCHECK((rd % 2) == 0);
2182 if (instr->HasH()) {
2183 // The strd instruction.
2184 int32_t value1 = get_register(rd);
2185 int32_t value2 = get_register(rd+1);
2186 WriteDW(addr, value1, value2);
2188 // The ldrd instruction.
2189 int* rn_data = ReadDW(addr);
2190 set_dw_register(rd, rn_data);
2192 } else if (instr->HasH()) {
2193 if (instr->HasSign()) {
2194 if (instr->HasL()) {
2195 int16_t val = ReadH(addr, instr);
2196 set_register(rd, val);
2198 int16_t val = get_register(rd);
2199 WriteH(addr, val, instr);
2202 if (instr->HasL()) {
2203 uint16_t val = ReadHU(addr, instr);
2204 set_register(rd, val);
2206 uint16_t val = get_register(rd);
2207 WriteH(addr, val, instr);
2211 // signed byte loads
2212 DCHECK(instr->HasSign());
2213 DCHECK(instr->HasL());
2214 int8_t val = ReadB(addr);
2215 set_register(rd, val);
2219 } else if ((type == 0) && instr->IsMiscType0()) {
2220 if (instr->Bits(22, 21) == 1) {
2221 int rm = instr->RmValue();
2222 switch (instr->BitField(7, 4)) {
2224 set_pc(get_register(rm));
2227 uint32_t old_pc = get_pc();
2228 set_pc(get_register(rm));
2229 set_register(lr, old_pc + Instruction::kInstrSize);
2233 ArmDebugger dbg(this);
2234 PrintF("Simulator hit BKPT.\n");
2241 } else if (instr->Bits(22, 21) == 3) {
2242 int rm = instr->RmValue();
2243 int rd = instr->RdValue();
2244 switch (instr->BitField(7, 4)) {
2246 uint32_t bits = get_register(rm);
2247 int leading_zeros = 0;
2251 while ((bits & 0x80000000u) == 0) {
2256 set_register(rd, leading_zeros);
2263 PrintF("%08x\n", instr->InstructionBits());
2266 } else if ((type == 1) && instr->IsNopType1()) {
2269 int rd = instr->RdValue();
2270 int rn = instr->RnValue();
2271 int32_t rn_val = get_register(rn);
2272 int32_t shifter_operand = 0;
2273 bool shifter_carry_out = 0;
2275 shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2277 DCHECK(instr->TypeValue() == 1);
2278 shifter_operand = GetImm(instr, &shifter_carry_out);
2282 switch (instr->OpcodeField()) {
2284 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
2285 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
2286 alu_out = rn_val & shifter_operand;
2287 set_register(rd, alu_out);
2288 if (instr->HasS()) {
2289 SetNZFlags(alu_out);
2290 SetCFlag(shifter_carry_out);
2296 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
2297 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
2298 alu_out = rn_val ^ shifter_operand;
2299 set_register(rd, alu_out);
2300 if (instr->HasS()) {
2301 SetNZFlags(alu_out);
2302 SetCFlag(shifter_carry_out);
2308 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
2309 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
2310 alu_out = rn_val - shifter_operand;
2311 set_register(rd, alu_out);
2312 if (instr->HasS()) {
2313 SetNZFlags(alu_out);
2314 SetCFlag(!BorrowFrom(rn_val, shifter_operand));
2315 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
2321 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
2322 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
2323 alu_out = shifter_operand - rn_val;
2324 set_register(rd, alu_out);
2325 if (instr->HasS()) {
2326 SetNZFlags(alu_out);
2327 SetCFlag(!BorrowFrom(shifter_operand, rn_val));
2328 SetVFlag(OverflowFrom(alu_out, shifter_operand, rn_val, false));
2334 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
2335 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
2336 alu_out = rn_val + shifter_operand;
2337 set_register(rd, alu_out);
2338 if (instr->HasS()) {
2339 SetNZFlags(alu_out);
2340 SetCFlag(CarryFrom(rn_val, shifter_operand));
2341 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
2347 // Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
2348 // Format(instr, "adc'cond's 'rd, 'rn, 'imm");
2349 alu_out = rn_val + shifter_operand + GetCarry();
2350 set_register(rd, alu_out);
2351 if (instr->HasS()) {
2352 SetNZFlags(alu_out);
2353 SetCFlag(CarryFrom(rn_val, shifter_operand, GetCarry()));
2354 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
2360 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
2361 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
2366 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
2367 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
2372 if (instr->HasS()) {
2373 // Format(instr, "tst'cond 'rn, 'shift_rm");
2374 // Format(instr, "tst'cond 'rn, 'imm");
2375 alu_out = rn_val & shifter_operand;
2376 SetNZFlags(alu_out);
2377 SetCFlag(shifter_carry_out);
2379 // Format(instr, "movw'cond 'rd, 'imm").
2380 alu_out = instr->ImmedMovwMovtValue();
2381 set_register(rd, alu_out);
2387 if (instr->HasS()) {
2388 // Format(instr, "teq'cond 'rn, 'shift_rm");
2389 // Format(instr, "teq'cond 'rn, 'imm");
2390 alu_out = rn_val ^ shifter_operand;
2391 SetNZFlags(alu_out);
2392 SetCFlag(shifter_carry_out);
2394 // Other instructions matching this pattern are handled in the
2395 // miscellaneous instructions part above.
2402 if (instr->HasS()) {
2403 // Format(instr, "cmp'cond 'rn, 'shift_rm");
2404 // Format(instr, "cmp'cond 'rn, 'imm");
2405 alu_out = rn_val - shifter_operand;
2406 SetNZFlags(alu_out);
2407 SetCFlag(!BorrowFrom(rn_val, shifter_operand));
2408 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
2410 // Format(instr, "movt'cond 'rd, 'imm").
2411 alu_out = (get_register(rd) & 0xffff) |
2412 (instr->ImmedMovwMovtValue() << 16);
2413 set_register(rd, alu_out);
2419 if (instr->HasS()) {
2420 // Format(instr, "cmn'cond 'rn, 'shift_rm");
2421 // Format(instr, "cmn'cond 'rn, 'imm");
2422 alu_out = rn_val + shifter_operand;
2423 SetNZFlags(alu_out);
2424 SetCFlag(CarryFrom(rn_val, shifter_operand));
2425 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
2427 // Other instructions matching this pattern are handled in the
2428 // miscellaneous instructions part above.
2435 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2436 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2437 alu_out = rn_val | shifter_operand;
2438 set_register(rd, alu_out);
2439 if (instr->HasS()) {
2440 SetNZFlags(alu_out);
2441 SetCFlag(shifter_carry_out);
2447 // Format(instr, "mov'cond's 'rd, 'shift_rm");
2448 // Format(instr, "mov'cond's 'rd, 'imm");
2449 alu_out = shifter_operand;
2450 set_register(rd, alu_out);
2451 if (instr->HasS()) {
2452 SetNZFlags(alu_out);
2453 SetCFlag(shifter_carry_out);
2459 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2460 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2461 alu_out = rn_val & ~shifter_operand;
2462 set_register(rd, alu_out);
2463 if (instr->HasS()) {
2464 SetNZFlags(alu_out);
2465 SetCFlag(shifter_carry_out);
2471 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
2472 // Format(instr, "mvn'cond's 'rd, 'imm");
2473 alu_out = ~shifter_operand;
2474 set_register(rd, alu_out);
2475 if (instr->HasS()) {
2476 SetNZFlags(alu_out);
2477 SetCFlag(shifter_carry_out);
2491 void Simulator::DecodeType2(Instruction* instr) {
2492 int rd = instr->RdValue();
2493 int rn = instr->RnValue();
2494 int32_t rn_val = get_register(rn);
2495 int32_t im_val = instr->Offset12Value();
2497 switch (instr->PUField()) {
2499 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2500 DCHECK(!instr->HasW());
2503 set_register(rn, rn_val);
2507 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2508 DCHECK(!instr->HasW());
2511 set_register(rn, rn_val);
2515 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2518 if (instr->HasW()) {
2519 set_register(rn, rn_val);
2524 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2527 if (instr->HasW()) {
2528 set_register(rn, rn_val);
2537 if (instr->HasB()) {
2538 if (instr->HasL()) {
2539 byte val = ReadBU(addr);
2540 set_register(rd, val);
2542 byte val = get_register(rd);
2546 if (instr->HasL()) {
2547 set_register(rd, ReadW(addr, instr));
2549 WriteW(addr, get_register(rd), instr);
2555 void Simulator::DecodeType3(Instruction* instr) {
2556 int rd = instr->RdValue();
2557 int rn = instr->RnValue();
2558 int32_t rn_val = get_register(rn);
2559 bool shifter_carry_out = 0;
2560 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2562 switch (instr->PUField()) {
2564 DCHECK(!instr->HasW());
2565 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2570 if (instr->Bit(4) == 0) {
2573 if (instr->Bit(5) == 0) {
2574 switch (instr->Bits(22, 21)) {
2576 if (instr->Bit(20) == 0) {
2577 if (instr->Bit(6) == 0) {
2579 uint32_t rn_val = get_register(rn);
2580 uint32_t rm_val = get_register(instr->RmValue());
2581 int32_t shift = instr->Bits(11, 7);
2583 set_register(rd, (rn_val & 0xFFFF) | (rm_val & 0xFFFF0000U));
2586 uint32_t rn_val = get_register(rn);
2587 int32_t rm_val = get_register(instr->RmValue());
2588 int32_t shift = instr->Bits(11, 7);
2593 set_register(rd, (rn_val & 0xFFFF0000U) | (rm_val & 0xFFFF));
2607 int32_t sat_pos = instr->Bits(20, 16);
2608 int32_t sat_val = (1 << sat_pos) - 1;
2609 int32_t shift = instr->Bits(11, 7);
2610 int32_t shift_type = instr->Bit(6);
2611 int32_t rm_val = get_register(instr->RmValue());
2612 if (shift_type == 0) { // LSL
2617 // If saturation occurs, the Q flag should be set in the CPSR.
2618 // There is no Q flag yet, and no instruction (MRS) to read the
2620 if (rm_val > sat_val) {
2622 } else if (rm_val < 0) {
2625 set_register(rd, rm_val);
2630 switch (instr->Bits(22, 21)) {
2635 if (instr->Bits(9, 6) == 1) {
2636 if (instr->Bit(20) == 0) {
2637 if (instr->Bits(19, 16) == 0xF) {
2639 int32_t rm_val = get_register(instr->RmValue());
2640 int32_t rotate = instr->Bits(11, 10);
2645 rm_val = (rm_val >> 8) | (rm_val << 24);
2648 rm_val = (rm_val >> 16) | (rm_val << 16);
2651 rm_val = (rm_val >> 24) | (rm_val << 8);
2654 set_register(rd, static_cast<int8_t>(rm_val));
2657 int32_t rn_val = get_register(rn);
2658 int32_t rm_val = get_register(instr->RmValue());
2659 int32_t rotate = instr->Bits(11, 10);
2664 rm_val = (rm_val >> 8) | (rm_val << 24);
2667 rm_val = (rm_val >> 16) | (rm_val << 16);
2670 rm_val = (rm_val >> 24) | (rm_val << 8);
2673 set_register(rd, rn_val + static_cast<int8_t>(rm_val));
2676 if (instr->Bits(19, 16) == 0xF) {
2678 int32_t rm_val = get_register(instr->RmValue());
2679 int32_t rotate = instr->Bits(11, 10);
2684 rm_val = (rm_val >> 8) | (rm_val << 24);
2687 rm_val = (rm_val >> 16) | (rm_val << 16);
2690 rm_val = (rm_val >> 24) | (rm_val << 8);
2693 set_register(rd, static_cast<int16_t>(rm_val));
2696 int32_t rn_val = get_register(rn);
2697 int32_t rm_val = get_register(instr->RmValue());
2698 int32_t rotate = instr->Bits(11, 10);
2703 rm_val = (rm_val >> 8) | (rm_val << 24);
2706 rm_val = (rm_val >> 16) | (rm_val << 16);
2709 rm_val = (rm_val >> 24) | (rm_val << 8);
2712 set_register(rd, rn_val + static_cast<int16_t>(rm_val));
2720 if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) {
2721 if (instr->Bits(19, 16) == 0xF) {
2723 uint32_t rm_val = get_register(instr->RmValue());
2724 int32_t rotate = instr->Bits(11, 10);
2729 rm_val = (rm_val >> 8) | (rm_val << 24);
2732 rm_val = (rm_val >> 16) | (rm_val << 16);
2735 rm_val = (rm_val >> 24) | (rm_val << 8);
2738 set_register(rd, (rm_val & 0xFF) | (rm_val & 0xFF0000));
2747 if ((instr->Bits(9, 6) == 1)) {
2748 if (instr->Bit(20) == 0) {
2749 if (instr->Bits(19, 16) == 0xF) {
2751 uint32_t rm_val = get_register(instr->RmValue());
2752 int32_t rotate = instr->Bits(11, 10);
2757 rm_val = (rm_val >> 8) | (rm_val << 24);
2760 rm_val = (rm_val >> 16) | (rm_val << 16);
2763 rm_val = (rm_val >> 24) | (rm_val << 8);
2766 set_register(rd, (rm_val & 0xFF));
2769 uint32_t rn_val = get_register(rn);
2770 uint32_t rm_val = get_register(instr->RmValue());
2771 int32_t rotate = instr->Bits(11, 10);
2776 rm_val = (rm_val >> 8) | (rm_val << 24);
2779 rm_val = (rm_val >> 16) | (rm_val << 16);
2782 rm_val = (rm_val >> 24) | (rm_val << 8);
2785 set_register(rd, rn_val + (rm_val & 0xFF));
2788 if (instr->Bits(19, 16) == 0xF) {
2790 uint32_t rm_val = get_register(instr->RmValue());
2791 int32_t rotate = instr->Bits(11, 10);
2796 rm_val = (rm_val >> 8) | (rm_val << 24);
2799 rm_val = (rm_val >> 16) | (rm_val << 16);
2802 rm_val = (rm_val >> 24) | (rm_val << 8);
2805 set_register(rd, (rm_val & 0xFFFF));
2808 uint32_t rn_val = get_register(rn);
2809 uint32_t rm_val = get_register(instr->RmValue());
2810 int32_t rotate = instr->Bits(11, 10);
2815 rm_val = (rm_val >> 8) | (rm_val << 24);
2818 rm_val = (rm_val >> 16) | (rm_val << 16);
2821 rm_val = (rm_val >> 24) | (rm_val << 8);
2824 set_register(rd, rn_val + (rm_val & 0xFFFF));
2838 if (instr->Bits(22, 20) == 0x5) {
2839 if (instr->Bits(7, 4) == 0x1) {
2840 int rm = instr->RmValue();
2841 int32_t rm_val = get_register(rm);
2842 int rs = instr->RsValue();
2843 int32_t rs_val = get_register(rs);
2844 if (instr->Bits(15, 12) == 0xF) {
2845 // SMMUL (in V8 notation matching ARM ISA format)
2846 // Format(instr, "smmul'cond 'rn, 'rm, 'rs");
2847 rn_val = base::bits::SignedMulHigh32(rm_val, rs_val);
2849 // SMMLA (in V8 notation matching ARM ISA format)
2850 // Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd");
2851 int rd = instr->RdValue();
2852 int32_t rd_val = get_register(rd);
2853 rn_val = base::bits::SignedMulHighAndAdd32(rm_val, rs_val, rd_val);
2855 set_register(rn, rn_val);
2859 if (FLAG_enable_sudiv) {
2860 if (instr->Bits(5, 4) == 0x1) {
2861 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
2862 // (s/u)div (in V8 notation matching ARM ISA format) rn = rm/rs
2863 // Format(instr, "'(s/u)div'cond'b 'rn, 'rm, 'rs);
2864 int rm = instr->RmValue();
2865 int32_t rm_val = get_register(rm);
2866 int rs = instr->RsValue();
2867 int32_t rs_val = get_register(rs);
2868 int32_t ret_val = 0;
2870 if (instr->Bit(21) == 0x1) {
2871 ret_val = bit_cast<int32_t>(base::bits::UnsignedDiv32(
2872 bit_cast<uint32_t>(rm_val), bit_cast<uint32_t>(rs_val)));
2874 ret_val = base::bits::SignedDiv32(rm_val, rs_val);
2876 set_register(rn, ret_val);
2881 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2882 addr = rn_val - shifter_operand;
2883 if (instr->HasW()) {
2884 set_register(rn, addr);
2889 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
2890 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
2891 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2892 uint32_t msbit = widthminus1 + lsbit;
2894 if (instr->Bit(22)) {
2895 // ubfx - unsigned bitfield extract.
2897 static_cast<uint32_t>(get_register(instr->RmValue()));
2898 uint32_t extr_val = rm_val << (31 - msbit);
2899 extr_val = extr_val >> (31 - widthminus1);
2900 set_register(instr->RdValue(), extr_val);
2902 // sbfx - signed bitfield extract.
2903 int32_t rm_val = get_register(instr->RmValue());
2904 int32_t extr_val = rm_val << (31 - msbit);
2905 extr_val = extr_val >> (31 - widthminus1);
2906 set_register(instr->RdValue(), extr_val);
2912 } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
2913 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2914 uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
2915 if (msbit >= lsbit) {
2916 // bfc or bfi - bitfield clear/insert.
2918 static_cast<uint32_t>(get_register(instr->RdValue()));
2919 uint32_t bitcount = msbit - lsbit + 1;
2920 uint32_t mask = 0xffffffffu >> (32 - bitcount);
2921 rd_val &= ~(mask << lsbit);
2922 if (instr->RmValue() != 15) {
2923 // bfi - bitfield insert.
2925 static_cast<uint32_t>(get_register(instr->RmValue()));
2927 rd_val |= rm_val << lsbit;
2929 set_register(instr->RdValue(), rd_val);
2935 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2936 addr = rn_val + shifter_operand;
2937 if (instr->HasW()) {
2938 set_register(rn, addr);
2948 if (instr->HasB()) {
2949 if (instr->HasL()) {
2950 uint8_t byte = ReadB(addr);
2951 set_register(rd, byte);
2953 uint8_t byte = get_register(rd);
2957 if (instr->HasL()) {
2958 set_register(rd, ReadW(addr, instr));
2960 WriteW(addr, get_register(rd), instr);
2966 void Simulator::DecodeType4(Instruction* instr) {
2967 DCHECK(instr->Bit(22) == 0); // only allowed to be set in privileged mode
2968 if (instr->HasL()) {
2969 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
2970 HandleRList(instr, true);
2972 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
2973 HandleRList(instr, false);
2978 void Simulator::DecodeType5(Instruction* instr) {
2979 // Format(instr, "b'l'cond 'target");
2980 int off = (instr->SImmed24Value() << 2);
2981 intptr_t pc_address = get_pc();
2982 if (instr->HasLink()) {
2983 set_register(lr, pc_address + Instruction::kInstrSize);
2985 int pc_reg = get_register(pc);
2986 set_pc(pc_reg + off);
2990 void Simulator::DecodeType6(Instruction* instr) {
2991 DecodeType6CoprocessorIns(instr);
2995 void Simulator::DecodeType7(Instruction* instr) {
2996 if (instr->Bit(24) == 1) {
2997 SoftwareInterrupt(instr);
2999 DecodeTypeVFP(instr);
3004 // void Simulator::DecodeTypeVFP(Instruction* instr)
3005 // The Following ARMv7 VFPv instructions are currently supported.
3010 // vcvt.f64.s32 Dd, Dd, #<fbits>
3013 // Dd = vadd(Dn, Dm)
3014 // Dd = vsub(Dn, Dm)
3015 // Dd = vmul(Dn, Dm)
3016 // Dd = vdiv(Dn, Dm)
3020 void Simulator::DecodeTypeVFP(Instruction* instr) {
3021 DCHECK((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
3022 DCHECK(instr->Bits(11, 9) == 0x5);
3024 // Obtain double precision register codes.
3025 int vm = instr->VFPMRegValue(kDoublePrecision);
3026 int vd = instr->VFPDRegValue(kDoublePrecision);
3027 int vn = instr->VFPNRegValue(kDoublePrecision);
3029 if (instr->Bit(4) == 0) {
3030 if (instr->Opc1Value() == 0x7) {
3031 // Other data processing instructions
3032 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
3033 // vmov register to register.
3034 if (instr->SzValue() == 0x1) {
3035 int m = instr->VFPMRegValue(kDoublePrecision);
3036 int d = instr->VFPDRegValue(kDoublePrecision);
3038 get_d_register(m, data);
3039 set_d_register(d, data);
3041 int m = instr->VFPMRegValue(kSinglePrecision);
3042 int d = instr->VFPDRegValue(kSinglePrecision);
3043 set_s_register_from_float(d, get_float_from_s_register(m));
3045 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
3047 double dm_value = get_double_from_d_register(vm);
3048 double dd_value = std::fabs(dm_value);
3049 dd_value = canonicalizeNaN(dd_value);
3050 set_d_register_from_double(vd, dd_value);
3051 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
3053 double dm_value = get_double_from_d_register(vm);
3054 double dd_value = -dm_value;
3055 dd_value = canonicalizeNaN(dd_value);
3056 set_d_register_from_double(vd, dd_value);
3057 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
3058 DecodeVCVTBetweenDoubleAndSingle(instr);
3059 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
3060 DecodeVCVTBetweenFloatingPointAndInteger(instr);
3061 } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
3062 (instr->Bit(8) == 1)) {
3063 // vcvt.f64.s32 Dd, Dd, #<fbits>
3064 int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5));
3065 int fixed_value = get_sinteger_from_s_register(vd * 2);
3066 double divide = 1 << fraction_bits;
3067 set_d_register_from_double(vd, fixed_value / divide);
3068 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
3069 (instr->Opc3Value() & 0x1)) {
3070 DecodeVCVTBetweenFloatingPointAndInteger(instr);
3071 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
3072 (instr->Opc3Value() & 0x1)) {
3074 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
3076 double dm_value = get_double_from_d_register(vm);
3077 double dd_value = fast_sqrt(dm_value);
3078 dd_value = canonicalizeNaN(dd_value);
3079 set_d_register_from_double(vd, dd_value);
3080 } else if (instr->Opc3Value() == 0x0) {
3082 if (instr->SzValue() == 0x1) {
3083 set_d_register_from_double(vd, instr->DoubleImmedVmov());
3085 UNREACHABLE(); // Not used by v8.
3087 } else if (((instr->Opc2Value() == 0x6)) && (instr->Opc3Value() == 0x3)) {
3088 // vrintz - truncate
3089 double dm_value = get_double_from_d_register(vm);
3090 double dd_value = trunc(dm_value);
3091 dd_value = canonicalizeNaN(dd_value);
3092 set_d_register_from_double(vd, dd_value);
3094 UNREACHABLE(); // Not used by V8.
3096 } else if (instr->Opc1Value() == 0x3) {
3097 if (instr->SzValue() != 0x1) {
3098 UNREACHABLE(); // Not used by V8.
3101 if (instr->Opc3Value() & 0x1) {
3103 double dn_value = get_double_from_d_register(vn);
3104 double dm_value = get_double_from_d_register(vm);
3105 double dd_value = dn_value - dm_value;
3106 dd_value = canonicalizeNaN(dd_value);
3107 set_d_register_from_double(vd, dd_value);
3110 double dn_value = get_double_from_d_register(vn);
3111 double dm_value = get_double_from_d_register(vm);
3112 double dd_value = dn_value + dm_value;
3113 dd_value = canonicalizeNaN(dd_value);
3114 set_d_register_from_double(vd, dd_value);
3116 } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
3118 if (instr->SzValue() != 0x1) {
3119 UNREACHABLE(); // Not used by V8.
3122 double dn_value = get_double_from_d_register(vn);
3123 double dm_value = get_double_from_d_register(vm);
3124 double dd_value = dn_value * dm_value;
3125 dd_value = canonicalizeNaN(dd_value);
3126 set_d_register_from_double(vd, dd_value);
3127 } else if ((instr->Opc1Value() == 0x0)) {
3129 const bool is_vmls = (instr->Opc3Value() & 0x1);
3131 if (instr->SzValue() != 0x1) {
3132 UNREACHABLE(); // Not used by V8.
3135 const double dd_val = get_double_from_d_register(vd);
3136 const double dn_val = get_double_from_d_register(vn);
3137 const double dm_val = get_double_from_d_register(vm);
3139 // Note: we do the mul and add/sub in separate steps to avoid getting a
3140 // result with too high precision.
3141 set_d_register_from_double(vd, dn_val * dm_val);
3143 set_d_register_from_double(
3145 canonicalizeNaN(dd_val - get_double_from_d_register(vd)));
3147 set_d_register_from_double(
3149 canonicalizeNaN(dd_val + get_double_from_d_register(vd)));
3151 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
3153 if (instr->SzValue() != 0x1) {
3154 UNREACHABLE(); // Not used by V8.
3157 double dn_value = get_double_from_d_register(vn);
3158 double dm_value = get_double_from_d_register(vm);
3159 double dd_value = dn_value / dm_value;
3160 div_zero_vfp_flag_ = (dm_value == 0);
3161 dd_value = canonicalizeNaN(dd_value);
3162 set_d_register_from_double(vd, dd_value);
3164 UNIMPLEMENTED(); // Not used by V8.
3167 if ((instr->VCValue() == 0x0) &&
3168 (instr->VAValue() == 0x0)) {
3169 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
3170 } else if ((instr->VLValue() == 0x0) &&
3171 (instr->VCValue() == 0x1) &&
3172 (instr->Bit(23) == 0x0)) {
3173 // vmov (ARM core register to scalar)
3174 int vd = instr->Bits(19, 16) | (instr->Bit(7) << 4);
3176 get_d_register(vd, data);
3177 data[instr->Bit(21)] = get_register(instr->RtValue());
3178 set_d_register(vd, data);
3179 } else if ((instr->VLValue() == 0x1) &&
3180 (instr->VCValue() == 0x1) &&
3181 (instr->Bit(23) == 0x0)) {
3182 // vmov (scalar to ARM core register)
3183 int vn = instr->Bits(19, 16) | (instr->Bit(7) << 4);
3184 double dn_value = get_double_from_d_register(vn);
3186 memcpy(data, &dn_value, 8);
3187 set_register(instr->RtValue(), data[instr->Bit(21)]);
3188 } else if ((instr->VLValue() == 0x1) &&
3189 (instr->VCValue() == 0x0) &&
3190 (instr->VAValue() == 0x7) &&
3191 (instr->Bits(19, 16) == 0x1)) {
3193 uint32_t rt = instr->RtValue();
3195 Copy_FPSCR_to_APSR();
3197 // Emulate FPSCR from the Simulator flags.
3198 uint32_t fpscr = (n_flag_FPSCR_ << 31) |
3199 (z_flag_FPSCR_ << 30) |
3200 (c_flag_FPSCR_ << 29) |
3201 (v_flag_FPSCR_ << 28) |
3202 (FPSCR_default_NaN_mode_ << 25) |
3203 (inexact_vfp_flag_ << 4) |
3204 (underflow_vfp_flag_ << 3) |
3205 (overflow_vfp_flag_ << 2) |
3206 (div_zero_vfp_flag_ << 1) |
3207 (inv_op_vfp_flag_ << 0) |
3208 (FPSCR_rounding_mode_);
3209 set_register(rt, fpscr);
3211 } else if ((instr->VLValue() == 0x0) &&
3212 (instr->VCValue() == 0x0) &&
3213 (instr->VAValue() == 0x7) &&
3214 (instr->Bits(19, 16) == 0x1)) {
3216 uint32_t rt = instr->RtValue();
3220 uint32_t rt_value = get_register(rt);
3221 n_flag_FPSCR_ = (rt_value >> 31) & 1;
3222 z_flag_FPSCR_ = (rt_value >> 30) & 1;
3223 c_flag_FPSCR_ = (rt_value >> 29) & 1;
3224 v_flag_FPSCR_ = (rt_value >> 28) & 1;
3225 FPSCR_default_NaN_mode_ = (rt_value >> 25) & 1;
3226 inexact_vfp_flag_ = (rt_value >> 4) & 1;
3227 underflow_vfp_flag_ = (rt_value >> 3) & 1;
3228 overflow_vfp_flag_ = (rt_value >> 2) & 1;
3229 div_zero_vfp_flag_ = (rt_value >> 1) & 1;
3230 inv_op_vfp_flag_ = (rt_value >> 0) & 1;
3231 FPSCR_rounding_mode_ =
3232 static_cast<VFPRoundingMode>((rt_value) & kVFPRoundingModeMask);
3235 UNIMPLEMENTED(); // Not used by V8.
3241 void Simulator::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
3242 Instruction* instr) {
3243 DCHECK((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
3244 (instr->VAValue() == 0x0));
3246 int t = instr->RtValue();
3247 int n = instr->VFPNRegValue(kSinglePrecision);
3248 bool to_arm_register = (instr->VLValue() == 0x1);
3250 if (to_arm_register) {
3251 int32_t int_value = get_sinteger_from_s_register(n);
3252 set_register(t, int_value);
3254 int32_t rs_val = get_register(t);
3255 set_s_register_from_sinteger(n, rs_val);
3260 void Simulator::DecodeVCMP(Instruction* instr) {
3261 DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
3262 DCHECK(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
3263 (instr->Opc3Value() & 0x1));
3266 VFPRegPrecision precision = kSinglePrecision;
3267 if (instr->SzValue() == 1) {
3268 precision = kDoublePrecision;
3271 int d = instr->VFPDRegValue(precision);
3273 if (instr->Opc2Value() == 0x4) {
3274 m = instr->VFPMRegValue(precision);
3277 if (precision == kDoublePrecision) {
3278 double dd_value = get_double_from_d_register(d);
3279 double dm_value = 0.0;
3280 if (instr->Opc2Value() == 0x4) {
3281 dm_value = get_double_from_d_register(m);
3284 // Raise exceptions for quiet NaNs if necessary.
3285 if (instr->Bit(7) == 1) {
3286 if (std::isnan(dd_value)) {
3287 inv_op_vfp_flag_ = true;
3291 Compute_FPSCR_Flags(dd_value, dm_value);
3293 UNIMPLEMENTED(); // Not used by V8.
3298 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
3299 DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
3300 DCHECK((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
3302 VFPRegPrecision dst_precision = kDoublePrecision;
3303 VFPRegPrecision src_precision = kSinglePrecision;
3304 if (instr->SzValue() == 1) {
3305 dst_precision = kSinglePrecision;
3306 src_precision = kDoublePrecision;
3309 int dst = instr->VFPDRegValue(dst_precision);
3310 int src = instr->VFPMRegValue(src_precision);
3312 if (dst_precision == kSinglePrecision) {
3313 double val = get_double_from_d_register(src);
3314 set_s_register_from_float(dst, static_cast<float>(val));
3316 float val = get_float_from_s_register(src);
3317 set_d_register_from_double(dst, static_cast<double>(val));
3321 bool get_inv_op_vfp_flag(VFPRoundingMode mode,
3324 DCHECK((mode == RN) || (mode == RM) || (mode == RZ));
3325 double max_uint = static_cast<double>(0xffffffffu);
3326 double max_int = static_cast<double>(kMaxInt);
3327 double min_int = static_cast<double>(kMinInt);
3334 // Check for overflow. This code works because 32bit integers can be
3335 // exactly represented by ieee-754 64bit floating-point values.
3338 return unsigned_ ? (val >= (max_uint + 0.5)) ||
3340 : (val >= (max_int + 0.5)) ||
3341 (val < (min_int - 0.5));
3344 return unsigned_ ? (val >= (max_uint + 1.0)) ||
3346 : (val >= (max_int + 1.0)) ||
3350 return unsigned_ ? (val >= (max_uint + 1.0)) ||
3352 : (val >= (max_int + 1.0)) ||
3353 (val <= (min_int - 1.0));
3361 // We call this function only if we had a vfp invalid exception.
3362 // It returns the correct saturated value.
3363 int VFPConversionSaturate(double val, bool unsigned_res) {
3368 return (val < 0) ? 0 : 0xffffffffu;
3370 return (val < 0) ? kMinInt : kMaxInt;
3376 void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
3377 DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7) &&
3378 (instr->Bits(27, 23) == 0x1D));
3379 DCHECK(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
3380 (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
3382 // Conversion between floating-point and integer.
3383 bool to_integer = (instr->Bit(18) == 1);
3385 VFPRegPrecision src_precision = (instr->SzValue() == 1) ? kDoublePrecision
3389 // We are playing with code close to the C++ standard's limits below,
3390 // hence the very simple code and heavy checks.
3393 // C++ defines default type casting from floating point to integer as
3394 // (close to) rounding toward zero ("fractional part discarded").
3396 int dst = instr->VFPDRegValue(kSinglePrecision);
3397 int src = instr->VFPMRegValue(src_precision);
3399 // Bit 7 in vcvt instructions indicates if we should use the FPSCR rounding
3400 // mode or the default Round to Zero mode.
3401 VFPRoundingMode mode = (instr->Bit(7) != 1) ? FPSCR_rounding_mode_
3403 DCHECK((mode == RM) || (mode == RZ) || (mode == RN));
3405 bool unsigned_integer = (instr->Bit(16) == 0);
3406 bool double_precision = (src_precision == kDoublePrecision);
3408 double val = double_precision ? get_double_from_d_register(src)
3409 : get_float_from_s_register(src);
3411 int temp = unsigned_integer ? static_cast<uint32_t>(val)
3412 : static_cast<int32_t>(val);
3414 inv_op_vfp_flag_ = get_inv_op_vfp_flag(mode, val, unsigned_integer);
3417 unsigned_integer ? std::fabs(val - static_cast<uint32_t>(temp))
3418 : std::fabs(val - temp);
3420 inexact_vfp_flag_ = (abs_diff != 0);
3422 if (inv_op_vfp_flag_) {
3423 temp = VFPConversionSaturate(val, unsigned_integer);
3427 int val_sign = (val > 0) ? 1 : -1;
3428 if (abs_diff > 0.5) {
3430 } else if (abs_diff == 0.5) {
3431 // Round to even if exactly halfway.
3432 temp = ((temp % 2) == 0) ? temp : temp + val_sign;
3438 temp = temp > val ? temp - 1 : temp;
3450 // Update the destination register.
3451 set_s_register_from_sinteger(dst, temp);
3454 bool unsigned_integer = (instr->Bit(7) == 0);
3456 int dst = instr->VFPDRegValue(src_precision);
3457 int src = instr->VFPMRegValue(kSinglePrecision);
3459 int val = get_sinteger_from_s_register(src);
3461 if (src_precision == kDoublePrecision) {
3462 if (unsigned_integer) {
3463 set_d_register_from_double(
3464 dst, static_cast<double>(static_cast<uint32_t>(val)));
3466 set_d_register_from_double(dst, static_cast<double>(val));
3469 if (unsigned_integer) {
3470 set_s_register_from_float(
3471 dst, static_cast<float>(static_cast<uint32_t>(val)));
3473 set_s_register_from_float(dst, static_cast<float>(val));
3480 // void Simulator::DecodeType6CoprocessorIns(Instruction* instr)
3481 // Decode Type 6 coprocessor instructions.
3482 // Dm = vmov(Rt, Rt2)
3483 // <Rt, Rt2> = vmov(Dm)
3484 // Ddst = MEM(Rbase + 4*offset).
3485 // MEM(Rbase + 4*offset) = Dsrc.
3486 void Simulator::DecodeType6CoprocessorIns(Instruction* instr) {
3487 DCHECK((instr->TypeValue() == 6));
3489 if (instr->CoprocessorValue() == 0xA) {
3490 switch (instr->OpcodeValue()) {
3494 case 0xE: { // Load and store single precision float to memory.
3495 int rn = instr->RnValue();
3496 int vd = instr->VFPDRegValue(kSinglePrecision);
3497 int offset = instr->Immed8Value();
3498 if (!instr->HasU()) {
3502 int32_t address = get_register(rn) + 4 * offset;
3503 if (instr->HasL()) {
3504 // Load double from memory: vldr.
3505 set_s_register_from_sinteger(vd, ReadW(address, instr));
3507 // Store double to memory: vstr.
3508 WriteW(address, get_sinteger_from_s_register(vd), instr);
3518 // Load/store multiple single from memory: vldm/vstm.
3522 UNIMPLEMENTED(); // Not used by V8.
3524 } else if (instr->CoprocessorValue() == 0xB) {
3525 switch (instr->OpcodeValue()) {
3527 // Load and store double to two GP registers
3528 if (instr->Bits(7, 6) != 0 || instr->Bit(4) != 1) {
3529 UNIMPLEMENTED(); // Not used by V8.
3531 int rt = instr->RtValue();
3532 int rn = instr->RnValue();
3533 int vm = instr->VFPMRegValue(kDoublePrecision);
3534 if (instr->HasL()) {
3536 get_d_register(vm, data);
3537 set_register(rt, data[0]);
3538 set_register(rn, data[1]);
3540 int32_t data[] = { get_register(rt), get_register(rn) };
3541 set_d_register(vm, reinterpret_cast<uint32_t*>(data));
3548 case 0xE: { // Load and store double to memory.
3549 int rn = instr->RnValue();
3550 int vd = instr->VFPDRegValue(kDoublePrecision);
3551 int offset = instr->Immed8Value();
3552 if (!instr->HasU()) {
3555 int32_t address = get_register(rn) + 4 * offset;
3556 if (instr->HasL()) {
3557 // Load double from memory: vldr.
3559 ReadW(address, instr),
3560 ReadW(address + 4, instr)
3562 set_d_register(vd, reinterpret_cast<uint32_t*>(data));
3564 // Store double to memory: vstr.
3566 get_d_register(vd, data);
3567 WriteW(address, data[0], instr);
3568 WriteW(address + 4, data[1], instr);
3578 // Load/store multiple double from memory: vldm/vstm.
3582 UNIMPLEMENTED(); // Not used by V8.
3585 UNIMPLEMENTED(); // Not used by V8.
3590 void Simulator::DecodeSpecialCondition(Instruction* instr) {
3591 switch (instr->SpecialValue()) {
3593 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
3594 (instr->Bit(4) == 1)) {
3596 if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
3597 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
3598 int Vm = (instr->Bit(5) << 4) | instr->VmValue();
3599 int imm3 = instr->Bits(21, 19);
3600 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
3601 int esize = 8 * imm3;
3602 int elements = 64 / esize;
3604 get_d_register(Vm, reinterpret_cast<uint64_t*>(from));
3607 while (e < elements) {
3611 set_q_register(Vd, reinterpret_cast<uint64_t*>(to));
3617 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
3618 (instr->Bit(4) == 1)) {
3620 if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
3621 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
3622 int Vm = (instr->Bit(5) << 4) | instr->VmValue();
3623 int imm3 = instr->Bits(21, 19);
3624 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED();
3625 int esize = 8 * imm3;
3626 int elements = 64 / esize;
3628 get_d_register(Vm, reinterpret_cast<uint64_t*>(from));
3631 while (e < elements) {
3635 set_q_register(Vd, reinterpret_cast<uint64_t*>(to));
3641 if (instr->Bits(21, 20) == 0) {
3643 int Vd = (instr->Bit(22) << 4) | instr->VdValue();
3644 int Rn = instr->VnValue();
3645 int type = instr->Bits(11, 8);
3646 int Rm = instr->VmValue();
3647 int32_t address = get_register(Rn);
3669 get_d_register(Vd + r, data);
3670 WriteW(address, data[0], instr);
3671 WriteW(address + 4, data[1], instr);
3677 set_register(Rn, address);
3679 set_register(Rn, get_register(Rn) + get_register(Rm));
3682 } else if (instr->Bits(21, 20) == 2) {
3684 int Vd = (instr->Bit(22) << 4) | instr->VdValue();
3685 int Rn = instr->VnValue();
3686 int type = instr->Bits(11, 8);
3687 int Rm = instr->VmValue();
3688 int32_t address = get_register(Rn);
3710 data[0] = ReadW(address, instr);
3711 data[1] = ReadW(address + 4, instr);
3712 set_d_register(Vd + r, data);
3718 set_register(Rn, address);
3720 set_register(Rn, get_register(Rn) + get_register(Rm));
3729 if ((instr->Bits(22, 20) == 5) && (instr->Bits(15, 12) == 0xf)) {
3730 // pld: ignore instruction.
3736 if (instr->Opc1Value() == 0x7 && instr->Opc3Value() == 0x1 &&
3737 instr->Bits(11, 9) == 0x5 && instr->Bits(19, 18) == 0x2 &&
3738 instr->Bit(8) == 0x1) {
3739 int vm = instr->VFPMRegValue(kDoublePrecision);
3740 int vd = instr->VFPDRegValue(kDoublePrecision);
3741 double dm_value = get_double_from_d_register(vm);
3742 double dd_value = 0.0;
3743 int rounding_mode = instr->Bits(17, 16);
3744 switch (rounding_mode) {
3745 case 0x0: // vrinta - round with ties to away from zero
3746 dd_value = round(dm_value);
3748 case 0x1: { // vrintn - round with ties to even
3749 dd_value = std::floor(dm_value);
3750 double error = dm_value - dd_value;
3751 // Take care of correctly handling the range [-0.5, -0.0], which
3753 if ((-0.5 <= dm_value) && (dm_value < 0.0)) {
3755 // If the error is greater than 0.5, or is equal to 0.5 and the
3756 // integer result is odd, round up.
3757 } else if ((error > 0.5) ||
3758 ((error == 0.5) && (fmod(dd_value, 2) != 0))) {
3763 case 0x2: // vrintp - ceil
3764 dd_value = std::ceil(dm_value);
3766 case 0x3: // vrintm - floor
3767 dd_value = std::floor(dm_value);
3770 UNREACHABLE(); // Case analysis is exhaustive.
3773 dd_value = canonicalizeNaN(dd_value);
3774 set_d_register_from_double(vd, dd_value);
3786 // Executes the current instruction.
3787 void Simulator::InstructionDecode(Instruction* instr) {
3788 if (v8::internal::FLAG_check_icache) {
3789 CheckICache(isolate_->simulator_i_cache(), instr);
3791 pc_modified_ = false;
3792 if (::v8::internal::FLAG_trace_sim) {
3793 disasm::NameConverter converter;
3794 disasm::Disassembler dasm(converter);
3795 // use a reasonably large buffer
3796 v8::internal::EmbeddedVector<char, 256> buffer;
3797 dasm.InstructionDecode(buffer,
3798 reinterpret_cast<byte*>(instr));
3799 PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr), buffer.start());
3801 if (instr->ConditionField() == kSpecialCondition) {
3802 DecodeSpecialCondition(instr);
3803 } else if (ConditionallyExecute(instr)) {
3804 switch (instr->TypeValue()) {
3807 DecodeType01(instr);
3839 // If the instruction is a non taken conditional stop, we need to skip the
3840 // inlined message address.
3841 } else if (instr->IsStop()) {
3842 set_pc(get_pc() + 2 * Instruction::kInstrSize);
3844 if (!pc_modified_) {
3845 set_register(pc, reinterpret_cast<int32_t>(instr)
3846 + Instruction::kInstrSize);
3851 void Simulator::Execute() {
3852 // Get the PC to simulate. Cannot use the accessor here as we need the
3853 // raw PC value and not the one used as input to arithmetic instructions.
3854 int program_counter = get_pc();
3856 if (::v8::internal::FLAG_stop_sim_at == 0) {
3857 // Fast version of the dispatch loop without checking whether the simulator
3858 // should be stopping at a particular executed instruction.
3859 while (program_counter != end_sim_pc) {
3860 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3862 InstructionDecode(instr);
3863 program_counter = get_pc();
3866 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
3867 // we reach the particular instuction count.
3868 while (program_counter != end_sim_pc) {
3869 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3871 if (icount_ == ::v8::internal::FLAG_stop_sim_at) {
3872 ArmDebugger dbg(this);
3875 InstructionDecode(instr);
3877 program_counter = get_pc();
3883 void Simulator::CallInternal(byte* entry) {
3884 // Prepare to execute the code at entry
3885 set_register(pc, reinterpret_cast<int32_t>(entry));
3886 // Put down marker for end of simulation. The simulator will stop simulation
3887 // when the PC reaches this value. By saving the "end simulation" value into
3888 // the LR the simulation stops when returning to this call point.
3889 set_register(lr, end_sim_pc);
3891 // Remember the values of callee-saved registers.
3892 // The code below assumes that r9 is not used as sb (static base) in
3893 // simulator code and therefore is regarded as a callee-saved register.
3894 int32_t r4_val = get_register(r4);
3895 int32_t r5_val = get_register(r5);
3896 int32_t r6_val = get_register(r6);
3897 int32_t r7_val = get_register(r7);
3898 int32_t r8_val = get_register(r8);
3899 int32_t r9_val = get_register(r9);
3900 int32_t r10_val = get_register(r10);
3901 int32_t r11_val = get_register(r11);
3903 // Set up the callee-saved registers with a known value. To be able to check
3904 // that they are preserved properly across JS execution.
3905 int32_t callee_saved_value = icount_;
3906 set_register(r4, callee_saved_value);
3907 set_register(r5, callee_saved_value);
3908 set_register(r6, callee_saved_value);
3909 set_register(r7, callee_saved_value);
3910 set_register(r8, callee_saved_value);
3911 set_register(r9, callee_saved_value);
3912 set_register(r10, callee_saved_value);
3913 set_register(r11, callee_saved_value);
3915 // Start the simulation
3918 // Check that the callee-saved registers have been preserved.
3919 CHECK_EQ(callee_saved_value, get_register(r4));
3920 CHECK_EQ(callee_saved_value, get_register(r5));
3921 CHECK_EQ(callee_saved_value, get_register(r6));
3922 CHECK_EQ(callee_saved_value, get_register(r7));
3923 CHECK_EQ(callee_saved_value, get_register(r8));
3924 CHECK_EQ(callee_saved_value, get_register(r9));
3925 CHECK_EQ(callee_saved_value, get_register(r10));
3926 CHECK_EQ(callee_saved_value, get_register(r11));
3928 // Restore callee-saved registers with the original value.
3929 set_register(r4, r4_val);
3930 set_register(r5, r5_val);
3931 set_register(r6, r6_val);
3932 set_register(r7, r7_val);
3933 set_register(r8, r8_val);
3934 set_register(r9, r9_val);
3935 set_register(r10, r10_val);
3936 set_register(r11, r11_val);
3940 int32_t Simulator::Call(byte* entry, int argument_count, ...) {
3942 va_start(parameters, argument_count);
3945 // First four arguments passed in registers.
3946 DCHECK(argument_count >= 4);
3947 set_register(r0, va_arg(parameters, int32_t));
3948 set_register(r1, va_arg(parameters, int32_t));
3949 set_register(r2, va_arg(parameters, int32_t));
3950 set_register(r3, va_arg(parameters, int32_t));
3952 // Remaining arguments passed on stack.
3953 int original_stack = get_register(sp);
3954 // Compute position of stack on entry to generated code.
3955 int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t));
3956 if (base::OS::ActivationFrameAlignment() != 0) {
3957 entry_stack &= -base::OS::ActivationFrameAlignment();
3959 // Store remaining arguments on stack, from low to high memory.
3960 intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack);
3961 for (int i = 4; i < argument_count; i++) {
3962 stack_argument[i - 4] = va_arg(parameters, int32_t);
3965 set_register(sp, entry_stack);
3967 CallInternal(entry);
3969 // Pop stack passed arguments.
3970 CHECK_EQ(entry_stack, get_register(sp));
3971 set_register(sp, original_stack);
3973 int32_t result = get_register(r0);
3978 void Simulator::CallFP(byte* entry, double d0, double d1) {
3979 if (use_eabi_hardfloat()) {
3980 set_d_register_from_double(0, d0);
3981 set_d_register_from_double(1, d1);
3983 set_register_pair_from_double(0, &d0);
3984 set_register_pair_from_double(2, &d1);
3986 CallInternal(entry);
3990 int32_t Simulator::CallFPReturnsInt(byte* entry, double d0, double d1) {
3991 CallFP(entry, d0, d1);
3992 int32_t result = get_register(r0);
3997 double Simulator::CallFPReturnsDouble(byte* entry, double d0, double d1) {
3998 CallFP(entry, d0, d1);
3999 if (use_eabi_hardfloat()) {
4000 return get_double_from_d_register(0);
4002 return get_double_from_register_pair(0);
4007 uintptr_t Simulator::PushAddress(uintptr_t address) {
4008 int new_sp = get_register(sp) - sizeof(uintptr_t);
4009 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
4010 *stack_slot = address;
4011 set_register(sp, new_sp);
4016 uintptr_t Simulator::PopAddress() {
4017 int current_sp = get_register(sp);
4018 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
4019 uintptr_t address = *stack_slot;
4020 set_register(sp, current_sp + sizeof(uintptr_t));
4024 } } // namespace v8::internal
4026 #endif // USE_SIMULATOR
4028 #endif // V8_TARGET_ARCH_ARM