deps/v8/src/arm/assembler-arm-inl.h

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  33 // The original source code covered by the above license above has been modified
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  35 // Copyright 2012 the V8 project authors. All rights reserved.
  36
  37 #ifndef V8_ARM_ASSEMBLER_ARM_INL_H_
  38 #define V8_ARM_ASSEMBLER_ARM_INL_H_
  39
  40 #include "src/arm/assembler-arm.h"
  41
  42 #include "src/assembler.h"
  43 #include "src/debug.h"
  44
  45
  46 namespace v8 {
  47 namespace internal {
  48
  49
  50 bool CpuFeatures::SupportsCrankshaft() { return IsSupported(VFP3); }
  51
  52
  53 int Register::NumAllocatableRegisters() {
  54   return kMaxNumAllocatableRegisters;
  55 }
  56
  57
  58 int DwVfpRegister::NumRegisters() {
  59   return CpuFeatures::IsSupported(VFP32DREGS) ? 32 : 16;
  60 }
  61
  62
  63 int DwVfpRegister::NumReservedRegisters() {
  64   return kNumReservedRegisters;
  65 }
  66
  67
  68 int DwVfpRegister::NumAllocatableRegisters() {
  69   return NumRegisters() - kNumReservedRegisters;
  70 }
  71
  72
  73 // static
  74 int DwVfpRegister::NumAllocatableAliasedRegisters() {
  75   return LowDwVfpRegister::kMaxNumLowRegisters - kNumReservedRegisters;
  76 }
  77
  78
  79 int DwVfpRegister::ToAllocationIndex(DwVfpRegister reg) {
  80   DCHECK(!reg.is(kDoubleRegZero));
  81   DCHECK(!reg.is(kScratchDoubleReg));
  82   if (reg.code() > kDoubleRegZero.code()) {
  83     return reg.code() - kNumReservedRegisters;
  84   }
  85   return reg.code();
  86 }
  87
  88
  89 DwVfpRegister DwVfpRegister::FromAllocationIndex(int index) {
  90   DCHECK(index >= 0 && index < NumAllocatableRegisters());
  91   DCHECK(kScratchDoubleReg.code() - kDoubleRegZero.code() ==
  92          kNumReservedRegisters - 1);
  93   if (index >= kDoubleRegZero.code()) {
  94     return from_code(index + kNumReservedRegisters);
  95   }
  96   return from_code(index);
  97 }
  98
  99
 100 void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) {
 101   if (RelocInfo::IsInternalReference(rmode_)) {
 102     // absolute code pointer inside code object moves with the code object.
 103     int32_t* p = reinterpret_cast<int32_t*>(pc_);
 104     *p += delta;  // relocate entry
 105   }
 106   // We do not use pc relative addressing on ARM, so there is
 107   // nothing else to do.
 108 }
 109
 110
 111 Address RelocInfo::target_address() {
 112   DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
 113   return Assembler::target_address_at(pc_, host_);
 114 }
 115
 116
 117 Address RelocInfo::target_address_address() {
 118   DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
 119                               || rmode_ == EMBEDDED_OBJECT
 120                               || rmode_ == EXTERNAL_REFERENCE);
 121   if (FLAG_enable_ool_constant_pool ||
 122       Assembler::IsMovW(Memory::int32_at(pc_))) {
 123     // We return the PC for ool constant pool since this function is used by the
 124     // serializerer and expects the address to reside within the code object.
 125     return reinterpret_cast<Address>(pc_);
 126   } else {
 127     DCHECK(Assembler::IsLdrPcImmediateOffset(Memory::int32_at(pc_)));
 128     return constant_pool_entry_address();
 129   }
 130 }
 131
 132
 133 Address RelocInfo::constant_pool_entry_address() {
 134   DCHECK(IsInConstantPool());
 135   return Assembler::constant_pool_entry_address(pc_, host_->constant_pool());
 136 }
 137
 138
 139 int RelocInfo::target_address_size() {
 140   return kPointerSize;
 141 }
 142
 143
 144 void RelocInfo::set_target_address(Address target,
 145                                    WriteBarrierMode write_barrier_mode,
 146                                    ICacheFlushMode icache_flush_mode) {
 147   DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
 148   Assembler::set_target_address_at(pc_, host_, target, icache_flush_mode);
 149   if (write_barrier_mode == UPDATE_WRITE_BARRIER &&
 150       host() != NULL && IsCodeTarget(rmode_)) {
 151     Object* target_code = Code::GetCodeFromTargetAddress(target);
 152     host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
 153         host(), this, HeapObject::cast(target_code));
 154   }
 155 }
 156
 157
 158 Object* RelocInfo::target_object() {
 159   DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
 160   return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_));
 161 }
 162
 163
 164 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
 165   DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
 166   return Handle<Object>(reinterpret_cast<Object**>(
 167       Assembler::target_address_at(pc_, host_)));
 168 }
 169
 170
 171 void RelocInfo::set_target_object(Object* target,
 172                                   WriteBarrierMode write_barrier_mode,
 173                                   ICacheFlushMode icache_flush_mode) {
 174   DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
 175   Assembler::set_target_address_at(pc_, host_,
 176                                    reinterpret_cast<Address>(target),
 177                                    icache_flush_mode);
 178   if (write_barrier_mode == UPDATE_WRITE_BARRIER &&
 179       host() != NULL &&
 180       target->IsHeapObject()) {
 181     host()->GetHeap()->incremental_marking()->RecordWrite(
 182         host(), &Memory::Object_at(pc_), HeapObject::cast(target));
 183   }
 184 }
 185
 186
 187 Address RelocInfo::target_reference() {
 188   DCHECK(rmode_ == EXTERNAL_REFERENCE);
 189   return Assembler::target_address_at(pc_, host_);
 190 }
 191
 192
 193 Address RelocInfo::target_runtime_entry(Assembler* origin) {
 194   DCHECK(IsRuntimeEntry(rmode_));
 195   return target_address();
 196 }
 197
 198
 199 void RelocInfo::set_target_runtime_entry(Address target,
 200                                          WriteBarrierMode write_barrier_mode,
 201                                          ICacheFlushMode icache_flush_mode) {
 202   DCHECK(IsRuntimeEntry(rmode_));
 203   if (target_address() != target)
 204     set_target_address(target, write_barrier_mode, icache_flush_mode);
 205 }
 206
 207
 208 Handle<Cell> RelocInfo::target_cell_handle() {
 209   DCHECK(rmode_ == RelocInfo::CELL);
 210   Address address = Memory::Address_at(pc_);
 211   return Handle<Cell>(reinterpret_cast<Cell**>(address));
 212 }
 213
 214
 215 Cell* RelocInfo::target_cell() {
 216   DCHECK(rmode_ == RelocInfo::CELL);
 217   return Cell::FromValueAddress(Memory::Address_at(pc_));
 218 }
 219
 220
 221 void RelocInfo::set_target_cell(Cell* cell,
 222                                 WriteBarrierMode write_barrier_mode,
 223                                 ICacheFlushMode icache_flush_mode) {
 224   DCHECK(rmode_ == RelocInfo::CELL);
 225   Address address = cell->address() + Cell::kValueOffset;
 226   Memory::Address_at(pc_) = address;
 227   if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL) {
 228     // TODO(1550) We are passing NULL as a slot because cell can never be on
 229     // evacuation candidate.
 230     host()->GetHeap()->incremental_marking()->RecordWrite(
 231         host(), NULL, cell);
 232   }
 233 }
 234
 235
 236 static const int kNoCodeAgeSequenceLength = 3 * Assembler::kInstrSize;
 237
 238
 239 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
 240   UNREACHABLE();  // This should never be reached on Arm.
 241   return Handle<Object>();
 242 }
 243
 244
 245 Code* RelocInfo::code_age_stub() {
 246   DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
 247   return Code::GetCodeFromTargetAddress(
 248       Memory::Address_at(pc_ +
 249                          (kNoCodeAgeSequenceLength - Assembler::kInstrSize)));
 250 }
 251
 252
 253 void RelocInfo::set_code_age_stub(Code* stub,
 254                                   ICacheFlushMode icache_flush_mode) {
 255   DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
 256   Memory::Address_at(pc_ +
 257                      (kNoCodeAgeSequenceLength - Assembler::kInstrSize)) =
 258       stub->instruction_start();
 259 }
 260
 261
 262 Address RelocInfo::call_address() {
 263   // The 2 instructions offset assumes patched debug break slot or return
 264   // sequence.
 265   DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
 266          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
 267   return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize);
 268 }
 269
 270
 271 void RelocInfo::set_call_address(Address target) {
 272   DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
 273          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
 274   Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target;
 275   if (host() != NULL) {
 276     Object* target_code = Code::GetCodeFromTargetAddress(target);
 277     host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
 278         host(), this, HeapObject::cast(target_code));
 279   }
 280 }
 281
 282
 283 Object* RelocInfo::call_object() {
 284   return *call_object_address();
 285 }
 286
 287
 288 void RelocInfo::set_call_object(Object* target) {
 289   *call_object_address() = target;
 290 }
 291
 292
 293 Object** RelocInfo::call_object_address() {
 294   DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
 295          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
 296   return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize);
 297 }
 298
 299
 300 void RelocInfo::WipeOut() {
 301   DCHECK(IsEmbeddedObject(rmode_) ||
 302          IsCodeTarget(rmode_) ||
 303          IsRuntimeEntry(rmode_) ||
 304          IsExternalReference(rmode_));
 305   Assembler::set_target_address_at(pc_, host_, NULL);
 306 }
 307
 308
 309 bool RelocInfo::IsPatchedReturnSequence() {
 310   Instr current_instr = Assembler::instr_at(pc_);
 311   Instr next_instr = Assembler::instr_at(pc_ + Assembler::kInstrSize);
 312   // A patched return sequence is:
 313   //  ldr ip, [pc, #0]
 314   //  blx ip
 315   return Assembler::IsLdrPcImmediateOffset(current_instr) &&
 316          Assembler::IsBlxReg(next_instr);
 317 }
 318
 319
 320 bool RelocInfo::IsPatchedDebugBreakSlotSequence() {
 321   Instr current_instr = Assembler::instr_at(pc_);
 322   return !Assembler::IsNop(current_instr, Assembler::DEBUG_BREAK_NOP);
 323 }
 324
 325
 326 void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
 327   RelocInfo::Mode mode = rmode();
 328   if (mode == RelocInfo::EMBEDDED_OBJECT) {
 329     visitor->VisitEmbeddedPointer(this);
 330   } else if (RelocInfo::IsCodeTarget(mode)) {
 331     visitor->VisitCodeTarget(this);
 332   } else if (mode == RelocInfo::CELL) {
 333     visitor->VisitCell(this);
 334   } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
 335     visitor->VisitExternalReference(this);
 336   } else if (RelocInfo::IsCodeAgeSequence(mode)) {
 337     visitor->VisitCodeAgeSequence(this);
 338   } else if (((RelocInfo::IsJSReturn(mode) &&
 339               IsPatchedReturnSequence()) ||
 340              (RelocInfo::IsDebugBreakSlot(mode) &&
 341               IsPatchedDebugBreakSlotSequence())) &&
 342              isolate->debug()->has_break_points()) {
 343     visitor->VisitDebugTarget(this);
 344   } else if (RelocInfo::IsRuntimeEntry(mode)) {
 345     visitor->VisitRuntimeEntry(this);
 346   }
 347 }
 348
 349
 350 template<typename StaticVisitor>
 351 void RelocInfo::Visit(Heap* heap) {
 352   RelocInfo::Mode mode = rmode();
 353   if (mode == RelocInfo::EMBEDDED_OBJECT) {
 354     StaticVisitor::VisitEmbeddedPointer(heap, this);
 355   } else if (RelocInfo::IsCodeTarget(mode)) {
 356     StaticVisitor::VisitCodeTarget(heap, this);
 357   } else if (mode == RelocInfo::CELL) {
 358     StaticVisitor::VisitCell(heap, this);
 359   } else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
 360     StaticVisitor::VisitExternalReference(this);
 361   } else if (RelocInfo::IsCodeAgeSequence(mode)) {
 362     StaticVisitor::VisitCodeAgeSequence(heap, this);
 363   } else if (heap->isolate()->debug()->has_break_points() &&
 364              ((RelocInfo::IsJSReturn(mode) &&
 365               IsPatchedReturnSequence()) ||
 366              (RelocInfo::IsDebugBreakSlot(mode) &&
 367               IsPatchedDebugBreakSlotSequence()))) {
 368     StaticVisitor::VisitDebugTarget(heap, this);
 369   } else if (RelocInfo::IsRuntimeEntry(mode)) {
 370     StaticVisitor::VisitRuntimeEntry(this);
 371   }
 372 }
 373
 374
 375 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode)  {
 376   rm_ = no_reg;
 377   imm32_ = immediate;
 378   rmode_ = rmode;
 379 }
 380
 381
 382 Operand::Operand(const ExternalReference& f)  {
 383   rm_ = no_reg;
 384   imm32_ = reinterpret_cast<int32_t>(f.address());
 385   rmode_ = RelocInfo::EXTERNAL_REFERENCE;
 386 }
 387
 388
 389 Operand::Operand(Smi* value) {
 390   rm_ = no_reg;
 391   imm32_ =  reinterpret_cast<intptr_t>(value);
 392   rmode_ = RelocInfo::NONE32;
 393 }
 394
 395
 396 Operand::Operand(Register rm) {
 397   rm_ = rm;
 398   rs_ = no_reg;
 399   shift_op_ = LSL;
 400   shift_imm_ = 0;
 401 }
 402
 403
 404 bool Operand::is_reg() const {
 405   return rm_.is_valid() &&
 406          rs_.is(no_reg) &&
 407          shift_op_ == LSL &&
 408          shift_imm_ == 0;
 409 }
 410
 411
 412 void Assembler::CheckBuffer() {
 413   if (buffer_space() <= kGap) {
 414     GrowBuffer();
 415   }
 416   if (pc_offset() >= next_buffer_check_) {
 417     CheckConstPool(false, true);
 418   }
 419 }
 420
 421
 422 void Assembler::emit(Instr x) {
 423   CheckBuffer();
 424   *reinterpret_cast<Instr*>(pc_) = x;
 425   pc_ += kInstrSize;
 426 }
 427
 428
 429 Address Assembler::target_address_from_return_address(Address pc) {
 430   // Returns the address of the call target from the return address that will
 431   // be returned to after a call.
 432   // Call sequence on V7 or later is:
 433   //  movw  ip, #... @ call address low 16
 434   //  movt  ip, #... @ call address high 16
 435   //  blx   ip
 436   //                      @ return address
 437   // For V6 when the constant pool is unavailable, it is:
 438   //  mov  ip, #...     @ call address low 8
 439   //  orr  ip, ip, #... @ call address 2nd 8
 440   //  orr  ip, ip, #... @ call address 3rd 8
 441   //  orr  ip, ip, #... @ call address high 8
 442   //  blx   ip
 443   //                      @ return address
 444   // In cases that need frequent patching, the address is in the
 445   // constant pool.  It could be a small constant pool load:
 446   //  ldr   ip, [pc / pp, #...] @ call address
 447   //  blx   ip
 448   //                      @ return address
 449   // Or an extended constant pool load (ARMv7):
 450   //  movw  ip, #...
 451   //  movt  ip, #...
 452   //  ldr   ip, [pc, ip]  @ call address
 453   //  blx   ip
 454   //                      @ return address
 455   // Or an extended constant pool load (ARMv6):
 456   //  mov  ip, #...
 457   //  orr  ip, ip, #...
 458   //  orr  ip, ip, #...
 459   //  orr  ip, ip, #...
 460   //  ldr   ip, [pc, ip]  @ call address
 461   //  blx   ip
 462   //                      @ return address
 463   Address candidate = pc - 2 * Assembler::kInstrSize;
 464   Instr candidate_instr(Memory::int32_at(candidate));
 465   if (IsLdrPcImmediateOffset(candidate_instr) |
 466       IsLdrPpImmediateOffset(candidate_instr)) {
 467     return candidate;
 468   } else {
 469     if (IsLdrPpRegOffset(candidate_instr)) {
 470       candidate -= Assembler::kInstrSize;
 471     }
 472     if (CpuFeatures::IsSupported(ARMv7)) {
 473       candidate -= 1 * Assembler::kInstrSize;
 474       DCHECK(IsMovW(Memory::int32_at(candidate)) &&
 475              IsMovT(Memory::int32_at(candidate + Assembler::kInstrSize)));
 476     } else {
 477       candidate -= 3 * Assembler::kInstrSize;
 478       DCHECK(
 479           IsMovImmed(Memory::int32_at(candidate)) &&
 480           IsOrrImmed(Memory::int32_at(candidate + Assembler::kInstrSize)) &&
 481           IsOrrImmed(Memory::int32_at(candidate + 2 * Assembler::kInstrSize)) &&
 482           IsOrrImmed(Memory::int32_at(candidate + 3 * Assembler::kInstrSize)));
 483     }
 484     return candidate;
 485   }
 486 }
 487
 488
 489 Address Assembler::break_address_from_return_address(Address pc) {
 490   return pc - Assembler::kPatchDebugBreakSlotReturnOffset;
 491 }
 492
 493
 494 Address Assembler::return_address_from_call_start(Address pc) {
 495   if (IsLdrPcImmediateOffset(Memory::int32_at(pc)) |
 496       IsLdrPpImmediateOffset(Memory::int32_at(pc))) {
 497     // Load from constant pool, small section.
 498     return pc + kInstrSize * 2;
 499   } else {
 500     if (CpuFeatures::IsSupported(ARMv7)) {
 501       DCHECK(IsMovW(Memory::int32_at(pc)));
 502       DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
 503       if (IsLdrPpRegOffset(Memory::int32_at(pc + 2 * kInstrSize))) {
 504         // Load from constant pool, extended section.
 505         return pc + kInstrSize * 4;
 506       } else {
 507         // A movw / movt load immediate.
 508         return pc + kInstrSize * 3;
 509       }
 510     } else {
 511       DCHECK(IsMovImmed(Memory::int32_at(pc)));
 512       DCHECK(IsOrrImmed(Memory::int32_at(pc + kInstrSize)));
 513       DCHECK(IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)));
 514       DCHECK(IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
 515       if (IsLdrPpRegOffset(Memory::int32_at(pc + 4 * kInstrSize))) {
 516         // Load from constant pool, extended section.
 517         return pc + kInstrSize * 6;
 518       } else {
 519         // A mov / orr load immediate.
 520         return pc + kInstrSize * 5;
 521       }
 522     }
 523   }
 524 }
 525
 526
 527 void Assembler::deserialization_set_special_target_at(
 528     Address constant_pool_entry, Code* code, Address target) {
 529   if (FLAG_enable_ool_constant_pool) {
 530     set_target_address_at(constant_pool_entry, code, target);
 531   } else {
 532     Memory::Address_at(constant_pool_entry) = target;
 533   }
 534 }
 535
 536
 537 bool Assembler::is_constant_pool_load(Address pc) {
 538   if (CpuFeatures::IsSupported(ARMv7)) {
 539     return !Assembler::IsMovW(Memory::int32_at(pc)) ||
 540            (FLAG_enable_ool_constant_pool &&
 541             Assembler::IsLdrPpRegOffset(
 542                 Memory::int32_at(pc + 2 * Assembler::kInstrSize)));
 543   } else {
 544     return !Assembler::IsMovImmed(Memory::int32_at(pc)) ||
 545            (FLAG_enable_ool_constant_pool &&
 546             Assembler::IsLdrPpRegOffset(
 547                 Memory::int32_at(pc + 4 * Assembler::kInstrSize)));
 548   }
 549 }
 550
 551
 552 Address Assembler::constant_pool_entry_address(
 553     Address pc, ConstantPoolArray* constant_pool) {
 554   if (FLAG_enable_ool_constant_pool) {
 555     DCHECK(constant_pool != NULL);
 556     int cp_offset;
 557     if (!CpuFeatures::IsSupported(ARMv7) && IsMovImmed(Memory::int32_at(pc))) {
 558       DCHECK(IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
 559              IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
 560              IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)) &&
 561              IsLdrPpRegOffset(Memory::int32_at(pc + 4 * kInstrSize)));
 562       // This is an extended constant pool lookup (ARMv6).
 563       Instr mov_instr = instr_at(pc);
 564       Instr orr_instr_1 = instr_at(pc + kInstrSize);
 565       Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
 566       Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize);
 567       cp_offset = DecodeShiftImm(mov_instr) | DecodeShiftImm(orr_instr_1) |
 568                   DecodeShiftImm(orr_instr_2) | DecodeShiftImm(orr_instr_3);
 569     } else if (IsMovW(Memory::int32_at(pc))) {
 570       DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)) &&
 571              IsLdrPpRegOffset(Memory::int32_at(pc + 2 * kInstrSize)));
 572       // This is an extended constant pool lookup (ARMv7).
 573       Instruction* movw_instr = Instruction::At(pc);
 574       Instruction* movt_instr = Instruction::At(pc + kInstrSize);
 575       cp_offset = (movt_instr->ImmedMovwMovtValue() << 16) |
 576                   movw_instr->ImmedMovwMovtValue();
 577     } else {
 578       // This is a small constant pool lookup.
 579       DCHECK(Assembler::IsLdrPpImmediateOffset(Memory::int32_at(pc)));
 580       cp_offset = GetLdrRegisterImmediateOffset(Memory::int32_at(pc));
 581     }
 582     return reinterpret_cast<Address>(constant_pool) + cp_offset;
 583   } else {
 584     DCHECK(Assembler::IsLdrPcImmediateOffset(Memory::int32_at(pc)));
 585     Instr instr = Memory::int32_at(pc);
 586     return pc + GetLdrRegisterImmediateOffset(instr) + kPcLoadDelta;
 587   }
 588 }
 589
 590
 591 Address Assembler::target_address_at(Address pc,
 592                                      ConstantPoolArray* constant_pool) {
 593   if (is_constant_pool_load(pc)) {
 594     // This is a constant pool lookup. Return the value in the constant pool.
 595     return Memory::Address_at(constant_pool_entry_address(pc, constant_pool));
 596   } else if (CpuFeatures::IsSupported(ARMv7)) {
 597     // This is an movw / movt immediate load. Return the immediate.
 598     DCHECK(IsMovW(Memory::int32_at(pc)) &&
 599            IsMovT(Memory::int32_at(pc + kInstrSize)));
 600     Instruction* movw_instr = Instruction::At(pc);
 601     Instruction* movt_instr = Instruction::At(pc + kInstrSize);
 602     return reinterpret_cast<Address>(
 603         (movt_instr->ImmedMovwMovtValue() << 16) |
 604          movw_instr->ImmedMovwMovtValue());
 605   } else {
 606     // This is an mov / orr immediate load. Return the immediate.
 607     DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
 608            IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
 609            IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
 610            IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
 611     Instr mov_instr = instr_at(pc);
 612     Instr orr_instr_1 = instr_at(pc + kInstrSize);
 613     Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
 614     Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize);
 615     Address ret = reinterpret_cast<Address>(
 616         DecodeShiftImm(mov_instr) | DecodeShiftImm(orr_instr_1) |
 617         DecodeShiftImm(orr_instr_2) | DecodeShiftImm(orr_instr_3));
 618     return ret;
 619   }
 620 }
 621
 622
 623 void Assembler::set_target_address_at(Address pc,
 624                                       ConstantPoolArray* constant_pool,
 625                                       Address target,
 626                                       ICacheFlushMode icache_flush_mode) {
 627   if (is_constant_pool_load(pc)) {
 628     // This is a constant pool lookup. Update the entry in the constant pool.
 629     Memory::Address_at(constant_pool_entry_address(pc, constant_pool)) = target;
 630     // Intuitively, we would think it is necessary to always flush the
 631     // instruction cache after patching a target address in the code as follows:
 632     //   CpuFeatures::FlushICache(pc, sizeof(target));
 633     // However, on ARM, no instruction is actually patched in the case
 634     // of embedded constants of the form:
 635     // ldr   ip, [pp, #...]
 636     // since the instruction accessing this address in the constant pool remains
 637     // unchanged.
 638   } else if (CpuFeatures::IsSupported(ARMv7)) {
 639     // This is an movw / movt immediate load. Patch the immediate embedded in
 640     // the instructions.
 641     DCHECK(IsMovW(Memory::int32_at(pc)));
 642     DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
 643     uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
 644     uint32_t immediate = reinterpret_cast<uint32_t>(target);
 645     instr_ptr[0] = PatchMovwImmediate(instr_ptr[0], immediate & 0xFFFF);
 646     instr_ptr[1] = PatchMovwImmediate(instr_ptr[1], immediate >> 16);
 647     DCHECK(IsMovW(Memory::int32_at(pc)));
 648     DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
 649     if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
 650       CpuFeatures::FlushICache(pc, 2 * kInstrSize);
 651     }
 652   } else {
 653     // This is an mov / orr immediate load. Patch the immediate embedded in
 654     // the instructions.
 655     DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
 656            IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
 657            IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
 658            IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
 659     uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
 660     uint32_t immediate = reinterpret_cast<uint32_t>(target);
 661     instr_ptr[0] = PatchShiftImm(instr_ptr[0], immediate & kImm8Mask);
 662     instr_ptr[1] = PatchShiftImm(instr_ptr[1], immediate & (kImm8Mask << 8));
 663     instr_ptr[2] = PatchShiftImm(instr_ptr[2], immediate & (kImm8Mask << 16));
 664     instr_ptr[3] = PatchShiftImm(instr_ptr[3], immediate & (kImm8Mask << 24));
 665     DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
 666            IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
 667            IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
 668            IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
 669     if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
 670       CpuFeatures::FlushICache(pc, 4 * kInstrSize);
 671     }
 672   }
 673 }
 674
 675
 676 } }  // namespace v8::internal
 677
 678 #endif  // V8_ARM_ASSEMBLER_ARM_INL_H_