1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
44 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
45 #define CORE_HASWELL CORE_NEHALEM
46 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
47 #define CORE_SANDYBRIDGE CORE_NEHALEM
48 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
49 #define CORE_BULLDOZER CORE_BARCELONA
54 #if defined(__APPLE__) && defined(__i386__)
55 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
57 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
59 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
67 unsigned int id, a, b, c, d;
76 extern idlist_t idlist[];
77 extern vendor_t vendor[];
79 static int cv = VENDOR;
81 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
83 static int current = 0;
85 int start = vendor[cv].start;
86 int stop = vendor[cv].stop;
87 int count = stop - start;
89 if ((current < start) || (current > stop)) current = start;
91 while ((count > 0) && (idlist[current].id != op)) {
94 if (current > stop) current = start;
99 *eax = idlist[current].a;
100 *ebx = idlist[current].b;
101 *ecx = idlist[current].c;
102 *edx = idlist[current].d;
107 static inline int have_cpuid(void){
108 int eax, ebx, ecx, edx;
110 cpuid(0, &eax, &ebx, &ecx, &edx);
114 static inline int have_excpuid(void){
115 int eax, ebx, ecx, edx;
117 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
122 static inline void xgetbv(int op, int * eax, int * edx){
123 //Use binary code for xgetbv
125 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
131 int eax, ebx, ecx, edx;
134 cpuid(1, &eax, &ebx, &ecx, &edx);
135 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
136 xgetbv(0, &eax, &edx);
138 ret=1; //OS support AVX
148 int get_vendor(void){
149 int eax, ebx, ecx, edx;
152 cpuid(0, &eax, &ebx, &ecx, &edx);
154 *(int *)(&vendor[0]) = ebx;
155 *(int *)(&vendor[4]) = edx;
156 *(int *)(&vendor[8]) = ecx;
157 vendor[12] = (char)0;
159 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
160 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
161 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
162 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
163 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
164 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
165 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
166 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
167 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
168 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
170 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
172 return VENDOR_UNKNOWN;
175 int get_cputype(int gettype){
176 int eax, ebx, ecx, edx;
177 int extend_family, family;
178 int extend_model, model;
182 cpuid(1, &eax, &ebx, &ecx, &edx);
186 return BITMASK(eax, 20, 0xff);
188 return BITMASK(eax, 16, 0x0f);
190 return BITMASK(eax, 12, 0x03);
192 return BITMASK(eax, 8, 0x0f);
194 return BITMASK(eax, 4, 0x0f);
196 return BITMASK(ebx, 24, 0x0f);
198 return BITMASK(ebx, 16, 0x0f);
200 return BITMASK(ebx, 8, 0x0f);
202 return BITMASK(eax, 0, 0x0f);
204 return BITMASK(ebx, 0, 0xff);
206 if (have_cpuid() < 4) return 0;
207 cpuid(4, &eax, &ebx, &ecx, &edx);
208 return BITMASK(eax, 14, 0xfff);
210 if (have_cpuid() < 4) return 0;
211 cpuid(4, &eax, &ebx, &ecx, &edx);
212 return BITMASK(eax, 26, 0x3f);
215 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
216 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
217 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
218 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
219 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
220 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
221 if ((edx & (1 << 27)) != 0) {
222 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
224 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
225 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
226 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
227 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
229 if (support_avx()) feature |= HAVE_AVX;
232 if (have_excpuid() >= 0x01) {
233 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
234 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
235 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
237 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
239 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
240 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
243 if (have_excpuid() >= 0x1a) {
244 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
245 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
246 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
253 int get_cacheinfo(int type, cache_info_t *cacheinfo){
254 int eax, ebx, ecx, edx, cpuid_level;
257 cache_info_t LC1, LD1, L2, L3,
258 ITB, DTB, LITB, LDTB,
259 L2ITB, L2DTB, L2LITB, L2LDTB;
261 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
262 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
263 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
264 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
265 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
266 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
267 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
268 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
269 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
270 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
271 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
272 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
274 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
276 if (cpuid_level > 1) {
278 cpuid(2, &eax, &ebx, &ecx, &edx);
280 info[ 0] = BITMASK(eax, 8, 0xff);
281 info[ 1] = BITMASK(eax, 16, 0xff);
282 info[ 2] = BITMASK(eax, 24, 0xff);
284 info[ 3] = BITMASK(ebx, 0, 0xff);
285 info[ 4] = BITMASK(ebx, 8, 0xff);
286 info[ 5] = BITMASK(ebx, 16, 0xff);
287 info[ 6] = BITMASK(ebx, 24, 0xff);
289 info[ 7] = BITMASK(ecx, 0, 0xff);
290 info[ 8] = BITMASK(ecx, 8, 0xff);
291 info[ 9] = BITMASK(ecx, 16, 0xff);
292 info[10] = BITMASK(ecx, 24, 0xff);
294 info[11] = BITMASK(edx, 0, 0xff);
295 info[12] = BITMASK(edx, 8, 0xff);
296 info[13] = BITMASK(edx, 16, 0xff);
297 info[14] = BITMASK(edx, 24, 0xff);
299 for (i = 0; i < 15; i++){
303 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
312 LITB.associative = 0;
322 LDTB.associative = 4;
327 LDTB.associative = 4;
486 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
531 LITB.associative = 0;
540 LITB.associative = 0;
549 LITB.associative = 0;
555 LITB.associative = 0;
561 LDTB.associative = 4;
566 LDTB.associative = 4;
574 LDTB.associative = 0;
583 LDTB.associative = 0;
592 LDTB.associative = 0;
744 L2DTB.associative = 0;
754 LITB.associative = 4;
841 if (get_vendor() == VENDOR_INTEL) {
842 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
843 if (cpuid_level >= 0x80000006) {
844 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
846 L2.size = BITMASK(ecx, 16, 0xffff);
847 L2.associative = BITMASK(ecx, 12, 0x0f);
848 L2.linesize = BITMASK(ecx, 0, 0xff);
852 if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
853 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
856 LDTB.associative = BITMASK(eax, 24, 0xff);
857 if (LDTB.associative == 0xff) LDTB.associative = 0;
858 LDTB.linesize = BITMASK(eax, 16, 0xff);
861 LITB.associative = BITMASK(eax, 8, 0xff);
862 if (LITB.associative == 0xff) LITB.associative = 0;
863 LITB.linesize = BITMASK(eax, 0, 0xff);
866 DTB.associative = BITMASK(ebx, 24, 0xff);
867 if (DTB.associative == 0xff) DTB.associative = 0;
868 DTB.linesize = BITMASK(ebx, 16, 0xff);
871 ITB.associative = BITMASK(ebx, 8, 0xff);
872 if (ITB.associative == 0xff) ITB.associative = 0;
873 ITB.linesize = BITMASK(ebx, 0, 0xff);
875 LD1.size = BITMASK(ecx, 24, 0xff);
876 LD1.associative = BITMASK(ecx, 16, 0xff);
877 if (LD1.associative == 0xff) LD1.associative = 0;
878 LD1.linesize = BITMASK(ecx, 0, 0xff);
880 LC1.size = BITMASK(ecx, 24, 0xff);
881 LC1.associative = BITMASK(ecx, 16, 0xff);
882 if (LC1.associative == 0xff) LC1.associative = 0;
883 LC1.linesize = BITMASK(ecx, 0, 0xff);
885 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
888 L2LDTB.associative = BITMASK(eax, 24, 0xff);
889 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
890 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
893 L2LITB.associative = BITMASK(eax, 8, 0xff);
894 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
895 L2LITB.linesize = BITMASK(eax, 0, 0xff);
898 L2DTB.associative = BITMASK(ebx, 24, 0xff);
899 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
900 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
903 L2ITB.associative = BITMASK(ebx, 8, 0xff);
904 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
905 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
907 L2.size = BITMASK(ecx, 16, 0xffff);
908 L2.associative = BITMASK(ecx, 12, 0xf);
909 if (L2.associative == 0xff) L2.associative = 0;
910 L2.linesize = BITMASK(ecx, 0, 0xff);
912 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
913 L3.associative = BITMASK(edx, 12, 0xf);
914 if (L3.associative == 0xff) L2.associative = 0;
915 L3.linesize = BITMASK(edx, 0, 0xff);
921 case CACHE_INFO_L1_I :
924 case CACHE_INFO_L1_D :
933 case CACHE_INFO_L1_DTB :
936 case CACHE_INFO_L1_ITB :
939 case CACHE_INFO_L1_LDTB :
942 case CACHE_INFO_L1_LITB :
945 case CACHE_INFO_L2_DTB :
948 case CACHE_INFO_L2_ITB :
951 case CACHE_INFO_L2_LDTB :
954 case CACHE_INFO_L2_LITB :
961 int get_cpuname(void){
963 int family, exfamily, model, vendor, exmodel;
965 if (!have_cpuid()) return CPUTYPE_80386;
967 family = get_cputype(GET_FAMILY);
968 exfamily = get_cputype(GET_EXFAMILY);
969 model = get_cputype(GET_MODEL);
970 exmodel = get_cputype(GET_EXMODEL);
972 vendor = get_vendor();
974 if (vendor == VENDOR_INTEL){
977 return CPUTYPE_80486;
979 return CPUTYPE_PENTIUM;
988 return CPUTYPE_PENTIUM2;
993 return CPUTYPE_PENTIUM3;
997 return CPUTYPE_PENTIUMM;
999 return CPUTYPE_CORE2;
1005 return CPUTYPE_CORE2;
1007 return CPUTYPE_PENRYN;
1012 return CPUTYPE_NEHALEM;
1014 return CPUTYPE_ATOM;
1016 return CPUTYPE_DUNNINGTON;
1022 //Intel Core (Clarkdale) / Core (Arrandale)
1023 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1024 // Xeon (Clarkdale), 32nm
1025 return CPUTYPE_NEHALEM;
1027 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1029 return CPUTYPE_SANDYBRIDGE;
1031 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1033 //Xeon Processor 5600 (Westmere-EP)
1034 return CPUTYPE_NEHALEM;
1036 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1038 return CPUTYPE_SANDYBRIDGE;
1040 return CPUTYPE_NEHALEM;
1044 //Xeon Processor E7 (Westmere-EX)
1045 return CPUTYPE_NEHALEM;
1052 return CPUTYPE_SANDYBRIDGE;
1054 return CPUTYPE_NEHALEM;
1057 return CPUTYPE_HASWELL;
1059 return CPUTYPE_NEHALEM;
1066 return CPUTYPE_HASWELL;
1068 return CPUTYPE_NEHALEM;
1074 return CPUTYPE_ITANIUM;
1078 return CPUTYPE_PENTIUM4;
1080 return CPUTYPE_ITANIUM;
1084 return CPUTYPE_INTEL_UNKNOWN;
1087 if (vendor == VENDOR_AMD){
1090 return CPUTYPE_AMD5X86;
1092 return CPUTYPE_AMDK6;
1094 return CPUTYPE_ATHLON;
1099 return CPUTYPE_OPTERON;
1102 return CPUTYPE_BARCELONA;
1103 case 6: //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1105 return CPUTYPE_BULLDOZER;
1107 return CPUTYPE_BARCELONA; //OS don't support AVX.
1109 return CPUTYPE_BOBCAT;
1113 return CPUTYPE_AMD_UNKNOWN;
1116 if (vendor == VENDOR_CYRIX){
1119 return CPUTYPE_CYRIX5X86;
1121 return CPUTYPE_CYRIXM1;
1123 return CPUTYPE_CYRIXM2;
1125 return CPUTYPE_CYRIX_UNKNOWN;
1128 if (vendor == VENDOR_NEXGEN){
1131 return CPUTYPE_NEXGENNX586;
1133 return CPUTYPE_NEXGEN_UNKNOWN;
1136 if (vendor == VENDOR_CENTAUR){
1139 return CPUTYPE_CENTAURC6;
1142 return CPUTYPE_NANO;
1146 return CPUTYPE_VIAC3;
1149 if (vendor == VENDOR_RISE){
1152 return CPUTYPE_RISEMP6;
1154 return CPUTYPE_RISE_UNKNOWN;
1157 if (vendor == VENDOR_SIS){
1160 return CPUTYPE_SYS55X;
1162 return CPUTYPE_SIS_UNKNOWN;
1165 if (vendor == VENDOR_TRANSMETA){
1168 return CPUTYPE_CRUSOETM3X;
1170 return CPUTYPE_TRANSMETA_UNKNOWN;
1173 if (vendor == VENDOR_NSC){
1176 return CPUTYPE_NSGEODE;
1178 return CPUTYPE_NSC_UNKNOWN;
1181 return CPUTYPE_UNKNOWN;
1184 static char *cpuname[] = {
1194 "TRANSMETA_UNKNOWN",
1234 static char *lowercpuname[] = {
1244 "transmeta_unknown",
1283 static char *corename[] = {
1309 static char *corename_lower[] = {
1336 char *get_cpunamechar(void){
1337 return cpuname[get_cpuname()];
1340 char *get_lower_cpunamechar(void){
1341 return lowercpuname[get_cpuname()];
1345 int get_coretype(void){
1347 int family, exfamily, model, exmodel, vendor;
1349 if (!have_cpuid()) return CORE_80486;
1351 family = get_cputype(GET_FAMILY);
1352 exfamily = get_cputype(GET_EXFAMILY);
1353 model = get_cputype(GET_MODEL);
1354 exmodel = get_cputype(GET_EXMODEL);
1356 vendor = get_vendor();
1358 if (vendor == VENDOR_INTEL){
1381 return CORE_COPPERMINE;
1400 return CORE_NEHALEM;
1404 return CORE_DUNNINGTON;
1410 //Intel Core (Clarkdale) / Core (Arrandale)
1411 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1412 // Xeon (Clarkdale), 32nm
1413 return CORE_NEHALEM;
1415 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1417 return CORE_SANDYBRIDGE;
1419 return CORE_NEHALEM; //OS doesn't support AVX
1421 //Xeon Processor 5600 (Westmere-EP)
1422 return CORE_NEHALEM;
1424 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1426 return CORE_SANDYBRIDGE;
1428 return CORE_NEHALEM; //OS doesn't support AVX
1432 //Xeon Processor E7 (Westmere-EX)
1433 return CORE_NEHALEM;
1440 return CORE_SANDYBRIDGE;
1442 return CORE_NEHALEM; //OS doesn't support AVX
1445 return CORE_HASWELL;
1447 return CORE_NEHALEM;
1454 return CORE_HASWELL;
1456 return CORE_NEHALEM;
1463 if (model <= 0x2) return CORE_NORTHWOOD;
1464 else return CORE_PRESCOTT;
1468 if (vendor == VENDOR_AMD){
1469 if (family <= 0x5) return CORE_80486;
1470 if (family <= 0xe) return CORE_ATHLON;
1472 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
1473 else if (exfamily == 5) return CORE_BOBCAT;
1474 else if (exfamily == 6) {
1475 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1477 return CORE_BULLDOZER;
1479 return CORE_BARCELONA; //OS don't support AVX. Use old kernels.
1480 }else return CORE_BARCELONA;
1484 if (vendor == VENDOR_CENTAUR) {
1493 return CORE_UNKNOWN;
1496 void get_cpuconfig(void){
1501 printf("#define %s\n", cpuname[get_cpuname()]);
1504 if (get_coretype() != CORE_P5) {
1506 get_cacheinfo(CACHE_INFO_L1_I, &info);
1507 if (info.size > 0) {
1508 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
1509 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
1510 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
1513 get_cacheinfo(CACHE_INFO_L1_D, &info);
1514 if (info.size > 0) {
1515 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
1516 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
1517 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
1520 get_cacheinfo(CACHE_INFO_L2, &info);
1521 if (info.size > 0) {
1522 printf("#define L2_SIZE %d\n", info.size * 1024);
1523 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
1524 printf("#define L2_LINESIZE %d\n", info.linesize);
1527 get_cacheinfo(CACHE_INFO_L3, &info);
1528 if (info.size > 0) {
1529 printf("#define L3_SIZE %d\n", info.size * 1024);
1530 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
1531 printf("#define L3_LINESIZE %d\n", info.linesize);
1534 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
1535 if (info.size > 0) {
1536 printf("#define ITB_SIZE %d\n", info.size * 1024);
1537 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
1538 printf("#define ITB_ENTRIES %d\n", info.linesize);
1541 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
1542 if (info.size > 0) {
1543 printf("#define DTB_SIZE %d\n", info.size * 1024);
1544 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
1545 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
1547 //fall back for some virtual machines.
1548 printf("#define DTB_DEFAULT_ENTRIES 32\n");
1551 features = get_cputype(GET_FEATURE);
1553 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
1554 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
1555 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
1556 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
1557 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
1558 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
1559 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
1560 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
1561 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
1562 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
1563 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
1564 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
1565 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
1566 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
1567 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
1568 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
1569 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
1570 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
1571 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
1573 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
1574 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
1576 features = get_coretype();
1577 if (features > 0) printf("#define CORE_%s\n", corename[features]);
1579 printf("#define DTB_DEFAULT_ENTRIES 16\n");
1580 printf("#define L1_CODE_SIZE 8192\n");
1581 printf("#define L1_DATA_SIZE 8192\n");
1582 printf("#define L2_SIZE 0\n");
1586 void get_architecture(void){
1594 void get_subarchitecture(void){
1595 printf("%s", get_cpunamechar());
1598 void get_subdirname(void){
1606 char *get_corename(void){
1607 return corename[get_coretype()];
1610 void get_libname(void){
1611 printf("%s", corename_lower[get_coretype()]);
1614 /* This if for Makefile */
1619 features = get_cputype(GET_FEATURE);
1621 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
1622 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
1623 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
1624 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
1625 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
1626 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
1627 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
1628 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
1629 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
1630 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
1631 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
1632 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
1633 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");