1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
43 #if defined(_MSC_VER) && !defined(__clang__)
44 #define C_INLINE __inline
46 #define C_INLINE inline
51 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
52 #define CORE_HASWELL CORE_NEHALEM
53 #define CPUTYPE_SKYLAKEX CPUTYPE_NEHALEM
54 #define CORE_SKYLAKEX CORE_NEHALEM
55 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
56 #define CORE_SANDYBRIDGE CORE_NEHALEM
57 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
58 #define CORE_BULLDOZER CORE_BARCELONA
59 #define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
60 #define CORE_PILEDRIVER CORE_BARCELONA
64 #if defined(_MSC_VER) && !defined(__clang__)
66 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
68 int cpuInfo[4] = {-1};
76 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx)
78 int cpuInfo[4] = {-1};
79 __cpuidex(cpuInfo, op, count);
90 #if defined(__APPLE__) && defined(__i386__)
91 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
92 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx);
94 static C_INLINE void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
95 #if defined(__i386__) && defined(__PIC__)
100 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op), "c" (0) : "cc");
103 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) , "c" (0) : "cc");
107 static C_INLINE void cpuid_count(int op, int count ,int *eax, int *ebx, int *ecx, int *edx){
108 #if defined(__i386__) && defined(__PIC__)
112 "xchgl %%ebx, %%edi;"
113 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
116 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
124 unsigned int id, a, b, c, d;
133 extern idlist_t idlist[];
134 extern vendor_t vendor[];
136 static int cv = VENDOR;
138 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
140 static int current = 0;
142 int start = vendor[cv].start;
143 int stop = vendor[cv].stop;
144 int count = stop - start;
146 if ((current < start) || (current > stop)) current = start;
148 while ((count > 0) && (idlist[current].id != op)) {
151 if (current > stop) current = start;
156 *eax = idlist[current].a;
157 *ebx = idlist[current].b;
158 *ecx = idlist[current].c;
159 *edx = idlist[current].d;
162 void cpuid_count (unsigned int op, unsigned int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
163 return cpuid (op, eax, ebx, ecx, edx);
170 static C_INLINE int have_cpuid(void){
171 int eax, ebx, ecx, edx;
173 cpuid(0, &eax, &ebx, &ecx, &edx);
177 static C_INLINE int have_excpuid(void){
178 int eax, ebx, ecx, edx;
180 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
185 static C_INLINE void xgetbv(int op, int * eax, int * edx){
186 //Use binary code for xgetbv
187 #if defined(_MSC_VER) && !defined(__clang__)
191 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
198 int eax, ebx, ecx, edx;
201 cpuid(1, &eax, &ebx, &ecx, &edx);
202 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
203 xgetbv(0, &eax, &edx);
205 ret=1; //OS supports saving xmm and ymm registers (6 = (1<<1) | (1<<2))
216 int eax, ebx, ecx=0, edx;
221 cpuid(7, &eax, &ebx, &ecx, &edx);
222 if((ebx & (1<<5)) != 0)
223 ret=1; //CPU supports AVX2
230 int support_avx512(){
231 #if !defined(NO_AVX) && !defined(NO_AVX512)
232 int eax, ebx, ecx, edx;
237 cpuid(7, &eax, &ebx, &ecx, &edx);
238 if((ebx & (1<<5)) == 0){
239 ret=0; //cpu does not have avx2 flag
241 if((ebx & (1<<31)) != 0){ //AVX512VL flag
242 xgetbv(0, &eax, &edx);
243 if((eax & 0xe0) == 0xe0)
244 ret=1; //OS supports saving zmm registers
252 int support_avx512_bf16(){
253 #if !defined(NO_AVX) && !defined(NO_AVX512)
254 int eax, ebx, ecx, edx;
257 if (!support_avx512())
259 cpuid_count(7, 1, &eax, &ebx, &ecx, &edx);
260 if((eax & 32) == 32){
261 ret=1; // CPUID.7.1:EAX[bit 5] indicates whether avx512_bf16 supported or not
269 int get_vendor(void){
270 int eax, ebx, ecx, edx;
273 cpuid(0, &eax, &ebx, &ecx, &edx);
275 *(int *)(&vendor[0]) = ebx;
276 *(int *)(&vendor[4]) = edx;
277 *(int *)(&vendor[8]) = ecx;
278 vendor[12] = (char)0;
280 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
281 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
282 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
283 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
284 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
285 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
286 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
287 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
288 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
289 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
290 if (!strcmp(vendor, "HygonGenuine")) return VENDOR_HYGON;
292 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
294 return VENDOR_UNKNOWN;
297 int get_cputype(int gettype){
298 int eax, ebx, ecx, edx;
299 int extend_family, family;
300 int extend_model, model;
304 cpuid(1, &eax, &ebx, &ecx, &edx);
308 return BITMASK(eax, 20, 0xff);
310 return BITMASK(eax, 16, 0x0f);
312 return BITMASK(eax, 12, 0x03);
314 return BITMASK(eax, 8, 0x0f);
316 return BITMASK(eax, 4, 0x0f);
318 return BITMASK(ebx, 24, 0x0f);
320 return BITMASK(ebx, 16, 0x0f);
322 return BITMASK(ebx, 8, 0x0f);
324 return BITMASK(eax, 0, 0x0f);
326 return BITMASK(ebx, 0, 0xff);
328 if (have_cpuid() < 4) return 0;
329 cpuid(4, &eax, &ebx, &ecx, &edx);
330 return BITMASK(eax, 14, 0xfff);
332 if (have_cpuid() < 4) return 0;
333 cpuid(4, &eax, &ebx, &ecx, &edx);
334 return BITMASK(eax, 26, 0x3f);
337 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
338 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
339 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
340 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
341 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
342 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
343 if ((edx & (1 << 27)) != 0) {
344 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
346 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
347 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
348 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
349 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
351 if (support_avx()) feature |= HAVE_AVX;
352 if (support_avx2()) feature |= HAVE_AVX2;
353 if (support_avx512()) feature |= HAVE_AVX512VL;
354 if (support_avx512_bf16()) feature |= HAVE_AVX512BF16;
355 if ((ecx & (1 << 12)) != 0) feature |= HAVE_FMA3;
358 if (have_excpuid() >= 0x01) {
359 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
360 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
361 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
363 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
365 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
366 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
369 if (have_excpuid() >= 0x1a) {
370 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
371 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
372 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
379 int get_cacheinfo(int type, cache_info_t *cacheinfo){
380 int eax, ebx, ecx, edx, cpuid_level;
383 cache_info_t LC1, LD1, L2, L3,
384 ITB, DTB, LITB, LDTB,
385 L2ITB, L2DTB, L2LITB, L2LDTB;
387 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
388 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
389 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
390 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
391 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
392 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
393 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
394 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
395 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
396 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
397 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
398 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
400 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
402 if (cpuid_level > 1) {
404 cpuid(2, &eax, &ebx, &ecx, &edx);
405 numcalls = BITMASK(eax, 0, 0xff); //FIXME some systems may require repeated calls to read all entries
406 info[ 0] = BITMASK(eax, 8, 0xff);
407 info[ 1] = BITMASK(eax, 16, 0xff);
408 info[ 2] = BITMASK(eax, 24, 0xff);
410 info[ 3] = BITMASK(ebx, 0, 0xff);
411 info[ 4] = BITMASK(ebx, 8, 0xff);
412 info[ 5] = BITMASK(ebx, 16, 0xff);
413 info[ 6] = BITMASK(ebx, 24, 0xff);
415 info[ 7] = BITMASK(ecx, 0, 0xff);
416 info[ 8] = BITMASK(ecx, 8, 0xff);
417 info[ 9] = BITMASK(ecx, 16, 0xff);
418 info[10] = BITMASK(ecx, 24, 0xff);
420 info[11] = BITMASK(edx, 0, 0xff);
421 info[12] = BITMASK(edx, 8, 0xff);
422 info[13] = BITMASK(edx, 16, 0xff);
423 info[14] = BITMASK(edx, 24, 0xff);
425 for (i = 0; i < 15; i++){
428 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
437 LITB.associative = 0;
447 LDTB.associative = 4;
452 LDTB.associative = 4;
611 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
656 LITB.associative = 0;
665 LITB.associative = 0;
674 LITB.associative = 0;
680 LITB.associative = 0;
686 LDTB.associative = 4;
691 LDTB.associative = 4;
699 LDTB.associative = 0;
708 LDTB.associative = 0;
717 LDTB.associative = 0;
885 L2DTB.associative = 0;
895 LITB.associative = 4;
982 if (get_vendor() == VENDOR_INTEL) {
983 if(LD1.size<=0 || LC1.size<=0){
984 //If we didn't detect L1 correctly before,
986 for (count=0;count <4;count++) {
987 cpuid_count(4, count, &eax, &ebx, &ecx, &edx);
994 switch ((eax >>5) &0x07)
998 // fprintf(stderr,"L1 data cache...\n");
1000 int lines = (ebx & 0x0fff) +1;
1002 int part = (ebx&0x03ff)+1;
1004 int assoc = (ebx&0x03ff)+1;
1005 LD1.size = (assoc*part*lines*sets)/1024;
1006 LD1.associative = assoc;
1007 LD1.linesize= lines;
1017 switch ((eax >>5) &0x07)
1021 // fprintf(stderr,"L1 instruction cache...\n");
1023 int lines = (ebx & 0x0fff) +1;
1025 int part = (ebx&0x03ff)+1;
1027 int assoc = (ebx&0x03ff)+1;
1028 LC1.size = (assoc*part*lines*sets)/1024;
1029 LC1.associative = assoc;
1030 LC1.linesize= lines;
1044 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
1045 if (cpuid_level >= 0x80000006) {
1047 //If we didn't detect L2 correctly before,
1048 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1050 L2.size = BITMASK(ecx, 16, 0xffff);
1051 L2.associative = BITMASK(ecx, 12, 0x0f);
1053 switch (L2.associative){
1058 L2.associative = 16;
1062 L2.linesize = BITMASK(ecx, 0, 0xff);
1067 if ((get_vendor() == VENDOR_AMD) ||
1068 (get_vendor() == VENDOR_HYGON) ||
1069 (get_vendor() == VENDOR_CENTAUR)) {
1070 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1073 LDTB.associative = BITMASK(eax, 24, 0xff);
1074 if (LDTB.associative == 0xff) LDTB.associative = 0;
1075 LDTB.linesize = BITMASK(eax, 16, 0xff);
1078 LITB.associative = BITMASK(eax, 8, 0xff);
1079 if (LITB.associative == 0xff) LITB.associative = 0;
1080 LITB.linesize = BITMASK(eax, 0, 0xff);
1083 DTB.associative = BITMASK(ebx, 24, 0xff);
1084 if (DTB.associative == 0xff) DTB.associative = 0;
1085 DTB.linesize = BITMASK(ebx, 16, 0xff);
1088 ITB.associative = BITMASK(ebx, 8, 0xff);
1089 if (ITB.associative == 0xff) ITB.associative = 0;
1090 ITB.linesize = BITMASK(ebx, 0, 0xff);
1092 LD1.size = BITMASK(ecx, 24, 0xff);
1093 LD1.associative = BITMASK(ecx, 16, 0xff);
1094 if (LD1.associative == 0xff) LD1.associative = 0;
1095 LD1.linesize = BITMASK(ecx, 0, 0xff);
1097 LC1.size = BITMASK(ecx, 24, 0xff);
1098 LC1.associative = BITMASK(ecx, 16, 0xff);
1099 if (LC1.associative == 0xff) LC1.associative = 0;
1100 LC1.linesize = BITMASK(ecx, 0, 0xff);
1102 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1105 L2LDTB.associative = BITMASK(eax, 24, 0xff);
1106 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
1107 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
1110 L2LITB.associative = BITMASK(eax, 8, 0xff);
1111 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
1112 L2LITB.linesize = BITMASK(eax, 0, 0xff);
1115 L2DTB.associative = BITMASK(ebx, 24, 0xff);
1116 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
1117 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
1120 L2ITB.associative = BITMASK(ebx, 8, 0xff);
1121 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
1122 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
1125 //If we didn't detect L2 correctly before,
1126 L2.size = BITMASK(ecx, 16, 0xffff);
1127 L2.associative = BITMASK(ecx, 12, 0xf);
1128 switch (L2.associative){
1133 L2.associative = 16;
1137 if (L2.associative == 0xff) L2.associative = 0;
1138 L2.linesize = BITMASK(ecx, 0, 0xff);
1141 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
1142 L3.associative = BITMASK(edx, 12, 0xf);
1143 if (L3.associative == 0xff) L2.associative = 0;
1144 L3.linesize = BITMASK(edx, 0, 0xff);
1150 case CACHE_INFO_L1_I :
1153 case CACHE_INFO_L1_D :
1156 case CACHE_INFO_L2 :
1159 case CACHE_INFO_L3 :
1162 case CACHE_INFO_L1_DTB :
1165 case CACHE_INFO_L1_ITB :
1168 case CACHE_INFO_L1_LDTB :
1171 case CACHE_INFO_L1_LITB :
1174 case CACHE_INFO_L2_DTB :
1177 case CACHE_INFO_L2_ITB :
1180 case CACHE_INFO_L2_LDTB :
1181 *cacheinfo = L2LDTB;
1183 case CACHE_INFO_L2_LITB :
1184 *cacheinfo = L2LITB;
1190 int get_cpuname(void){
1192 int family, exfamily, model, vendor, exmodel;
1194 if (!have_cpuid()) return CPUTYPE_80386;
1196 family = get_cputype(GET_FAMILY);
1197 exfamily = get_cputype(GET_EXFAMILY);
1198 model = get_cputype(GET_MODEL);
1199 exmodel = get_cputype(GET_EXMODEL);
1201 vendor = get_vendor();
1203 if (vendor == VENDOR_INTEL){
1206 return CPUTYPE_80486;
1208 return CPUTYPE_PENTIUM;
1217 #if defined(__x86_64__) || defined(__amd64__)
1218 return CPUTYPE_CORE2;
1220 return CPUTYPE_PENTIUM2;
1226 return CPUTYPE_PENTIUM3;
1230 return CPUTYPE_PENTIUMM;
1232 return CPUTYPE_CORE2;
1235 case 1: // family 6 exmodel 1
1238 return CPUTYPE_CORE2;
1240 return CPUTYPE_PENRYN;
1245 return CPUTYPE_NEHALEM;
1247 return CPUTYPE_ATOM;
1249 return CPUTYPE_DUNNINGTON;
1252 case 2: // family 6 exmodel 2
1255 //Intel Core (Clarkdale) / Core (Arrandale)
1256 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1257 // Xeon (Clarkdale), 32nm
1258 return CPUTYPE_NEHALEM;
1260 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1262 return CPUTYPE_SANDYBRIDGE;
1264 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1266 //Xeon Processor 5600 (Westmere-EP)
1267 return CPUTYPE_NEHALEM;
1269 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1271 return CPUTYPE_SANDYBRIDGE;
1273 return CPUTYPE_NEHALEM;
1277 //Xeon Processor E7 (Westmere-EX)
1278 return CPUTYPE_NEHALEM;
1281 case 3: // family 6 exmodel 3
1285 return CPUTYPE_ATOM;
1290 return CPUTYPE_SANDYBRIDGE;
1292 return CPUTYPE_NEHALEM;
1296 return CPUTYPE_HASWELL;
1298 return CPUTYPE_SANDYBRIDGE;
1300 return CPUTYPE_NEHALEM;
1304 return CPUTYPE_HASWELL;
1306 return CPUTYPE_SANDYBRIDGE;
1308 return CPUTYPE_NEHALEM;
1311 case 4: // family 6 exmodel 4
1316 return CPUTYPE_HASWELL;
1318 return CPUTYPE_SANDYBRIDGE;
1320 return CPUTYPE_NEHALEM;
1325 return CPUTYPE_HASWELL;
1327 return CPUTYPE_SANDYBRIDGE;
1329 return CPUTYPE_NEHALEM;
1333 return CPUTYPE_HASWELL;
1335 return CPUTYPE_SANDYBRIDGE;
1337 return CPUTYPE_NEHALEM;
1342 return CPUTYPE_NEHALEM;
1345 case 5: // family 6 exmodel 5
1350 return CPUTYPE_HASWELL;
1352 return CPUTYPE_SANDYBRIDGE;
1354 return CPUTYPE_NEHALEM;
1357 if(support_avx512_bf16())
1358 return CPUTYPE_COOPERLAKE;
1359 if(support_avx512())
1360 return CPUTYPE_SKYLAKEX;
1362 return CPUTYPE_HASWELL;
1364 return CPUTYPE_SANDYBRIDGE;
1366 return CPUTYPE_NEHALEM;
1370 return CPUTYPE_HASWELL;
1372 return CPUTYPE_SANDYBRIDGE;
1374 return CPUTYPE_NEHALEM;
1376 // Xeon Phi Knights Landing
1378 return CPUTYPE_HASWELL;
1380 return CPUTYPE_SANDYBRIDGE;
1382 return CPUTYPE_NEHALEM;
1387 return CPUTYPE_NEHALEM;
1390 case 6: // family 6 exmodel 6
1392 case 6: // Cannon Lake
1393 if(support_avx512())
1394 return CPUTYPE_SKYLAKEX;
1396 return CPUTYPE_HASWELL;
1398 return CPUTYPE_SANDYBRIDGE;
1400 return CPUTYPE_NEHALEM;
1403 case 7: // family 6 exmodel 7
1405 case 10: // Goldmont Plus
1406 return CPUTYPE_NEHALEM;
1407 case 14: // Ice Lake
1408 if(support_avx512())
1409 return CPUTYPE_SKYLAKEX;
1411 return CPUTYPE_HASWELL;
1413 return CPUTYPE_SANDYBRIDGE;
1415 return CPUTYPE_NEHALEM;
1421 case 14: // Kaby Lake and refreshes
1423 return CPUTYPE_HASWELL;
1425 return CPUTYPE_SANDYBRIDGE;
1427 return CPUTYPE_NEHALEM;
1429 case 10: //family 6 exmodel 10
1431 case 5: // Comet Lake H and S
1432 case 6: // Comet Lake U
1434 return CPUTYPE_HASWELL;
1436 return CPUTYPE_SANDYBRIDGE;
1438 return CPUTYPE_NEHALEM;
1439 case 7: // Rocket Lake
1440 if(support_avx512())
1441 return CPUTYPE_SKYLAKEX;
1443 return CPUTYPE_HASWELL;
1445 return CPUTYPE_SANDYBRIDGE;
1447 return CPUTYPE_NEHALEM;
1453 return CPUTYPE_ITANIUM;
1457 return CPUTYPE_PENTIUM4;
1459 return CPUTYPE_ITANIUM;
1463 return CPUTYPE_INTEL_UNKNOWN;
1466 if (vendor == VENDOR_AMD){
1469 return CPUTYPE_AMD5X86;
1471 return CPUTYPE_AMDK6;
1473 #if defined(__x86_64__) || defined(__amd64__)
1474 return CPUTYPE_BARCELONA;
1476 return CPUTYPE_ATHLON;
1482 return CPUTYPE_OPTERON;
1487 return CPUTYPE_BARCELONA;
1490 return CPUTYPE_BOBCAT;
1494 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1496 return CPUTYPE_BULLDOZER;
1498 return CPUTYPE_BARCELONA; //OS don't support AVX.
1499 case 2: //AMD Piledriver
1500 case 3: //AMD Richland
1502 return CPUTYPE_PILEDRIVER;
1504 return CPUTYPE_BARCELONA; //OS don't support AVX.
1505 case 5: // New EXCAVATOR CPUS
1507 return CPUTYPE_EXCAVATOR;
1509 return CPUTYPE_BARCELONA; //OS don't support AVX.
1513 case 1: //AMD Trinity
1515 return CPUTYPE_PILEDRIVER;
1517 return CPUTYPE_BARCELONA; //OS don't support AVX.
1520 return CPUTYPE_STEAMROLLER;
1522 return CPUTYPE_BARCELONA; //OS don't support AVX.
1526 return CPUTYPE_EXCAVATOR;
1528 return CPUTYPE_BARCELONA; //OS don't support AVX.
1540 // Matisse/Renoir and other recent Ryzen2
1545 return CPUTYPE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1548 return CPUTYPE_BARCELONA;
1556 return CPUTYPE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1559 return CPUTYPE_BARCELONA;
1563 return CPUTYPE_AMD_UNKNOWN;
1566 if (vendor == VENDOR_HYGON){
1576 return CPUTYPE_SANDYBRIDGE; // closer in architecture to Sandy Bridge than to Excavator
1579 return CPUTYPE_BARCELONA;
1583 return CPUTYPE_HYGON_UNKNOWN;
1586 if (vendor == VENDOR_CYRIX){
1589 return CPUTYPE_CYRIX5X86;
1591 return CPUTYPE_CYRIXM1;
1593 return CPUTYPE_CYRIXM2;
1595 return CPUTYPE_CYRIX_UNKNOWN;
1598 if (vendor == VENDOR_NEXGEN){
1601 return CPUTYPE_NEXGENNX586;
1603 return CPUTYPE_NEXGEN_UNKNOWN;
1606 if (vendor == VENDOR_CENTAUR){
1609 return CPUTYPE_CENTAURC6;
1612 return CPUTYPE_NANO;
1616 return CPUTYPE_VIAC3;
1619 if (vendor == VENDOR_RISE){
1622 return CPUTYPE_RISEMP6;
1624 return CPUTYPE_RISE_UNKNOWN;
1627 if (vendor == VENDOR_SIS){
1630 return CPUTYPE_SYS55X;
1632 return CPUTYPE_SIS_UNKNOWN;
1635 if (vendor == VENDOR_TRANSMETA){
1638 return CPUTYPE_CRUSOETM3X;
1640 return CPUTYPE_TRANSMETA_UNKNOWN;
1643 if (vendor == VENDOR_NSC){
1646 return CPUTYPE_NSGEODE;
1648 return CPUTYPE_NSC_UNKNOWN;
1651 return CPUTYPE_UNKNOWN;
1654 static char *cpuname[] = {
1664 "TRANSMETA_UNKNOWN",
1712 static char *lowercpuname[] = {
1722 "transmeta_unknown",
1769 static char *corename[] = {
1803 static char *corename_lower[] = {
1838 char *get_cpunamechar(void){
1839 return cpuname[get_cpuname()];
1842 char *get_lower_cpunamechar(void){
1843 return lowercpuname[get_cpuname()];
1847 int get_coretype(void){
1849 int family, exfamily, model, exmodel, vendor;
1851 if (!have_cpuid()) return CORE_80486;
1853 family = get_cputype(GET_FAMILY);
1854 exfamily = get_cputype(GET_EXFAMILY);
1855 model = get_cputype(GET_MODEL);
1856 exmodel = get_cputype(GET_EXMODEL);
1858 vendor = get_vendor();
1860 if (vendor == VENDOR_INTEL){
1877 #if defined(__x86_64__) || defined(__amd64__)
1887 return CORE_COPPERMINE;
1906 return CORE_NEHALEM;
1910 return CORE_DUNNINGTON;
1916 //Intel Core (Clarkdale) / Core (Arrandale)
1917 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1918 // Xeon (Clarkdale), 32nm
1919 return CORE_NEHALEM;
1921 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1923 return CORE_SANDYBRIDGE;
1925 return CORE_NEHALEM; //OS doesn't support AVX
1927 //Xeon Processor 5600 (Westmere-EP)
1928 return CORE_NEHALEM;
1930 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1932 return CORE_SANDYBRIDGE;
1934 return CORE_NEHALEM; //OS doesn't support AVX
1938 //Xeon Processor E7 (Westmere-EX)
1939 return CORE_NEHALEM;
1949 return CORE_SANDYBRIDGE;
1951 return CORE_NEHALEM; //OS doesn't support AVX
1956 return CORE_HASWELL;
1958 return CORE_SANDYBRIDGE;
1961 return CORE_NEHALEM;
1966 return CORE_HASWELL;
1968 return CORE_SANDYBRIDGE;
1971 return CORE_NEHALEM;
1980 return CORE_HASWELL;
1982 return CORE_SANDYBRIDGE;
1985 return CORE_NEHALEM;
1991 return CORE_HASWELL;
1993 return CORE_SANDYBRIDGE;
1996 return CORE_NEHALEM;
2001 return CORE_HASWELL;
2003 return CORE_SANDYBRIDGE;
2006 return CORE_NEHALEM;
2011 return CORE_NEHALEM;
2016 case 5: // Comet Lake H and S
2017 case 6: // Comet Lake U
2020 return CORE_HASWELL;
2022 return CORE_SANDYBRIDGE;
2025 return CORE_NEHALEM;
2026 case 7:// Rocket Lake
2028 if(support_avx512())
2029 return CORE_SKYLAKEX;
2033 return CORE_HASWELL;
2036 return CORE_SANDYBRIDGE;
2038 return CORE_NEHALEM;
2046 return CORE_HASWELL;
2048 return CORE_SANDYBRIDGE;
2051 return CORE_NEHALEM;
2055 if(support_avx512_bf16())
2056 return CORE_COOPERLAKE;
2057 return CORE_SKYLAKEX;
2061 return CORE_HASWELL;
2063 return CORE_SANDYBRIDGE;
2066 return CORE_NEHALEM;
2072 return CORE_HASWELL;
2074 return CORE_SANDYBRIDGE;
2077 return CORE_NEHALEM;
2079 // Phi Knights Landing
2082 return CORE_HASWELL;
2084 return CORE_SANDYBRIDGE;
2087 return CORE_NEHALEM;
2090 return CORE_NEHALEM;
2096 return CORE_SKYLAKEX;
2100 return CORE_HASWELL;
2102 return CORE_SANDYBRIDGE;
2105 return CORE_NEHALEM;
2110 return CORE_NEHALEM;
2113 return CORE_SKYLAKEX;
2117 return CORE_HASWELL;
2119 return CORE_SANDYBRIDGE;
2122 return CORE_NEHALEM;
2127 if (model == 14) { // Kaby Lake
2130 return CORE_HASWELL;
2132 return CORE_SANDYBRIDGE;
2135 return CORE_NEHALEM;
2141 if (model <= 0x2) return CORE_NORTHWOOD;
2142 else return CORE_PRESCOTT;
2146 if (vendor == VENDOR_AMD){
2147 if (family <= 0x5) return CORE_80486;
2148 #if defined(__x86_64__) || defined(__amd64__)
2149 if (family <= 0xe) return CORE_BARCELONA;
2151 if (family <= 0xe) return CORE_ATHLON;
2154 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
2155 else if (exfamily == 5) return CORE_BOBCAT;
2156 else if (exfamily == 6) {
2159 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
2161 return CORE_BULLDOZER;
2163 return CORE_BARCELONA; //OS don't support AVX.
2164 case 2: //AMD Piledriver
2165 case 3: //AMD Richland
2167 return CORE_PILEDRIVER;
2169 return CORE_BARCELONA; //OS don't support AVX.
2170 case 5: // New EXCAVATOR
2172 return CORE_EXCAVATOR;
2174 return CORE_BARCELONA; //OS don't support AVX.
2178 case 1: //AMD Trinity
2180 return CORE_PILEDRIVER;
2182 return CORE_BARCELONA; //OS don't support AVX.
2186 return CORE_STEAMROLLER;
2188 return CORE_BARCELONA; //OS don't support AVX.
2192 return CORE_EXCAVATOR;
2194 return CORE_BARCELONA; //OS don't support AVX.
2198 } else if (exfamily == 8 || exfamily == 10) {
2205 // Matisse,Renoir Ryzen2 models
2210 return CORE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
2213 return CORE_BARCELONA;
2216 return CORE_BARCELONA;
2221 if (vendor == VENDOR_HYGON){
2223 if (exfamily == 9) {
2228 return CORE_SANDYBRIDGE; // closer in architecture to Sandy Bridge than to Excavator
2231 return CORE_BARCELONA;
2233 return CORE_BARCELONA;
2238 if (vendor == VENDOR_CENTAUR) {
2247 return CORE_UNKNOWN;
2250 void get_cpuconfig(void){
2255 printf("#define %s\n", cpuname[get_cpuname()]);
2258 if (get_coretype() != CORE_P5) {
2260 get_cacheinfo(CACHE_INFO_L1_I, &info);
2261 if (info.size > 0) {
2262 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
2263 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
2264 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
2267 get_cacheinfo(CACHE_INFO_L1_D, &info);
2268 if (info.size > 0) {
2269 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
2270 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
2271 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
2274 get_cacheinfo(CACHE_INFO_L2, &info);
2275 if (info.size > 0) {
2276 printf("#define L2_SIZE %d\n", info.size * 1024);
2277 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
2278 printf("#define L2_LINESIZE %d\n", info.linesize);
2280 //fall back for some virtual machines.
2281 printf("#define L2_SIZE 1048576\n");
2282 printf("#define L2_ASSOCIATIVE 6\n");
2283 printf("#define L2_LINESIZE 64\n");
2287 get_cacheinfo(CACHE_INFO_L3, &info);
2288 if (info.size > 0) {
2289 printf("#define L3_SIZE %d\n", info.size * 1024);
2290 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
2291 printf("#define L3_LINESIZE %d\n", info.linesize);
2294 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
2295 if (info.size > 0) {
2296 printf("#define ITB_SIZE %d\n", info.size * 1024);
2297 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
2298 printf("#define ITB_ENTRIES %d\n", info.linesize);
2301 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
2302 if (info.size > 0) {
2303 printf("#define DTB_SIZE %d\n", info.size * 1024);
2304 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
2305 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
2307 //fall back for some virtual machines.
2308 printf("#define DTB_DEFAULT_ENTRIES 32\n");
2311 features = get_cputype(GET_FEATURE);
2313 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
2314 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
2315 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
2316 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
2317 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
2318 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
2319 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
2320 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
2321 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
2322 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
2323 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
2324 if (features & HAVE_AVX2 ) printf("#define HAVE_AVX2\n");
2325 if (features & HAVE_AVX512VL ) printf("#define HAVE_AVX512VL\n");
2326 if (features & HAVE_AVX512BF16 ) printf("#define HAVE_AVX512BF16\n");
2327 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
2328 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
2329 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
2330 if (features & HAVE_FMA3 ) printf("#define HAVE_FMA3\n");
2331 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
2332 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
2333 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
2334 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
2335 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
2337 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
2338 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
2340 features = get_coretype();
2341 if (features > 0) printf("#define CORE_%s\n", corename[features]);
2343 printf("#define DTB_DEFAULT_ENTRIES 16\n");
2344 printf("#define L1_CODE_SIZE 8192\n");
2345 printf("#define L1_DATA_SIZE 8192\n");
2346 printf("#define L2_SIZE 0\n");
2350 void get_architecture(void){
2358 void get_subarchitecture(void){
2359 printf("%s", get_cpunamechar());
2362 void get_subdirname(void){
2370 char *get_corename(void){
2371 return corename[get_coretype()];
2374 void get_libname(void){
2375 printf("%s", corename_lower[get_coretype()]);
2378 /* This if for Makefile */
2383 features = get_cputype(GET_FEATURE);
2385 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
2386 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
2387 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
2388 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
2389 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
2390 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
2391 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
2392 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
2393 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
2394 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
2395 if (features & HAVE_AVX2 ) printf("HAVE_AVX2=1\n");
2396 if (features & HAVE_AVX512VL ) printf("HAVE_AVX512VL=1\n");
2397 if (features & HAVE_AVX512BF16 ) printf("HAVE_AVX512BF16=1\n");
2398 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
2399 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
2400 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");
2401 if (features & HAVE_FMA3 ) printf("HAVE_FMA3=1\n");