1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
44 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
45 #define CORE_HASWELL CORE_NEHALEM
46 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
47 #define CORE_SANDYBRIDGE CORE_NEHALEM
48 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
49 #define CORE_BULLDOZER CORE_BARCELONA
50 #define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
51 #define CORE_PILEDRIVER CORE_BARCELONA
56 #if defined(__APPLE__) && defined(__i386__)
57 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
59 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
61 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
69 unsigned int id, a, b, c, d;
78 extern idlist_t idlist[];
79 extern vendor_t vendor[];
81 static int cv = VENDOR;
83 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
85 static int current = 0;
87 int start = vendor[cv].start;
88 int stop = vendor[cv].stop;
89 int count = stop - start;
91 if ((current < start) || (current > stop)) current = start;
93 while ((count > 0) && (idlist[current].id != op)) {
96 if (current > stop) current = start;
101 *eax = idlist[current].a;
102 *ebx = idlist[current].b;
103 *ecx = idlist[current].c;
104 *edx = idlist[current].d;
109 static inline int have_cpuid(void){
110 int eax, ebx, ecx, edx;
112 cpuid(0, &eax, &ebx, &ecx, &edx);
116 static inline int have_excpuid(void){
117 int eax, ebx, ecx, edx;
119 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
124 static inline void xgetbv(int op, int * eax, int * edx){
125 //Use binary code for xgetbv
127 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
133 int eax, ebx, ecx, edx;
136 cpuid(1, &eax, &ebx, &ecx, &edx);
137 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
138 xgetbv(0, &eax, &edx);
140 ret=1; //OS support AVX
150 int get_vendor(void){
151 int eax, ebx, ecx, edx;
154 cpuid(0, &eax, &ebx, &ecx, &edx);
156 *(int *)(&vendor[0]) = ebx;
157 *(int *)(&vendor[4]) = edx;
158 *(int *)(&vendor[8]) = ecx;
159 vendor[12] = (char)0;
161 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
162 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
163 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
164 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
165 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
166 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
167 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
168 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
169 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
170 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
172 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
174 return VENDOR_UNKNOWN;
177 int get_cputype(int gettype){
178 int eax, ebx, ecx, edx;
179 int extend_family, family;
180 int extend_model, model;
184 cpuid(1, &eax, &ebx, &ecx, &edx);
188 return BITMASK(eax, 20, 0xff);
190 return BITMASK(eax, 16, 0x0f);
192 return BITMASK(eax, 12, 0x03);
194 return BITMASK(eax, 8, 0x0f);
196 return BITMASK(eax, 4, 0x0f);
198 return BITMASK(ebx, 24, 0x0f);
200 return BITMASK(ebx, 16, 0x0f);
202 return BITMASK(ebx, 8, 0x0f);
204 return BITMASK(eax, 0, 0x0f);
206 return BITMASK(ebx, 0, 0xff);
208 if (have_cpuid() < 4) return 0;
209 cpuid(4, &eax, &ebx, &ecx, &edx);
210 return BITMASK(eax, 14, 0xfff);
212 if (have_cpuid() < 4) return 0;
213 cpuid(4, &eax, &ebx, &ecx, &edx);
214 return BITMASK(eax, 26, 0x3f);
217 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
218 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
219 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
220 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
221 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
222 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
223 if ((edx & (1 << 27)) != 0) {
224 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
226 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
227 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
228 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
229 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
231 if (support_avx()) feature |= HAVE_AVX;
233 if ((ecx & (1 << 20)) != 0) feature |= HAVE_FMA3;
235 if (have_excpuid() >= 0x01) {
236 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
237 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
238 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
240 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
242 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
243 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
246 if (have_excpuid() >= 0x1a) {
247 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
248 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
249 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
256 int get_cacheinfo(int type, cache_info_t *cacheinfo){
257 int eax, ebx, ecx, edx, cpuid_level;
260 cache_info_t LC1, LD1, L2, L3,
261 ITB, DTB, LITB, LDTB,
262 L2ITB, L2DTB, L2LITB, L2LDTB;
264 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
265 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
266 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
267 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
268 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
269 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
270 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
271 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
272 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
273 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
274 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
275 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
277 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
279 if (cpuid_level > 1) {
281 cpuid(2, &eax, &ebx, &ecx, &edx);
283 info[ 0] = BITMASK(eax, 8, 0xff);
284 info[ 1] = BITMASK(eax, 16, 0xff);
285 info[ 2] = BITMASK(eax, 24, 0xff);
287 info[ 3] = BITMASK(ebx, 0, 0xff);
288 info[ 4] = BITMASK(ebx, 8, 0xff);
289 info[ 5] = BITMASK(ebx, 16, 0xff);
290 info[ 6] = BITMASK(ebx, 24, 0xff);
292 info[ 7] = BITMASK(ecx, 0, 0xff);
293 info[ 8] = BITMASK(ecx, 8, 0xff);
294 info[ 9] = BITMASK(ecx, 16, 0xff);
295 info[10] = BITMASK(ecx, 24, 0xff);
297 info[11] = BITMASK(edx, 0, 0xff);
298 info[12] = BITMASK(edx, 8, 0xff);
299 info[13] = BITMASK(edx, 16, 0xff);
300 info[14] = BITMASK(edx, 24, 0xff);
302 for (i = 0; i < 15; i++){
306 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
315 LITB.associative = 0;
325 LDTB.associative = 4;
330 LDTB.associative = 4;
489 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
534 LITB.associative = 0;
543 LITB.associative = 0;
552 LITB.associative = 0;
558 LITB.associative = 0;
564 LDTB.associative = 4;
569 LDTB.associative = 4;
577 LDTB.associative = 0;
586 LDTB.associative = 0;
595 LDTB.associative = 0;
747 L2DTB.associative = 0;
757 LITB.associative = 4;
844 if (get_vendor() == VENDOR_INTEL) {
845 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
846 if (cpuid_level >= 0x80000006) {
847 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
849 L2.size = BITMASK(ecx, 16, 0xffff);
850 L2.associative = BITMASK(ecx, 12, 0x0f);
851 L2.linesize = BITMASK(ecx, 0, 0xff);
855 if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
856 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
859 LDTB.associative = BITMASK(eax, 24, 0xff);
860 if (LDTB.associative == 0xff) LDTB.associative = 0;
861 LDTB.linesize = BITMASK(eax, 16, 0xff);
864 LITB.associative = BITMASK(eax, 8, 0xff);
865 if (LITB.associative == 0xff) LITB.associative = 0;
866 LITB.linesize = BITMASK(eax, 0, 0xff);
869 DTB.associative = BITMASK(ebx, 24, 0xff);
870 if (DTB.associative == 0xff) DTB.associative = 0;
871 DTB.linesize = BITMASK(ebx, 16, 0xff);
874 ITB.associative = BITMASK(ebx, 8, 0xff);
875 if (ITB.associative == 0xff) ITB.associative = 0;
876 ITB.linesize = BITMASK(ebx, 0, 0xff);
878 LD1.size = BITMASK(ecx, 24, 0xff);
879 LD1.associative = BITMASK(ecx, 16, 0xff);
880 if (LD1.associative == 0xff) LD1.associative = 0;
881 LD1.linesize = BITMASK(ecx, 0, 0xff);
883 LC1.size = BITMASK(ecx, 24, 0xff);
884 LC1.associative = BITMASK(ecx, 16, 0xff);
885 if (LC1.associative == 0xff) LC1.associative = 0;
886 LC1.linesize = BITMASK(ecx, 0, 0xff);
888 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
891 L2LDTB.associative = BITMASK(eax, 24, 0xff);
892 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
893 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
896 L2LITB.associative = BITMASK(eax, 8, 0xff);
897 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
898 L2LITB.linesize = BITMASK(eax, 0, 0xff);
901 L2DTB.associative = BITMASK(ebx, 24, 0xff);
902 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
903 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
906 L2ITB.associative = BITMASK(ebx, 8, 0xff);
907 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
908 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
910 L2.size = BITMASK(ecx, 16, 0xffff);
911 L2.associative = BITMASK(ecx, 12, 0xf);
912 if (L2.associative == 0xff) L2.associative = 0;
913 L2.linesize = BITMASK(ecx, 0, 0xff);
915 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
916 L3.associative = BITMASK(edx, 12, 0xf);
917 if (L3.associative == 0xff) L2.associative = 0;
918 L3.linesize = BITMASK(edx, 0, 0xff);
924 case CACHE_INFO_L1_I :
927 case CACHE_INFO_L1_D :
936 case CACHE_INFO_L1_DTB :
939 case CACHE_INFO_L1_ITB :
942 case CACHE_INFO_L1_LDTB :
945 case CACHE_INFO_L1_LITB :
948 case CACHE_INFO_L2_DTB :
951 case CACHE_INFO_L2_ITB :
954 case CACHE_INFO_L2_LDTB :
957 case CACHE_INFO_L2_LITB :
964 int get_cpuname(void){
966 int family, exfamily, model, vendor, exmodel;
968 if (!have_cpuid()) return CPUTYPE_80386;
970 family = get_cputype(GET_FAMILY);
971 exfamily = get_cputype(GET_EXFAMILY);
972 model = get_cputype(GET_MODEL);
973 exmodel = get_cputype(GET_EXMODEL);
975 vendor = get_vendor();
977 if (vendor == VENDOR_INTEL){
980 return CPUTYPE_80486;
982 return CPUTYPE_PENTIUM;
991 return CPUTYPE_PENTIUM2;
996 return CPUTYPE_PENTIUM3;
1000 return CPUTYPE_PENTIUMM;
1002 return CPUTYPE_CORE2;
1008 return CPUTYPE_CORE2;
1010 return CPUTYPE_PENRYN;
1015 return CPUTYPE_NEHALEM;
1017 return CPUTYPE_ATOM;
1019 return CPUTYPE_DUNNINGTON;
1025 //Intel Core (Clarkdale) / Core (Arrandale)
1026 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1027 // Xeon (Clarkdale), 32nm
1028 return CPUTYPE_NEHALEM;
1030 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1032 return CPUTYPE_SANDYBRIDGE;
1034 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1036 //Xeon Processor 5600 (Westmere-EP)
1037 return CPUTYPE_NEHALEM;
1039 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1041 return CPUTYPE_SANDYBRIDGE;
1043 return CPUTYPE_NEHALEM;
1047 //Xeon Processor E7 (Westmere-EX)
1048 return CPUTYPE_NEHALEM;
1055 return CPUTYPE_SANDYBRIDGE;
1057 return CPUTYPE_NEHALEM;
1060 return CPUTYPE_HASWELL;
1062 return CPUTYPE_NEHALEM;
1069 return CPUTYPE_HASWELL;
1071 return CPUTYPE_NEHALEM;
1077 return CPUTYPE_ITANIUM;
1081 return CPUTYPE_PENTIUM4;
1083 return CPUTYPE_ITANIUM;
1087 return CPUTYPE_INTEL_UNKNOWN;
1090 if (vendor == VENDOR_AMD){
1093 return CPUTYPE_AMD5X86;
1095 return CPUTYPE_AMDK6;
1097 return CPUTYPE_ATHLON;
1102 return CPUTYPE_OPTERON;
1105 return CPUTYPE_BARCELONA;
1109 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1111 return CPUTYPE_BULLDOZER;
1113 return CPUTYPE_BARCELONA; //OS don't support AVX.
1116 return CPUTYPE_PILEDRIVER;
1118 return CPUTYPE_BARCELONA; //OS don't support AVX.
1122 return CPUTYPE_BOBCAT;
1126 return CPUTYPE_AMD_UNKNOWN;
1129 if (vendor == VENDOR_CYRIX){
1132 return CPUTYPE_CYRIX5X86;
1134 return CPUTYPE_CYRIXM1;
1136 return CPUTYPE_CYRIXM2;
1138 return CPUTYPE_CYRIX_UNKNOWN;
1141 if (vendor == VENDOR_NEXGEN){
1144 return CPUTYPE_NEXGENNX586;
1146 return CPUTYPE_NEXGEN_UNKNOWN;
1149 if (vendor == VENDOR_CENTAUR){
1152 return CPUTYPE_CENTAURC6;
1155 return CPUTYPE_NANO;
1159 return CPUTYPE_VIAC3;
1162 if (vendor == VENDOR_RISE){
1165 return CPUTYPE_RISEMP6;
1167 return CPUTYPE_RISE_UNKNOWN;
1170 if (vendor == VENDOR_SIS){
1173 return CPUTYPE_SYS55X;
1175 return CPUTYPE_SIS_UNKNOWN;
1178 if (vendor == VENDOR_TRANSMETA){
1181 return CPUTYPE_CRUSOETM3X;
1183 return CPUTYPE_TRANSMETA_UNKNOWN;
1186 if (vendor == VENDOR_NSC){
1189 return CPUTYPE_NSGEODE;
1191 return CPUTYPE_NSC_UNKNOWN;
1194 return CPUTYPE_UNKNOWN;
1197 static char *cpuname[] = {
1207 "TRANSMETA_UNKNOWN",
1248 static char *lowercpuname[] = {
1258 "transmeta_unknown",
1298 static char *corename[] = {
1325 static char *corename_lower[] = {
1353 char *get_cpunamechar(void){
1354 return cpuname[get_cpuname()];
1357 char *get_lower_cpunamechar(void){
1358 return lowercpuname[get_cpuname()];
1362 int get_coretype(void){
1364 int family, exfamily, model, exmodel, vendor;
1366 if (!have_cpuid()) return CORE_80486;
1368 family = get_cputype(GET_FAMILY);
1369 exfamily = get_cputype(GET_EXFAMILY);
1370 model = get_cputype(GET_MODEL);
1371 exmodel = get_cputype(GET_EXMODEL);
1373 vendor = get_vendor();
1375 if (vendor == VENDOR_INTEL){
1398 return CORE_COPPERMINE;
1417 return CORE_NEHALEM;
1421 return CORE_DUNNINGTON;
1427 //Intel Core (Clarkdale) / Core (Arrandale)
1428 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1429 // Xeon (Clarkdale), 32nm
1430 return CORE_NEHALEM;
1432 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1434 return CORE_SANDYBRIDGE;
1436 return CORE_NEHALEM; //OS doesn't support AVX
1438 //Xeon Processor 5600 (Westmere-EP)
1439 return CORE_NEHALEM;
1441 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1443 return CORE_SANDYBRIDGE;
1445 return CORE_NEHALEM; //OS doesn't support AVX
1449 //Xeon Processor E7 (Westmere-EX)
1450 return CORE_NEHALEM;
1457 return CORE_SANDYBRIDGE;
1459 return CORE_NEHALEM; //OS doesn't support AVX
1462 return CORE_HASWELL;
1464 return CORE_NEHALEM;
1471 return CORE_HASWELL;
1473 return CORE_NEHALEM;
1480 if (model <= 0x2) return CORE_NORTHWOOD;
1481 else return CORE_PRESCOTT;
1485 if (vendor == VENDOR_AMD){
1486 if (family <= 0x5) return CORE_80486;
1487 if (family <= 0xe) return CORE_ATHLON;
1489 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
1490 else if (exfamily == 5) return CORE_BOBCAT;
1491 else if (exfamily == 6) {
1494 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1496 return CORE_BULLDOZER;
1498 return CORE_BARCELONA; //OS don't support AVX.
1501 return CORE_PILEDRIVER;
1503 return CORE_BARCELONA; //OS don't support AVX.
1505 }else return CORE_BARCELONA;
1509 if (vendor == VENDOR_CENTAUR) {
1518 return CORE_UNKNOWN;
1521 void get_cpuconfig(void){
1526 printf("#define %s\n", cpuname[get_cpuname()]);
1529 if (get_coretype() != CORE_P5) {
1531 get_cacheinfo(CACHE_INFO_L1_I, &info);
1532 if (info.size > 0) {
1533 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
1534 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
1535 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
1538 get_cacheinfo(CACHE_INFO_L1_D, &info);
1539 if (info.size > 0) {
1540 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
1541 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
1542 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
1545 get_cacheinfo(CACHE_INFO_L2, &info);
1546 if (info.size > 0) {
1547 printf("#define L2_SIZE %d\n", info.size * 1024);
1548 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
1549 printf("#define L2_LINESIZE %d\n", info.linesize);
1552 get_cacheinfo(CACHE_INFO_L3, &info);
1553 if (info.size > 0) {
1554 printf("#define L3_SIZE %d\n", info.size * 1024);
1555 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
1556 printf("#define L3_LINESIZE %d\n", info.linesize);
1559 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
1560 if (info.size > 0) {
1561 printf("#define ITB_SIZE %d\n", info.size * 1024);
1562 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
1563 printf("#define ITB_ENTRIES %d\n", info.linesize);
1566 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
1567 if (info.size > 0) {
1568 printf("#define DTB_SIZE %d\n", info.size * 1024);
1569 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
1570 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
1572 //fall back for some virtual machines.
1573 printf("#define DTB_DEFAULT_ENTRIES 32\n");
1576 features = get_cputype(GET_FEATURE);
1578 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
1579 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
1580 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
1581 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
1582 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
1583 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
1584 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
1585 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
1586 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
1587 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
1588 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
1589 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
1590 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
1591 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
1592 if (features & HAVE_FMA3 ) printf("#define HAVE_FMA3\n");
1593 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
1594 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
1595 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
1596 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
1597 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
1599 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
1600 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
1602 features = get_coretype();
1603 if (features > 0) printf("#define CORE_%s\n", corename[features]);
1605 printf("#define DTB_DEFAULT_ENTRIES 16\n");
1606 printf("#define L1_CODE_SIZE 8192\n");
1607 printf("#define L1_DATA_SIZE 8192\n");
1608 printf("#define L2_SIZE 0\n");
1612 void get_architecture(void){
1620 void get_subarchitecture(void){
1621 printf("%s", get_cpunamechar());
1624 void get_subdirname(void){
1632 char *get_corename(void){
1633 return corename[get_coretype()];
1636 void get_libname(void){
1637 printf("%s", corename_lower[get_coretype()]);
1640 /* This if for Makefile */
1645 features = get_cputype(GET_FEATURE);
1647 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
1648 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
1649 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
1650 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
1651 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
1652 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
1653 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
1654 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
1655 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
1656 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
1657 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
1658 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
1659 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");
1660 if (features & HAVE_FMA3 ) printf("HAVE_FMA3=1\n");