1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
43 #if defined(_MSC_VER) && !defined(__clang__)
44 #define C_INLINE __inline
46 #define C_INLINE inline
51 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
52 #define CORE_HASWELL CORE_NEHALEM
53 #define CPUTYPE_SKYLAKEX CPUTYPE_NEHALEM
54 #define CORE_SKYLAKEX CORE_NEHALEM
55 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
56 #define CORE_SANDYBRIDGE CORE_NEHALEM
57 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
58 #define CORE_BULLDOZER CORE_BARCELONA
59 #define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
60 #define CORE_PILEDRIVER CORE_BARCELONA
64 #if defined(_MSC_VER) && !defined(__clang__)
66 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
68 int cpuInfo[4] = {-1};
76 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx)
78 int cpuInfo[4] = {-1};
79 __cpuidex(cpuInfo, op, count);
90 #if defined(__APPLE__) && defined(__i386__)
91 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
92 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx);
94 static C_INLINE void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
95 #if defined(__i386__) && defined(__PIC__)
100 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op), "c" (0) : "cc");
103 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) , "c" (0) : "cc");
107 static C_INLINE void cpuid_count(int op, int count ,int *eax, int *ebx, int *ecx, int *edx){
108 #if defined(__i386__) && defined(__PIC__)
112 "xchgl %%ebx, %%edi;"
113 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
116 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
124 unsigned int id, a, b, c, d;
133 extern idlist_t idlist[];
134 extern vendor_t vendor[];
136 static int cv = VENDOR;
138 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
140 static int current = 0;
142 int start = vendor[cv].start;
143 int stop = vendor[cv].stop;
144 int count = stop - start;
146 if ((current < start) || (current > stop)) current = start;
148 while ((count > 0) && (idlist[current].id != op)) {
151 if (current > stop) current = start;
156 *eax = idlist[current].a;
157 *ebx = idlist[current].b;
158 *ecx = idlist[current].c;
159 *edx = idlist[current].d;
162 void cpuid_count (unsigned int op, unsigned int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
163 return cpuid (op, eax, ebx, ecx, edx);
170 static C_INLINE int have_cpuid(void){
171 int eax, ebx, ecx, edx;
173 cpuid(0, &eax, &ebx, &ecx, &edx);
177 static C_INLINE int have_excpuid(void){
178 int eax, ebx, ecx, edx;
180 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
185 static C_INLINE void xgetbv(int op, int * eax, int * edx){
186 //Use binary code for xgetbv
187 #if defined(_MSC_VER) && !defined(__clang__)
191 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
198 int eax, ebx, ecx, edx;
201 cpuid(1, &eax, &ebx, &ecx, &edx);
202 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
203 xgetbv(0, &eax, &edx);
205 ret=1; //OS support AVX
216 int eax, ebx, ecx=0, edx;
221 cpuid(7, &eax, &ebx, &ecx, &edx);
222 if((ebx & (1<<7)) != 0)
223 ret=1; //OS supports AVX2
230 int support_avx512(){
231 #if !defined(NO_AVX) && !defined(NO_AVX512)
232 int eax, ebx, ecx, edx;
237 cpuid(7, &eax, &ebx, &ecx, &edx);
238 if((ebx & 32) != 32){
239 ret=0; //OS does not even support AVX2
241 if((ebx & (1<<31)) != 0){
242 xgetbv(0, &eax, &edx);
243 if((eax & 0xe0) == 0xe0)
244 ret=1; //OS supports AVX512VL
253 int get_vendor(void){
254 int eax, ebx, ecx, edx;
257 cpuid(0, &eax, &ebx, &ecx, &edx);
259 *(int *)(&vendor[0]) = ebx;
260 *(int *)(&vendor[4]) = edx;
261 *(int *)(&vendor[8]) = ecx;
262 vendor[12] = (char)0;
264 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
265 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
266 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
267 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
268 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
269 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
270 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
271 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
272 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
273 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
274 if (!strcmp(vendor, "HygonGenuine")) return VENDOR_HYGON;
276 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
278 return VENDOR_UNKNOWN;
281 int get_cputype(int gettype){
282 int eax, ebx, ecx, edx;
283 int extend_family, family;
284 int extend_model, model;
288 cpuid(1, &eax, &ebx, &ecx, &edx);
292 return BITMASK(eax, 20, 0xff);
294 return BITMASK(eax, 16, 0x0f);
296 return BITMASK(eax, 12, 0x03);
298 return BITMASK(eax, 8, 0x0f);
300 return BITMASK(eax, 4, 0x0f);
302 return BITMASK(ebx, 24, 0x0f);
304 return BITMASK(ebx, 16, 0x0f);
306 return BITMASK(ebx, 8, 0x0f);
308 return BITMASK(eax, 0, 0x0f);
310 return BITMASK(ebx, 0, 0xff);
312 if (have_cpuid() < 4) return 0;
313 cpuid(4, &eax, &ebx, &ecx, &edx);
314 return BITMASK(eax, 14, 0xfff);
316 if (have_cpuid() < 4) return 0;
317 cpuid(4, &eax, &ebx, &ecx, &edx);
318 return BITMASK(eax, 26, 0x3f);
321 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
322 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
323 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
324 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
325 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
326 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
327 if ((edx & (1 << 27)) != 0) {
328 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
330 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
331 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
332 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
333 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
335 if (support_avx()) feature |= HAVE_AVX;
336 if (support_avx2()) feature |= HAVE_AVX2;
337 if (support_avx512()) feature |= HAVE_AVX512VL;
338 if ((ecx & (1 << 12)) != 0) feature |= HAVE_FMA3;
341 if (have_excpuid() >= 0x01) {
342 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
343 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
344 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
346 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
348 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
349 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
352 if (have_excpuid() >= 0x1a) {
353 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
354 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
355 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
362 int get_cacheinfo(int type, cache_info_t *cacheinfo){
363 int eax, ebx, ecx, edx, cpuid_level;
366 cache_info_t LC1, LD1, L2, L3,
367 ITB, DTB, LITB, LDTB,
368 L2ITB, L2DTB, L2LITB, L2LDTB;
370 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
371 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
372 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
373 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
374 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
375 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
376 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
377 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
378 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
379 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
380 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
381 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
383 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
385 if (cpuid_level > 1) {
387 cpuid(2, &eax, &ebx, &ecx, &edx);
388 numcalls = BITMASK(eax, 0, 0xff); //FIXME some systems may require repeated calls to read all entries
389 info[ 0] = BITMASK(eax, 8, 0xff);
390 info[ 1] = BITMASK(eax, 16, 0xff);
391 info[ 2] = BITMASK(eax, 24, 0xff);
393 info[ 3] = BITMASK(ebx, 0, 0xff);
394 info[ 4] = BITMASK(ebx, 8, 0xff);
395 info[ 5] = BITMASK(ebx, 16, 0xff);
396 info[ 6] = BITMASK(ebx, 24, 0xff);
398 info[ 7] = BITMASK(ecx, 0, 0xff);
399 info[ 8] = BITMASK(ecx, 8, 0xff);
400 info[ 9] = BITMASK(ecx, 16, 0xff);
401 info[10] = BITMASK(ecx, 24, 0xff);
403 info[11] = BITMASK(edx, 0, 0xff);
404 info[12] = BITMASK(edx, 8, 0xff);
405 info[13] = BITMASK(edx, 16, 0xff);
406 info[14] = BITMASK(edx, 24, 0xff);
408 for (i = 0; i < 15; i++){
411 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
420 LITB.associative = 0;
430 LDTB.associative = 4;
435 LDTB.associative = 4;
594 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
639 LITB.associative = 0;
648 LITB.associative = 0;
657 LITB.associative = 0;
663 LITB.associative = 0;
669 LDTB.associative = 4;
674 LDTB.associative = 4;
682 LDTB.associative = 0;
691 LDTB.associative = 0;
700 LDTB.associative = 0;
868 L2DTB.associative = 0;
878 LITB.associative = 4;
965 if (get_vendor() == VENDOR_INTEL) {
966 if(LD1.size<=0 || LC1.size<=0){
967 //If we didn't detect L1 correctly before,
969 for (count=0;count <4;count++) {
970 cpuid_count(4, count, &eax, &ebx, &ecx, &edx);
977 switch ((eax >>5) &0x07)
981 // fprintf(stderr,"L1 data cache...\n");
983 int lines = (ebx & 0x0fff) +1;
985 int part = (ebx&0x03ff)+1;
987 int assoc = (ebx&0x03ff)+1;
988 LD1.size = (assoc*part*lines*sets)/1024;
989 LD1.associative = assoc;
1000 switch ((eax >>5) &0x07)
1004 // fprintf(stderr,"L1 instruction cache...\n");
1006 int lines = (ebx & 0x0fff) +1;
1008 int part = (ebx&0x03ff)+1;
1010 int assoc = (ebx&0x03ff)+1;
1011 LC1.size = (assoc*part*lines*sets)/1024;
1012 LC1.associative = assoc;
1013 LC1.linesize= lines;
1027 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
1028 if (cpuid_level >= 0x80000006) {
1030 //If we didn't detect L2 correctly before,
1031 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1033 L2.size = BITMASK(ecx, 16, 0xffff);
1034 L2.associative = BITMASK(ecx, 12, 0x0f);
1036 switch (L2.associative){
1041 L2.associative = 16;
1045 L2.linesize = BITMASK(ecx, 0, 0xff);
1050 if ((get_vendor() == VENDOR_AMD) ||
1051 (get_vendor() == VENDOR_HYGON) ||
1052 (get_vendor() == VENDOR_CENTAUR)) {
1053 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1056 LDTB.associative = BITMASK(eax, 24, 0xff);
1057 if (LDTB.associative == 0xff) LDTB.associative = 0;
1058 LDTB.linesize = BITMASK(eax, 16, 0xff);
1061 LITB.associative = BITMASK(eax, 8, 0xff);
1062 if (LITB.associative == 0xff) LITB.associative = 0;
1063 LITB.linesize = BITMASK(eax, 0, 0xff);
1066 DTB.associative = BITMASK(ebx, 24, 0xff);
1067 if (DTB.associative == 0xff) DTB.associative = 0;
1068 DTB.linesize = BITMASK(ebx, 16, 0xff);
1071 ITB.associative = BITMASK(ebx, 8, 0xff);
1072 if (ITB.associative == 0xff) ITB.associative = 0;
1073 ITB.linesize = BITMASK(ebx, 0, 0xff);
1075 LD1.size = BITMASK(ecx, 24, 0xff);
1076 LD1.associative = BITMASK(ecx, 16, 0xff);
1077 if (LD1.associative == 0xff) LD1.associative = 0;
1078 LD1.linesize = BITMASK(ecx, 0, 0xff);
1080 LC1.size = BITMASK(ecx, 24, 0xff);
1081 LC1.associative = BITMASK(ecx, 16, 0xff);
1082 if (LC1.associative == 0xff) LC1.associative = 0;
1083 LC1.linesize = BITMASK(ecx, 0, 0xff);
1085 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1088 L2LDTB.associative = BITMASK(eax, 24, 0xff);
1089 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
1090 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
1093 L2LITB.associative = BITMASK(eax, 8, 0xff);
1094 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
1095 L2LITB.linesize = BITMASK(eax, 0, 0xff);
1098 L2DTB.associative = BITMASK(ebx, 24, 0xff);
1099 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
1100 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
1103 L2ITB.associative = BITMASK(ebx, 8, 0xff);
1104 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
1105 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
1108 //If we didn't detect L2 correctly before,
1109 L2.size = BITMASK(ecx, 16, 0xffff);
1110 L2.associative = BITMASK(ecx, 12, 0xf);
1111 switch (L2.associative){
1116 L2.associative = 16;
1120 if (L2.associative == 0xff) L2.associative = 0;
1121 L2.linesize = BITMASK(ecx, 0, 0xff);
1124 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
1125 L3.associative = BITMASK(edx, 12, 0xf);
1126 if (L3.associative == 0xff) L2.associative = 0;
1127 L3.linesize = BITMASK(edx, 0, 0xff);
1133 case CACHE_INFO_L1_I :
1136 case CACHE_INFO_L1_D :
1139 case CACHE_INFO_L2 :
1142 case CACHE_INFO_L3 :
1145 case CACHE_INFO_L1_DTB :
1148 case CACHE_INFO_L1_ITB :
1151 case CACHE_INFO_L1_LDTB :
1154 case CACHE_INFO_L1_LITB :
1157 case CACHE_INFO_L2_DTB :
1160 case CACHE_INFO_L2_ITB :
1163 case CACHE_INFO_L2_LDTB :
1164 *cacheinfo = L2LDTB;
1166 case CACHE_INFO_L2_LITB :
1167 *cacheinfo = L2LITB;
1173 int get_cpuname(void){
1175 int family, exfamily, model, vendor, exmodel;
1177 if (!have_cpuid()) return CPUTYPE_80386;
1179 family = get_cputype(GET_FAMILY);
1180 exfamily = get_cputype(GET_EXFAMILY);
1181 model = get_cputype(GET_MODEL);
1182 exmodel = get_cputype(GET_EXMODEL);
1184 vendor = get_vendor();
1186 if (vendor == VENDOR_INTEL){
1189 return CPUTYPE_80486;
1191 return CPUTYPE_PENTIUM;
1200 return CPUTYPE_PENTIUM2;
1205 return CPUTYPE_PENTIUM3;
1209 return CPUTYPE_PENTIUMM;
1211 return CPUTYPE_CORE2;
1217 return CPUTYPE_CORE2;
1219 return CPUTYPE_PENRYN;
1224 return CPUTYPE_NEHALEM;
1226 return CPUTYPE_ATOM;
1228 return CPUTYPE_DUNNINGTON;
1234 //Intel Core (Clarkdale) / Core (Arrandale)
1235 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1236 // Xeon (Clarkdale), 32nm
1237 return CPUTYPE_NEHALEM;
1239 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1241 return CPUTYPE_SANDYBRIDGE;
1243 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1245 //Xeon Processor 5600 (Westmere-EP)
1246 return CPUTYPE_NEHALEM;
1248 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1250 return CPUTYPE_SANDYBRIDGE;
1252 return CPUTYPE_NEHALEM;
1256 //Xeon Processor E7 (Westmere-EX)
1257 return CPUTYPE_NEHALEM;
1264 return CPUTYPE_ATOM;
1269 return CPUTYPE_SANDYBRIDGE;
1271 return CPUTYPE_NEHALEM;
1275 return CPUTYPE_HASWELL;
1277 return CPUTYPE_SANDYBRIDGE;
1279 return CPUTYPE_NEHALEM;
1283 return CPUTYPE_HASWELL;
1285 return CPUTYPE_SANDYBRIDGE;
1287 return CPUTYPE_NEHALEM;
1295 return CPUTYPE_HASWELL;
1297 return CPUTYPE_SANDYBRIDGE;
1299 return CPUTYPE_NEHALEM;
1304 return CPUTYPE_HASWELL;
1306 return CPUTYPE_SANDYBRIDGE;
1308 return CPUTYPE_NEHALEM;
1312 return CPUTYPE_HASWELL;
1314 return CPUTYPE_SANDYBRIDGE;
1316 return CPUTYPE_NEHALEM;
1321 return CPUTYPE_NEHALEM;
1329 return CPUTYPE_HASWELL;
1331 return CPUTYPE_SANDYBRIDGE;
1333 return CPUTYPE_NEHALEM;
1336 if(support_avx512())
1337 return CPUTYPE_SKYLAKEX;
1339 return CPUTYPE_HASWELL;
1341 return CPUTYPE_SANDYBRIDGE;
1343 return CPUTYPE_NEHALEM;
1347 return CPUTYPE_HASWELL;
1349 return CPUTYPE_SANDYBRIDGE;
1351 return CPUTYPE_NEHALEM;
1353 // Xeon Phi Knights Landing
1355 return CPUTYPE_HASWELL;
1357 return CPUTYPE_SANDYBRIDGE;
1359 return CPUTYPE_NEHALEM;
1364 return CPUTYPE_NEHALEM;
1369 case 6: // Cannon Lake
1370 if(support_avx512())
1371 return CPUTYPE_SKYLAKEX;
1373 return CPUTYPE_HASWELL;
1375 return CPUTYPE_SANDYBRIDGE;
1377 return CPUTYPE_NEHALEM;
1383 case 14: // Kaby Lake and refreshes
1385 return CPUTYPE_HASWELL;
1387 return CPUTYPE_SANDYBRIDGE;
1389 return CPUTYPE_NEHALEM;
1395 return CPUTYPE_ITANIUM;
1399 return CPUTYPE_PENTIUM4;
1401 return CPUTYPE_ITANIUM;
1405 return CPUTYPE_INTEL_UNKNOWN;
1408 if (vendor == VENDOR_AMD){
1411 return CPUTYPE_AMD5X86;
1413 return CPUTYPE_AMDK6;
1415 return CPUTYPE_ATHLON;
1420 return CPUTYPE_OPTERON;
1425 return CPUTYPE_BARCELONA;
1427 return CPUTYPE_BOBCAT;
1431 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1433 return CPUTYPE_BULLDOZER;
1435 return CPUTYPE_BARCELONA; //OS don't support AVX.
1436 case 2: //AMD Piledriver
1437 case 3: //AMD Richland
1439 return CPUTYPE_PILEDRIVER;
1441 return CPUTYPE_BARCELONA; //OS don't support AVX.
1442 case 5: // New EXCAVATOR CPUS
1444 return CPUTYPE_EXCAVATOR;
1446 return CPUTYPE_BARCELONA; //OS don't support AVX.
1450 case 1: //AMD Trinity
1452 return CPUTYPE_PILEDRIVER;
1454 return CPUTYPE_BARCELONA; //OS don't support AVX.
1457 return CPUTYPE_STEAMROLLER;
1459 return CPUTYPE_BARCELONA; //OS don't support AVX.
1463 return CPUTYPE_EXCAVATOR;
1465 return CPUTYPE_BARCELONA; //OS don't support AVX.
1480 return CPUTYPE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1483 return CPUTYPE_BARCELONA;
1488 return CPUTYPE_AMD_UNKNOWN;
1491 if (vendor == VENDOR_HYGON){
1501 return CPUTYPE_SANDYBRIDGE; // closer in architecture to Sandy Bridge than to Excavator
1504 return CPUTYPE_BARCELONA;
1508 return CPUTYPE_HYGON_UNKNOWN;
1511 if (vendor == VENDOR_CYRIX){
1514 return CPUTYPE_CYRIX5X86;
1516 return CPUTYPE_CYRIXM1;
1518 return CPUTYPE_CYRIXM2;
1520 return CPUTYPE_CYRIX_UNKNOWN;
1523 if (vendor == VENDOR_NEXGEN){
1526 return CPUTYPE_NEXGENNX586;
1528 return CPUTYPE_NEXGEN_UNKNOWN;
1531 if (vendor == VENDOR_CENTAUR){
1534 return CPUTYPE_CENTAURC6;
1537 return CPUTYPE_NANO;
1541 return CPUTYPE_VIAC3;
1544 if (vendor == VENDOR_RISE){
1547 return CPUTYPE_RISEMP6;
1549 return CPUTYPE_RISE_UNKNOWN;
1552 if (vendor == VENDOR_SIS){
1555 return CPUTYPE_SYS55X;
1557 return CPUTYPE_SIS_UNKNOWN;
1560 if (vendor == VENDOR_TRANSMETA){
1563 return CPUTYPE_CRUSOETM3X;
1565 return CPUTYPE_TRANSMETA_UNKNOWN;
1568 if (vendor == VENDOR_NSC){
1571 return CPUTYPE_NSGEODE;
1573 return CPUTYPE_NSC_UNKNOWN;
1576 return CPUTYPE_UNKNOWN;
1579 static char *cpuname[] = {
1589 "TRANSMETA_UNKNOWN",
1636 static char *lowercpuname[] = {
1646 "transmeta_unknown",
1692 static char *corename[] = {
1725 static char *corename_lower[] = {
1759 char *get_cpunamechar(void){
1760 return cpuname[get_cpuname()];
1763 char *get_lower_cpunamechar(void){
1764 return lowercpuname[get_cpuname()];
1768 int get_coretype(void){
1770 int family, exfamily, model, exmodel, vendor;
1772 if (!have_cpuid()) return CORE_80486;
1774 family = get_cputype(GET_FAMILY);
1775 exfamily = get_cputype(GET_EXFAMILY);
1776 model = get_cputype(GET_MODEL);
1777 exmodel = get_cputype(GET_EXMODEL);
1779 vendor = get_vendor();
1781 if (vendor == VENDOR_INTEL){
1804 return CORE_COPPERMINE;
1823 return CORE_NEHALEM;
1827 return CORE_DUNNINGTON;
1833 //Intel Core (Clarkdale) / Core (Arrandale)
1834 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1835 // Xeon (Clarkdale), 32nm
1836 return CORE_NEHALEM;
1838 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1840 return CORE_SANDYBRIDGE;
1842 return CORE_NEHALEM; //OS doesn't support AVX
1844 //Xeon Processor 5600 (Westmere-EP)
1845 return CORE_NEHALEM;
1847 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1849 return CORE_SANDYBRIDGE;
1851 return CORE_NEHALEM; //OS doesn't support AVX
1855 //Xeon Processor E7 (Westmere-EX)
1856 return CORE_NEHALEM;
1866 return CORE_SANDYBRIDGE;
1868 return CORE_NEHALEM; //OS doesn't support AVX
1873 return CORE_HASWELL;
1875 return CORE_SANDYBRIDGE;
1878 return CORE_NEHALEM;
1883 return CORE_HASWELL;
1885 return CORE_SANDYBRIDGE;
1888 return CORE_NEHALEM;
1897 return CORE_HASWELL;
1899 return CORE_SANDYBRIDGE;
1902 return CORE_NEHALEM;
1908 return CORE_HASWELL;
1910 return CORE_SANDYBRIDGE;
1913 return CORE_NEHALEM;
1918 return CORE_HASWELL;
1920 return CORE_SANDYBRIDGE;
1923 return CORE_NEHALEM;
1928 return CORE_NEHALEM;
1937 return CORE_HASWELL;
1939 return CORE_SANDYBRIDGE;
1942 return CORE_NEHALEM;
1946 return CORE_SKYLAKEX;
1950 return CORE_HASWELL;
1952 return CORE_SANDYBRIDGE;
1955 return CORE_NEHALEM;
1961 return CORE_HASWELL;
1963 return CORE_SANDYBRIDGE;
1966 return CORE_NEHALEM;
1968 // Phi Knights Landing
1971 return CORE_HASWELL;
1973 return CORE_SANDYBRIDGE;
1976 return CORE_NEHALEM;
1979 return CORE_NEHALEM;
1984 if (model == 14) { // Kaby Lake
1987 return CORE_HASWELL;
1989 return CORE_SANDYBRIDGE;
1992 return CORE_NEHALEM;
1998 if (model <= 0x2) return CORE_NORTHWOOD;
1999 else return CORE_PRESCOTT;
2003 if (vendor == VENDOR_AMD){
2004 if (family <= 0x5) return CORE_80486;
2005 if (family <= 0xe) return CORE_ATHLON;
2007 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
2008 else if (exfamily == 5) return CORE_BOBCAT;
2009 else if (exfamily == 6) {
2012 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
2014 return CORE_BULLDOZER;
2016 return CORE_BARCELONA; //OS don't support AVX.
2017 case 2: //AMD Piledriver
2018 case 3: //AMD Richland
2020 return CORE_PILEDRIVER;
2022 return CORE_BARCELONA; //OS don't support AVX.
2023 case 5: // New EXCAVATOR
2025 return CORE_EXCAVATOR;
2027 return CORE_BARCELONA; //OS don't support AVX.
2031 case 1: //AMD Trinity
2033 return CORE_PILEDRIVER;
2035 return CORE_BARCELONA; //OS don't support AVX.
2039 return CORE_STEAMROLLER;
2041 return CORE_BARCELONA; //OS don't support AVX.
2045 return CORE_EXCAVATOR;
2047 return CORE_BARCELONA; //OS don't support AVX.
2051 } else if (exfamily == 8) {
2061 return CORE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
2064 return CORE_BARCELONA;
2067 return CORE_BARCELONA;
2072 if (vendor == VENDOR_HYGON){
2074 if (exfamily == 9) {
2079 return CORE_SANDYBRIDGE; // closer in architecture to Sandy Bridge than to Excavator
2082 return CORE_BARCELONA;
2084 return CORE_BARCELONA;
2089 if (vendor == VENDOR_CENTAUR) {
2098 return CORE_UNKNOWN;
2101 void get_cpuconfig(void){
2106 printf("#define %s\n", cpuname[get_cpuname()]);
2109 if (get_coretype() != CORE_P5) {
2111 get_cacheinfo(CACHE_INFO_L1_I, &info);
2112 if (info.size > 0) {
2113 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
2114 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
2115 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
2118 get_cacheinfo(CACHE_INFO_L1_D, &info);
2119 if (info.size > 0) {
2120 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
2121 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
2122 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
2125 get_cacheinfo(CACHE_INFO_L2, &info);
2126 if (info.size > 0) {
2127 printf("#define L2_SIZE %d\n", info.size * 1024);
2128 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
2129 printf("#define L2_LINESIZE %d\n", info.linesize);
2131 //fall back for some virtual machines.
2132 printf("#define L2_SIZE 1048576\n");
2133 printf("#define L2_ASSOCIATIVE 6\n");
2134 printf("#define L2_LINESIZE 64\n");
2138 get_cacheinfo(CACHE_INFO_L3, &info);
2139 if (info.size > 0) {
2140 printf("#define L3_SIZE %d\n", info.size * 1024);
2141 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
2142 printf("#define L3_LINESIZE %d\n", info.linesize);
2145 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
2146 if (info.size > 0) {
2147 printf("#define ITB_SIZE %d\n", info.size * 1024);
2148 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
2149 printf("#define ITB_ENTRIES %d\n", info.linesize);
2152 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
2153 if (info.size > 0) {
2154 printf("#define DTB_SIZE %d\n", info.size * 1024);
2155 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
2156 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
2158 //fall back for some virtual machines.
2159 printf("#define DTB_DEFAULT_ENTRIES 32\n");
2162 features = get_cputype(GET_FEATURE);
2164 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
2165 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
2166 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
2167 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
2168 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
2169 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
2170 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
2171 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
2172 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
2173 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
2174 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
2175 if (features & HAVE_AVX2 ) printf("#define HAVE_AVX2\n");
2176 if (features & HAVE_AVX512VL ) printf("#define HAVE_AVX512VL\n");
2177 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
2178 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
2179 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
2180 if (features & HAVE_FMA3 ) printf("#define HAVE_FMA3\n");
2181 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
2182 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
2183 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
2184 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
2185 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
2187 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
2188 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
2190 features = get_coretype();
2191 if (features > 0) printf("#define CORE_%s\n", corename[features]);
2193 printf("#define DTB_DEFAULT_ENTRIES 16\n");
2194 printf("#define L1_CODE_SIZE 8192\n");
2195 printf("#define L1_DATA_SIZE 8192\n");
2196 printf("#define L2_SIZE 0\n");
2200 void get_architecture(void){
2208 void get_subarchitecture(void){
2209 printf("%s", get_cpunamechar());
2212 void get_subdirname(void){
2220 char *get_corename(void){
2221 return corename[get_coretype()];
2224 void get_libname(void){
2225 printf("%s", corename_lower[get_coretype()]);
2228 /* This if for Makefile */
2233 features = get_cputype(GET_FEATURE);
2235 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
2236 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
2237 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
2238 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
2239 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
2240 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
2241 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
2242 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
2243 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
2244 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
2245 if (features & HAVE_AVX2 ) printf("HAVE_AVX2=1\n");
2246 if (features & HAVE_AVX512VL ) printf("HAVE_AVX512VL=1\n");
2247 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
2248 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
2249 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");
2250 if (features & HAVE_FMA3 ) printf("HAVE_FMA3=1\n");