1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
44 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
45 #define CORE_SANDYBRIDGE CORE_NEHALEM
50 #if defined(__APPLE__) && defined(__i386__)
51 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
53 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
55 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
63 unsigned int id, a, b, c, d;
72 extern idlist_t idlist[];
73 extern vendor_t vendor[];
75 static int cv = VENDOR;
77 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
79 static int current = 0;
81 int start = vendor[cv].start;
82 int stop = vendor[cv].stop;
83 int count = stop - start;
85 if ((current < start) || (current > stop)) current = start;
87 while ((count > 0) && (idlist[current].id != op)) {
90 if (current > stop) current = start;
95 *eax = idlist[current].a;
96 *ebx = idlist[current].b;
97 *ecx = idlist[current].c;
98 *edx = idlist[current].d;
103 static inline int have_cpuid(void){
104 int eax, ebx, ecx, edx;
106 cpuid(0, &eax, &ebx, &ecx, &edx);
110 static inline int have_excpuid(void){
111 int eax, ebx, ecx, edx;
113 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
118 static inline void xgetbv(int op, int * eax, int * edx){
120 ("xgetbv": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
126 int eax, ebx, ecx, edx;
129 cpuid(1, &eax, &ebx, &ecx, &edx);
130 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0){
131 xgetbv(0, &eax, &edx);
133 ret=1; //OS support AVX
143 int get_vendor(void){
144 int eax, ebx, ecx, edx;
147 cpuid(0, &eax, &ebx, &ecx, &edx);
149 *(int *)(&vendor[0]) = ebx;
150 *(int *)(&vendor[4]) = edx;
151 *(int *)(&vendor[8]) = ecx;
152 vendor[12] = (char)0;
154 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
155 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
156 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
157 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
158 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
159 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
160 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
161 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
162 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
163 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
165 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
167 return VENDOR_UNKNOWN;
170 int get_cputype(int gettype){
171 int eax, ebx, ecx, edx;
172 int extend_family, family;
173 int extend_model, model;
177 cpuid(1, &eax, &ebx, &ecx, &edx);
181 return BITMASK(eax, 20, 0xff);
183 return BITMASK(eax, 16, 0x0f);
185 return BITMASK(eax, 12, 0x03);
187 return BITMASK(eax, 8, 0x0f);
189 return BITMASK(eax, 4, 0x0f);
191 return BITMASK(ebx, 24, 0x0f);
193 return BITMASK(ebx, 16, 0x0f);
195 return BITMASK(ebx, 8, 0x0f);
197 return BITMASK(eax, 0, 0x0f);
199 return BITMASK(ebx, 0, 0xff);
201 if (have_cpuid() < 4) return 0;
202 cpuid(4, &eax, &ebx, &ecx, &edx);
203 return BITMASK(eax, 14, 0xfff);
205 if (have_cpuid() < 4) return 0;
206 cpuid(4, &eax, &ebx, &ecx, &edx);
207 return BITMASK(eax, 26, 0x3f);
210 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
211 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
212 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
213 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
214 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
215 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
216 if ((edx & (1 << 27)) != 0) {
217 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
219 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
220 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
221 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
222 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
224 if (support_avx()) feature |= HAVE_AVX;
227 if (have_excpuid() >= 0x01) {
228 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
229 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
230 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
231 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
232 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
235 if (have_excpuid() >= 0x1a) {
236 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
237 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
238 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
245 int get_cacheinfo(int type, cache_info_t *cacheinfo){
246 int eax, ebx, ecx, edx, cpuid_level;
249 cache_info_t LC1, LD1, L2, L3,
250 ITB, DTB, LITB, LDTB,
251 L2ITB, L2DTB, L2LITB, L2LDTB;
253 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
254 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
255 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
256 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
257 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
258 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
259 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
260 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
261 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
262 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
263 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
264 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
266 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
268 if (cpuid_level > 1) {
270 cpuid(2, &eax, &ebx, &ecx, &edx);
272 info[ 0] = BITMASK(eax, 8, 0xff);
273 info[ 1] = BITMASK(eax, 16, 0xff);
274 info[ 2] = BITMASK(eax, 24, 0xff);
276 info[ 3] = BITMASK(ebx, 0, 0xff);
277 info[ 4] = BITMASK(ebx, 8, 0xff);
278 info[ 5] = BITMASK(ebx, 16, 0xff);
279 info[ 6] = BITMASK(ebx, 24, 0xff);
281 info[ 7] = BITMASK(ecx, 0, 0xff);
282 info[ 8] = BITMASK(ecx, 8, 0xff);
283 info[ 9] = BITMASK(ecx, 16, 0xff);
284 info[10] = BITMASK(ecx, 24, 0xff);
286 info[11] = BITMASK(edx, 0, 0xff);
287 info[12] = BITMASK(edx, 8, 0xff);
288 info[13] = BITMASK(edx, 16, 0xff);
289 info[14] = BITMASK(edx, 24, 0xff);
291 for (i = 0; i < 15; i++){
295 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
304 LITB.associative = 0;
314 LDTB.associative = 4;
319 LDTB.associative = 4;
478 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
523 LITB.associative = 0;
532 LITB.associative = 0;
541 LITB.associative = 0;
547 LITB.associative = 0;
553 LDTB.associative = 4;
558 LDTB.associative = 4;
566 LDTB.associative = 0;
575 LDTB.associative = 0;
584 LDTB.associative = 0;
736 L2DTB.associative = 0;
746 LITB.associative = 4;
833 if (get_vendor() == VENDOR_INTEL) {
834 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
835 if (cpuid_level >= 0x80000006) {
836 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
838 L2.size = BITMASK(ecx, 16, 0xffff);
839 L2.associative = BITMASK(ecx, 12, 0x0f);
840 L2.linesize = BITMASK(ecx, 0, 0xff);
844 if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
845 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
848 LDTB.associative = BITMASK(eax, 24, 0xff);
849 if (LDTB.associative == 0xff) LDTB.associative = 0;
850 LDTB.linesize = BITMASK(eax, 16, 0xff);
853 LITB.associative = BITMASK(eax, 8, 0xff);
854 if (LITB.associative == 0xff) LITB.associative = 0;
855 LITB.linesize = BITMASK(eax, 0, 0xff);
858 DTB.associative = BITMASK(ebx, 24, 0xff);
859 if (DTB.associative == 0xff) DTB.associative = 0;
860 DTB.linesize = BITMASK(ebx, 16, 0xff);
863 ITB.associative = BITMASK(ebx, 8, 0xff);
864 if (ITB.associative == 0xff) ITB.associative = 0;
865 ITB.linesize = BITMASK(ebx, 0, 0xff);
867 LD1.size = BITMASK(ecx, 24, 0xff);
868 LD1.associative = BITMASK(ecx, 16, 0xff);
869 if (LD1.associative == 0xff) LD1.associative = 0;
870 LD1.linesize = BITMASK(ecx, 0, 0xff);
872 LC1.size = BITMASK(ecx, 24, 0xff);
873 LC1.associative = BITMASK(ecx, 16, 0xff);
874 if (LC1.associative == 0xff) LC1.associative = 0;
875 LC1.linesize = BITMASK(ecx, 0, 0xff);
877 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
880 L2LDTB.associative = BITMASK(eax, 24, 0xff);
881 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
882 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
885 L2LITB.associative = BITMASK(eax, 8, 0xff);
886 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
887 L2LITB.linesize = BITMASK(eax, 0, 0xff);
890 L2DTB.associative = BITMASK(ebx, 24, 0xff);
891 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
892 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
895 L2ITB.associative = BITMASK(ebx, 8, 0xff);
896 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
897 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
899 L2.size = BITMASK(ecx, 16, 0xffff);
900 L2.associative = BITMASK(ecx, 12, 0xf);
901 if (L2.associative == 0xff) L2.associative = 0;
902 L2.linesize = BITMASK(ecx, 0, 0xff);
904 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
905 L3.associative = BITMASK(edx, 12, 0xf);
906 if (L3.associative == 0xff) L2.associative = 0;
907 L3.linesize = BITMASK(edx, 0, 0xff);
913 case CACHE_INFO_L1_I :
916 case CACHE_INFO_L1_D :
925 case CACHE_INFO_L1_DTB :
928 case CACHE_INFO_L1_ITB :
931 case CACHE_INFO_L1_LDTB :
934 case CACHE_INFO_L1_LITB :
937 case CACHE_INFO_L2_DTB :
940 case CACHE_INFO_L2_ITB :
943 case CACHE_INFO_L2_LDTB :
946 case CACHE_INFO_L2_LITB :
953 int get_cpuname(void){
955 int family, exfamily, model, vendor, exmodel;
957 if (!have_cpuid()) return CPUTYPE_80386;
959 family = get_cputype(GET_FAMILY);
960 exfamily = get_cputype(GET_EXFAMILY);
961 model = get_cputype(GET_MODEL);
962 exmodel = get_cputype(GET_EXMODEL);
964 vendor = get_vendor();
966 if (vendor == VENDOR_INTEL){
969 return CPUTYPE_80486;
971 return CPUTYPE_PENTIUM;
980 return CPUTYPE_PENTIUM2;
985 return CPUTYPE_PENTIUM3;
989 return CPUTYPE_PENTIUMM;
991 return CPUTYPE_CORE2;
997 return CPUTYPE_CORE2;
999 return CPUTYPE_PENRYN;
1004 return CPUTYPE_NEHALEM;
1006 return CPUTYPE_ATOM;
1008 return CPUTYPE_DUNNINGTON;
1014 //Intel Core (Clarkdale) / Core (Arrandale)
1015 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1016 // Xeon (Clarkdale), 32nm
1017 return CPUTYPE_NEHALEM;
1019 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1021 return CPUTYPE_SANDYBRIDGE;
1023 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1025 //Xeon Processor 5600 (Westmere-EP)
1026 return CPUTYPE_NEHALEM;
1028 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1030 return CPUTYPE_SANDYBRIDGE;
1032 return CPUTYPE_NEHALEM;
1034 //Xeon Processor E7 (Westmere-EX)
1035 return CPUTYPE_NEHALEM;
1042 return CPUTYPE_SANDYBRIDGE;
1044 return CPUTYPE_NEHALEM;
1050 return CPUTYPE_ITANIUM;
1054 return CPUTYPE_PENTIUM4;
1056 return CPUTYPE_ITANIUM;
1060 return CPUTYPE_INTEL_UNKNOWN;
1063 if (vendor == VENDOR_AMD){
1066 return CPUTYPE_AMD5X86;
1068 return CPUTYPE_AMDK6;
1070 return CPUTYPE_ATHLON;
1075 return CPUTYPE_OPTERON;
1078 case 6: //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1079 return CPUTYPE_BARCELONA;
1081 return CPUTYPE_BOBCAT;
1085 return CPUTYPE_AMD_UNKNOWN;
1088 if (vendor == VENDOR_CYRIX){
1091 return CPUTYPE_CYRIX5X86;
1093 return CPUTYPE_CYRIXM1;
1095 return CPUTYPE_CYRIXM2;
1097 return CPUTYPE_CYRIX_UNKNOWN;
1100 if (vendor == VENDOR_NEXGEN){
1103 return CPUTYPE_NEXGENNX586;
1105 return CPUTYPE_NEXGEN_UNKNOWN;
1108 if (vendor == VENDOR_CENTAUR){
1111 return CPUTYPE_CENTAURC6;
1114 return CPUTYPE_NANO;
1118 return CPUTYPE_VIAC3;
1121 if (vendor == VENDOR_RISE){
1124 return CPUTYPE_RISEMP6;
1126 return CPUTYPE_RISE_UNKNOWN;
1129 if (vendor == VENDOR_SIS){
1132 return CPUTYPE_SYS55X;
1134 return CPUTYPE_SIS_UNKNOWN;
1137 if (vendor == VENDOR_TRANSMETA){
1140 return CPUTYPE_CRUSOETM3X;
1142 return CPUTYPE_TRANSMETA_UNKNOWN;
1145 if (vendor == VENDOR_NSC){
1148 return CPUTYPE_NSGEODE;
1150 return CPUTYPE_NSC_UNKNOWN;
1153 return CPUTYPE_UNKNOWN;
1156 static char *cpuname[] = {
1166 "TRANSMETA_UNKNOWN",
1206 static char *lowercpuname[] = {
1216 "transmeta_unknown",
1255 static char *corename[] = {
1281 static char *corename_lower[] = {
1308 char *get_cpunamechar(void){
1309 return cpuname[get_cpuname()];
1312 char *get_lower_cpunamechar(void){
1313 return lowercpuname[get_cpuname()];
1317 int get_coretype(void){
1319 int family, exfamily, model, exmodel, vendor;
1321 if (!have_cpuid()) return CORE_80486;
1323 family = get_cputype(GET_FAMILY);
1324 exfamily = get_cputype(GET_EXFAMILY);
1325 model = get_cputype(GET_MODEL);
1326 exmodel = get_cputype(GET_EXMODEL);
1328 vendor = get_vendor();
1330 if (vendor == VENDOR_INTEL){
1353 return CORE_COPPERMINE;
1372 return CORE_NEHALEM;
1376 return CORE_DUNNINGTON;
1382 //Intel Core (Clarkdale) / Core (Arrandale)
1383 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1384 // Xeon (Clarkdale), 32nm
1385 return CORE_NEHALEM;
1387 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1389 return CORE_SANDYBRIDGE;
1391 return CORE_NEHALEM; //OS doesn't support AVX
1393 //Xeon Processor 5600 (Westmere-EP)
1394 return CORE_NEHALEM;
1396 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1398 return CORE_SANDYBRIDGE;
1400 return CORE_NEHALEM; //OS doesn't support AVX
1402 //Xeon Processor E7 (Westmere-EX)
1403 return CORE_NEHALEM;
1410 return CORE_SANDYBRIDGE;
1412 return CORE_NEHALEM; //OS doesn't support AVX
1419 if (model <= 0x2) return CORE_NORTHWOOD;
1420 else return CORE_PRESCOTT;
1424 if (vendor == VENDOR_AMD){
1425 if (family <= 0x5) return CORE_80486;
1426 if (family <= 0xe) return CORE_ATHLON;
1428 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
1429 else if (exfamily == 5) return CORE_BOBCAT;
1430 else if (exfamily == 6) return CORE_BARCELONA; //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1431 else return CORE_BARCELONA;
1435 if (vendor == VENDOR_CENTAUR) {
1444 return CORE_UNKNOWN;
1447 void get_cpuconfig(void){
1452 printf("#define %s\n", cpuname[get_cpuname()]);
1455 if (get_coretype() != CORE_P5) {
1457 get_cacheinfo(CACHE_INFO_L1_I, &info);
1458 if (info.size > 0) {
1459 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
1460 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
1461 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
1464 get_cacheinfo(CACHE_INFO_L1_D, &info);
1465 if (info.size > 0) {
1466 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
1467 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
1468 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
1471 get_cacheinfo(CACHE_INFO_L2, &info);
1472 if (info.size > 0) {
1473 printf("#define L2_SIZE %d\n", info.size * 1024);
1474 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
1475 printf("#define L2_LINESIZE %d\n", info.linesize);
1478 get_cacheinfo(CACHE_INFO_L3, &info);
1479 if (info.size > 0) {
1480 printf("#define L3_SIZE %d\n", info.size * 1024);
1481 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
1482 printf("#define L3_LINESIZE %d\n", info.linesize);
1485 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
1486 if (info.size > 0) {
1487 printf("#define ITB_SIZE %d\n", info.size * 1024);
1488 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
1489 printf("#define ITB_ENTRIES %d\n", info.linesize);
1492 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
1493 if (info.size > 0) {
1494 printf("#define DTB_SIZE %d\n", info.size * 1024);
1495 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
1496 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
1499 features = get_cputype(GET_FEATURE);
1501 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
1502 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
1503 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
1504 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
1505 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
1506 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
1507 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
1508 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
1509 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
1510 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
1511 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
1512 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
1513 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
1514 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
1515 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
1516 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
1517 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
1518 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
1520 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
1521 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
1523 features = get_coretype();
1524 if (features > 0) printf("#define CORE_%s\n", corename[features]);
1526 printf("#define DTB_DEFAULT_ENTRIES 16\n");
1527 printf("#define L1_CODE_SIZE 8192\n");
1528 printf("#define L1_DATA_SIZE 8192\n");
1529 printf("#define L2_SIZE 0\n");
1533 void get_architecture(void){
1541 void get_subarchitecture(void){
1542 printf("%s", get_cpunamechar());
1545 void get_subdirname(void){
1553 char *get_corename(void){
1554 return corename[get_coretype()];
1557 void get_libname(void){
1558 printf("%s", corename_lower[get_coretype()]);
1561 /* This if for Makefile */
1566 features = get_cputype(GET_FEATURE);
1568 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
1569 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
1570 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
1571 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
1572 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
1573 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
1574 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
1575 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
1576 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
1577 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
1578 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
1579 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");