1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
43 #if defined(_MSC_VER) && !defined(__clang__)
44 #define C_INLINE __inline
46 #define C_INLINE inline
51 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
52 #define CORE_HASWELL CORE_NEHALEM
53 #define CPUTYPE_SKYLAKEX CPUTYPE_NEHALEM
54 #define CORE_SKYLAKEX CORE_NEHALEM
55 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
56 #define CORE_SANDYBRIDGE CORE_NEHALEM
57 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
58 #define CORE_BULLDOZER CORE_BARCELONA
59 #define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
60 #define CORE_PILEDRIVER CORE_BARCELONA
64 #if defined(_MSC_VER) && !defined(__clang__)
66 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
68 int cpuInfo[4] = {-1};
76 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx)
78 int cpuInfo[4] = {-1};
79 __cpuidex(cpuInfo, op, count);
90 #if defined(__APPLE__) && defined(__i386__)
91 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
92 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx);
94 static C_INLINE void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
95 #if defined(__i386__) && defined(__PIC__)
100 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
103 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
107 static C_INLINE void cpuid_count(int op, int count ,int *eax, int *ebx, int *ecx, int *edx){
108 #if defined(__i386__) && defined(__PIC__)
112 "xchgl %%ebx, %%edi;"
113 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
116 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
124 unsigned int id, a, b, c, d;
133 extern idlist_t idlist[];
134 extern vendor_t vendor[];
136 static int cv = VENDOR;
138 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
140 static int current = 0;
142 int start = vendor[cv].start;
143 int stop = vendor[cv].stop;
144 int count = stop - start;
146 if ((current < start) || (current > stop)) current = start;
148 while ((count > 0) && (idlist[current].id != op)) {
151 if (current > stop) current = start;
156 *eax = idlist[current].a;
157 *ebx = idlist[current].b;
158 *ecx = idlist[current].c;
159 *edx = idlist[current].d;
162 void cpuid_count (unsigned int op, unsigned int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
163 return cpuid (op, eax, ebx, ecx, edx);
170 static C_INLINE int have_cpuid(void){
171 int eax, ebx, ecx, edx;
173 cpuid(0, &eax, &ebx, &ecx, &edx);
177 static C_INLINE int have_excpuid(void){
178 int eax, ebx, ecx, edx;
180 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
185 static C_INLINE void xgetbv(int op, int * eax, int * edx){
186 //Use binary code for xgetbv
187 #if defined(_MSC_VER) && !defined(__clang__)
191 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
198 int eax, ebx, ecx, edx;
201 cpuid(1, &eax, &ebx, &ecx, &edx);
202 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
203 xgetbv(0, &eax, &edx);
205 ret=1; //OS support AVX
215 int get_vendor(void){
216 int eax, ebx, ecx, edx;
219 cpuid(0, &eax, &ebx, &ecx, &edx);
221 *(int *)(&vendor[0]) = ebx;
222 *(int *)(&vendor[4]) = edx;
223 *(int *)(&vendor[8]) = ecx;
224 vendor[12] = (char)0;
226 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
227 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
228 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
229 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
230 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
231 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
232 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
233 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
234 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
235 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
237 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
239 return VENDOR_UNKNOWN;
242 int get_cputype(int gettype){
243 int eax, ebx, ecx, edx;
244 int extend_family, family;
245 int extend_model, model;
249 cpuid(1, &eax, &ebx, &ecx, &edx);
253 return BITMASK(eax, 20, 0xff);
255 return BITMASK(eax, 16, 0x0f);
257 return BITMASK(eax, 12, 0x03);
259 return BITMASK(eax, 8, 0x0f);
261 return BITMASK(eax, 4, 0x0f);
263 return BITMASK(ebx, 24, 0x0f);
265 return BITMASK(ebx, 16, 0x0f);
267 return BITMASK(ebx, 8, 0x0f);
269 return BITMASK(eax, 0, 0x0f);
271 return BITMASK(ebx, 0, 0xff);
273 if (have_cpuid() < 4) return 0;
274 cpuid(4, &eax, &ebx, &ecx, &edx);
275 return BITMASK(eax, 14, 0xfff);
277 if (have_cpuid() < 4) return 0;
278 cpuid(4, &eax, &ebx, &ecx, &edx);
279 return BITMASK(eax, 26, 0x3f);
282 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
283 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
284 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
285 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
286 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
287 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
288 if ((edx & (1 << 27)) != 0) {
289 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
291 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
292 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
293 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
294 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
296 if (support_avx()) feature |= HAVE_AVX;
297 if ((ecx & (1 << 12)) != 0) feature |= HAVE_FMA3;
300 if (have_excpuid() >= 0x01) {
301 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
302 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
303 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
305 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
307 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
308 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
311 if (have_excpuid() >= 0x1a) {
312 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
313 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
314 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
321 int get_cacheinfo(int type, cache_info_t *cacheinfo){
322 int eax, ebx, ecx, edx, cpuid_level;
325 cache_info_t LC1, LD1, L2, L3,
326 ITB, DTB, LITB, LDTB,
327 L2ITB, L2DTB, L2LITB, L2LDTB;
329 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
330 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
331 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
332 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
333 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
334 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
335 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
336 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
337 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
338 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
339 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
340 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
342 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
344 if (cpuid_level > 1) {
346 cpuid(2, &eax, &ebx, &ecx, &edx);
347 numcalls = BITMASK(eax, 0, 0xff); //FIXME some systems may require repeated calls to read all entries
348 info[ 0] = BITMASK(eax, 8, 0xff);
349 info[ 1] = BITMASK(eax, 16, 0xff);
350 info[ 2] = BITMASK(eax, 24, 0xff);
352 info[ 3] = BITMASK(ebx, 0, 0xff);
353 info[ 4] = BITMASK(ebx, 8, 0xff);
354 info[ 5] = BITMASK(ebx, 16, 0xff);
355 info[ 6] = BITMASK(ebx, 24, 0xff);
357 info[ 7] = BITMASK(ecx, 0, 0xff);
358 info[ 8] = BITMASK(ecx, 8, 0xff);
359 info[ 9] = BITMASK(ecx, 16, 0xff);
360 info[10] = BITMASK(ecx, 24, 0xff);
362 info[11] = BITMASK(edx, 0, 0xff);
363 info[12] = BITMASK(edx, 8, 0xff);
364 info[13] = BITMASK(edx, 16, 0xff);
365 info[14] = BITMASK(edx, 24, 0xff);
367 for (i = 0; i < 15; i++){
370 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
379 LITB.associative = 0;
389 LDTB.associative = 4;
394 LDTB.associative = 4;
553 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
598 LITB.associative = 0;
607 LITB.associative = 0;
616 LITB.associative = 0;
622 LITB.associative = 0;
628 LDTB.associative = 4;
633 LDTB.associative = 4;
641 LDTB.associative = 0;
650 LDTB.associative = 0;
659 LDTB.associative = 0;
827 L2DTB.associative = 0;
837 LITB.associative = 4;
924 if (get_vendor() == VENDOR_INTEL) {
925 if(LD1.size<=0 || LC1.size<=0){
926 //If we didn't detect L1 correctly before,
928 for (count=0;count <4;count++) {
929 cpuid_count(4, count, &eax, &ebx, &ecx, &edx);
936 switch ((eax >>5) &0x07)
940 // fprintf(stderr,"L1 data cache...\n");
942 int lines = (ebx & 0x0fff) +1;
944 int part = (ebx&0x03ff)+1;
946 int assoc = (ebx&0x03ff)+1;
947 LD1.size = (assoc*part*lines*sets)/1024;
948 LD1.associative = assoc;
959 switch ((eax >>5) &0x07)
963 // fprintf(stderr,"L1 instruction cache...\n");
965 int lines = (ebx & 0x0fff) +1;
967 int part = (ebx&0x03ff)+1;
969 int assoc = (ebx&0x03ff)+1;
970 LC1.size = (assoc*part*lines*sets)/1024;
971 LC1.associative = assoc;
986 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
987 if (cpuid_level >= 0x80000006) {
989 //If we didn't detect L2 correctly before,
990 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
992 L2.size = BITMASK(ecx, 16, 0xffff);
993 L2.associative = BITMASK(ecx, 12, 0x0f);
995 switch (L2.associative){
1000 L2.associative = 16;
1004 L2.linesize = BITMASK(ecx, 0, 0xff);
1009 if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
1010 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1013 LDTB.associative = BITMASK(eax, 24, 0xff);
1014 if (LDTB.associative == 0xff) LDTB.associative = 0;
1015 LDTB.linesize = BITMASK(eax, 16, 0xff);
1018 LITB.associative = BITMASK(eax, 8, 0xff);
1019 if (LITB.associative == 0xff) LITB.associative = 0;
1020 LITB.linesize = BITMASK(eax, 0, 0xff);
1023 DTB.associative = BITMASK(ebx, 24, 0xff);
1024 if (DTB.associative == 0xff) DTB.associative = 0;
1025 DTB.linesize = BITMASK(ebx, 16, 0xff);
1028 ITB.associative = BITMASK(ebx, 8, 0xff);
1029 if (ITB.associative == 0xff) ITB.associative = 0;
1030 ITB.linesize = BITMASK(ebx, 0, 0xff);
1032 LD1.size = BITMASK(ecx, 24, 0xff);
1033 LD1.associative = BITMASK(ecx, 16, 0xff);
1034 if (LD1.associative == 0xff) LD1.associative = 0;
1035 LD1.linesize = BITMASK(ecx, 0, 0xff);
1037 LC1.size = BITMASK(ecx, 24, 0xff);
1038 LC1.associative = BITMASK(ecx, 16, 0xff);
1039 if (LC1.associative == 0xff) LC1.associative = 0;
1040 LC1.linesize = BITMASK(ecx, 0, 0xff);
1042 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1045 L2LDTB.associative = BITMASK(eax, 24, 0xff);
1046 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
1047 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
1050 L2LITB.associative = BITMASK(eax, 8, 0xff);
1051 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
1052 L2LITB.linesize = BITMASK(eax, 0, 0xff);
1055 L2DTB.associative = BITMASK(ebx, 24, 0xff);
1056 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
1057 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
1060 L2ITB.associative = BITMASK(ebx, 8, 0xff);
1061 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
1062 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
1065 //If we didn't detect L2 correctly before,
1066 L2.size = BITMASK(ecx, 16, 0xffff);
1067 L2.associative = BITMASK(ecx, 12, 0xf);
1068 switch (L2.associative){
1073 L2.associative = 16;
1077 if (L2.associative == 0xff) L2.associative = 0;
1078 L2.linesize = BITMASK(ecx, 0, 0xff);
1081 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
1082 L3.associative = BITMASK(edx, 12, 0xf);
1083 if (L3.associative == 0xff) L2.associative = 0;
1084 L3.linesize = BITMASK(edx, 0, 0xff);
1090 case CACHE_INFO_L1_I :
1093 case CACHE_INFO_L1_D :
1096 case CACHE_INFO_L2 :
1099 case CACHE_INFO_L3 :
1102 case CACHE_INFO_L1_DTB :
1105 case CACHE_INFO_L1_ITB :
1108 case CACHE_INFO_L1_LDTB :
1111 case CACHE_INFO_L1_LITB :
1114 case CACHE_INFO_L2_DTB :
1117 case CACHE_INFO_L2_ITB :
1120 case CACHE_INFO_L2_LDTB :
1121 *cacheinfo = L2LDTB;
1123 case CACHE_INFO_L2_LITB :
1124 *cacheinfo = L2LITB;
1130 int get_cpuname(void){
1132 int family, exfamily, model, vendor, exmodel;
1134 if (!have_cpuid()) return CPUTYPE_80386;
1136 family = get_cputype(GET_FAMILY);
1137 exfamily = get_cputype(GET_EXFAMILY);
1138 model = get_cputype(GET_MODEL);
1139 exmodel = get_cputype(GET_EXMODEL);
1141 vendor = get_vendor();
1143 if (vendor == VENDOR_INTEL){
1146 return CPUTYPE_80486;
1148 return CPUTYPE_PENTIUM;
1157 return CPUTYPE_PENTIUM2;
1162 return CPUTYPE_PENTIUM3;
1166 return CPUTYPE_PENTIUMM;
1168 return CPUTYPE_CORE2;
1174 return CPUTYPE_CORE2;
1176 return CPUTYPE_PENRYN;
1181 return CPUTYPE_NEHALEM;
1183 return CPUTYPE_ATOM;
1185 return CPUTYPE_DUNNINGTON;
1191 //Intel Core (Clarkdale) / Core (Arrandale)
1192 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1193 // Xeon (Clarkdale), 32nm
1194 return CPUTYPE_NEHALEM;
1196 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1198 return CPUTYPE_SANDYBRIDGE;
1200 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1202 //Xeon Processor 5600 (Westmere-EP)
1203 return CPUTYPE_NEHALEM;
1205 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1207 return CPUTYPE_SANDYBRIDGE;
1209 return CPUTYPE_NEHALEM;
1213 //Xeon Processor E7 (Westmere-EX)
1214 return CPUTYPE_NEHALEM;
1221 return CPUTYPE_ATOM;
1226 return CPUTYPE_SANDYBRIDGE;
1228 return CPUTYPE_NEHALEM;
1233 return CPUTYPE_HASWELL;
1235 return CPUTYPE_SANDYBRIDGE;
1238 return CPUTYPE_NEHALEM;
1243 return CPUTYPE_HASWELL;
1245 return CPUTYPE_SANDYBRIDGE;
1248 return CPUTYPE_NEHALEM;
1257 return CPUTYPE_HASWELL;
1259 return CPUTYPE_SANDYBRIDGE;
1262 return CPUTYPE_NEHALEM;
1268 return CPUTYPE_HASWELL;
1270 return CPUTYPE_SANDYBRIDGE;
1273 return CPUTYPE_NEHALEM;
1278 return CPUTYPE_HASWELL;
1280 return CPUTYPE_SANDYBRIDGE;
1283 return CPUTYPE_NEHALEM;
1288 return CPUTYPE_NEHALEM;
1297 return CPUTYPE_HASWELL;
1299 return CPUTYPE_SANDYBRIDGE;
1302 return CPUTYPE_NEHALEM;
1306 return CPUTYPE_SKYLAKEX;
1310 return CPUTYPE_HASWELL;
1312 return CPUTYPE_SANDYBRIDGE;
1315 return CPUTYPE_NEHALEM;
1321 return CPUTYPE_HASWELL;
1323 return CPUTYPE_SANDYBRIDGE;
1326 return CPUTYPE_NEHALEM;
1328 // Xeon Phi Knights Landing
1331 return CPUTYPE_HASWELL;
1333 return CPUTYPE_SANDYBRIDGE;
1336 return CPUTYPE_NEHALEM;
1339 return CPUTYPE_NEHALEM;
1344 case 6: // Cannon Lake
1346 return CPUTYPE_SKYLAKEX;
1350 return CPUTYPE_HASWELL;
1352 return CPUTYPE_SANDYBRIDGE;
1355 return CPUTYPE_NEHALEM;
1362 case 14: // Kaby Lake
1365 return CPUTYPE_HASWELL;
1367 return CPUTYPE_SANDYBRIDGE;
1370 return CPUTYPE_NEHALEM;
1376 return CPUTYPE_ITANIUM;
1380 return CPUTYPE_PENTIUM4;
1382 return CPUTYPE_ITANIUM;
1386 return CPUTYPE_INTEL_UNKNOWN;
1389 if (vendor == VENDOR_AMD){
1392 return CPUTYPE_AMD5X86;
1394 return CPUTYPE_AMDK6;
1396 return CPUTYPE_ATHLON;
1401 return CPUTYPE_OPTERON;
1406 return CPUTYPE_BARCELONA;
1408 return CPUTYPE_BOBCAT;
1412 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1414 return CPUTYPE_BULLDOZER;
1416 return CPUTYPE_BARCELONA; //OS don't support AVX.
1417 case 2: //AMD Piledriver
1418 case 3: //AMD Richland
1420 return CPUTYPE_PILEDRIVER;
1422 return CPUTYPE_BARCELONA; //OS don't support AVX.
1423 case 5: // New EXCAVATOR CPUS
1425 return CPUTYPE_EXCAVATOR;
1427 return CPUTYPE_BARCELONA; //OS don't support AVX.
1431 case 1: //AMD Trinity
1433 return CPUTYPE_PILEDRIVER;
1435 return CPUTYPE_BARCELONA; //OS don't support AVX.
1438 return CPUTYPE_STEAMROLLER;
1440 return CPUTYPE_BARCELONA; //OS don't support AVX.
1444 return CPUTYPE_EXCAVATOR;
1446 return CPUTYPE_BARCELONA; //OS don't support AVX.
1461 return CPUTYPE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1464 return CPUTYPE_BARCELONA;
1469 return CPUTYPE_AMD_UNKNOWN;
1472 if (vendor == VENDOR_CYRIX){
1475 return CPUTYPE_CYRIX5X86;
1477 return CPUTYPE_CYRIXM1;
1479 return CPUTYPE_CYRIXM2;
1481 return CPUTYPE_CYRIX_UNKNOWN;
1484 if (vendor == VENDOR_NEXGEN){
1487 return CPUTYPE_NEXGENNX586;
1489 return CPUTYPE_NEXGEN_UNKNOWN;
1492 if (vendor == VENDOR_CENTAUR){
1495 return CPUTYPE_CENTAURC6;
1498 return CPUTYPE_NANO;
1502 return CPUTYPE_VIAC3;
1505 if (vendor == VENDOR_RISE){
1508 return CPUTYPE_RISEMP6;
1510 return CPUTYPE_RISE_UNKNOWN;
1513 if (vendor == VENDOR_SIS){
1516 return CPUTYPE_SYS55X;
1518 return CPUTYPE_SIS_UNKNOWN;
1521 if (vendor == VENDOR_TRANSMETA){
1524 return CPUTYPE_CRUSOETM3X;
1526 return CPUTYPE_TRANSMETA_UNKNOWN;
1529 if (vendor == VENDOR_NSC){
1532 return CPUTYPE_NSGEODE;
1534 return CPUTYPE_NSC_UNKNOWN;
1537 return CPUTYPE_UNKNOWN;
1540 static char *cpuname[] = {
1550 "TRANSMETA_UNKNOWN",
1596 static char *lowercpuname[] = {
1606 "transmeta_unknown",
1651 static char *corename[] = {
1683 static char *corename_lower[] = {
1716 char *get_cpunamechar(void){
1717 return cpuname[get_cpuname()];
1720 char *get_lower_cpunamechar(void){
1721 return lowercpuname[get_cpuname()];
1725 int get_coretype(void){
1727 int family, exfamily, model, exmodel, vendor;
1729 if (!have_cpuid()) return CORE_80486;
1731 family = get_cputype(GET_FAMILY);
1732 exfamily = get_cputype(GET_EXFAMILY);
1733 model = get_cputype(GET_MODEL);
1734 exmodel = get_cputype(GET_EXMODEL);
1736 vendor = get_vendor();
1738 if (vendor == VENDOR_INTEL){
1761 return CORE_COPPERMINE;
1780 return CORE_NEHALEM;
1784 return CORE_DUNNINGTON;
1790 //Intel Core (Clarkdale) / Core (Arrandale)
1791 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1792 // Xeon (Clarkdale), 32nm
1793 return CORE_NEHALEM;
1795 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1797 return CORE_SANDYBRIDGE;
1799 return CORE_NEHALEM; //OS doesn't support AVX
1801 //Xeon Processor 5600 (Westmere-EP)
1802 return CORE_NEHALEM;
1804 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1806 return CORE_SANDYBRIDGE;
1808 return CORE_NEHALEM; //OS doesn't support AVX
1812 //Xeon Processor E7 (Westmere-EX)
1813 return CORE_NEHALEM;
1823 return CORE_SANDYBRIDGE;
1825 return CORE_NEHALEM; //OS doesn't support AVX
1830 return CORE_HASWELL;
1832 return CORE_SANDYBRIDGE;
1835 return CORE_NEHALEM;
1840 return CORE_HASWELL;
1842 return CORE_SANDYBRIDGE;
1845 return CORE_NEHALEM;
1854 return CORE_HASWELL;
1856 return CORE_SANDYBRIDGE;
1859 return CORE_NEHALEM;
1865 return CORE_HASWELL;
1867 return CORE_SANDYBRIDGE;
1870 return CORE_NEHALEM;
1875 return CORE_HASWELL;
1877 return CORE_SANDYBRIDGE;
1880 return CORE_NEHALEM;
1885 return CORE_NEHALEM;
1894 return CORE_HASWELL;
1896 return CORE_SANDYBRIDGE;
1899 return CORE_NEHALEM;
1903 return CORE_SKYLAKEX;
1907 return CORE_HASWELL;
1909 return CORE_SANDYBRIDGE;
1912 return CORE_NEHALEM;
1918 return CORE_HASWELL;
1920 return CORE_SANDYBRIDGE;
1923 return CORE_NEHALEM;
1925 // Phi Knights Landing
1928 return CORE_HASWELL;
1930 return CORE_SANDYBRIDGE;
1933 return CORE_NEHALEM;
1936 return CORE_NEHALEM;
1941 if (model == 14) { // Kaby Lake
1944 return CORE_HASWELL;
1946 return CORE_SANDYBRIDGE;
1949 return CORE_NEHALEM;
1955 if (model <= 0x2) return CORE_NORTHWOOD;
1956 else return CORE_PRESCOTT;
1960 if (vendor == VENDOR_AMD){
1961 if (family <= 0x5) return CORE_80486;
1962 if (family <= 0xe) return CORE_ATHLON;
1964 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
1965 else if (exfamily == 5) return CORE_BOBCAT;
1966 else if (exfamily == 6) {
1969 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1971 return CORE_BULLDOZER;
1973 return CORE_BARCELONA; //OS don't support AVX.
1974 case 2: //AMD Piledriver
1975 case 3: //AMD Richland
1977 return CORE_PILEDRIVER;
1979 return CORE_BARCELONA; //OS don't support AVX.
1980 case 5: // New EXCAVATOR
1982 return CORE_EXCAVATOR;
1984 return CORE_BARCELONA; //OS don't support AVX.
1988 case 1: //AMD Trinity
1990 return CORE_PILEDRIVER;
1992 return CORE_BARCELONA; //OS don't support AVX.
1996 return CORE_STEAMROLLER;
1998 return CORE_BARCELONA; //OS don't support AVX.
2002 return CORE_EXCAVATOR;
2004 return CORE_BARCELONA; //OS don't support AVX.
2008 } else if (exfamily == 8) {
2016 return CORE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
2019 return CORE_BARCELONA;
2022 return CORE_BARCELONA;
2027 if (vendor == VENDOR_CENTAUR) {
2036 return CORE_UNKNOWN;
2039 void get_cpuconfig(void){
2044 printf("#define %s\n", cpuname[get_cpuname()]);
2047 if (get_coretype() != CORE_P5) {
2049 get_cacheinfo(CACHE_INFO_L1_I, &info);
2050 if (info.size > 0) {
2051 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
2052 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
2053 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
2056 get_cacheinfo(CACHE_INFO_L1_D, &info);
2057 if (info.size > 0) {
2058 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
2059 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
2060 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
2063 get_cacheinfo(CACHE_INFO_L2, &info);
2064 if (info.size > 0) {
2065 printf("#define L2_SIZE %d\n", info.size * 1024);
2066 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
2067 printf("#define L2_LINESIZE %d\n", info.linesize);
2069 //fall back for some virtual machines.
2070 printf("#define L2_SIZE 1048576\n");
2071 printf("#define L2_ASSOCIATIVE 6\n");
2072 printf("#define L2_LINESIZE 64\n");
2076 get_cacheinfo(CACHE_INFO_L3, &info);
2077 if (info.size > 0) {
2078 printf("#define L3_SIZE %d\n", info.size * 1024);
2079 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
2080 printf("#define L3_LINESIZE %d\n", info.linesize);
2083 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
2084 if (info.size > 0) {
2085 printf("#define ITB_SIZE %d\n", info.size * 1024);
2086 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
2087 printf("#define ITB_ENTRIES %d\n", info.linesize);
2090 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
2091 if (info.size > 0) {
2092 printf("#define DTB_SIZE %d\n", info.size * 1024);
2093 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
2094 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
2096 //fall back for some virtual machines.
2097 printf("#define DTB_DEFAULT_ENTRIES 32\n");
2100 features = get_cputype(GET_FEATURE);
2102 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
2103 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
2104 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
2105 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
2106 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
2107 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
2108 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
2109 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
2110 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
2111 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
2112 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
2113 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
2114 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
2115 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
2116 if (features & HAVE_FMA3 ) printf("#define HAVE_FMA3\n");
2117 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
2118 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
2119 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
2120 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
2121 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
2123 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
2124 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
2126 features = get_coretype();
2127 if (features > 0) printf("#define CORE_%s\n", corename[features]);
2129 printf("#define DTB_DEFAULT_ENTRIES 16\n");
2130 printf("#define L1_CODE_SIZE 8192\n");
2131 printf("#define L1_DATA_SIZE 8192\n");
2132 printf("#define L2_SIZE 0\n");
2136 void get_architecture(void){
2144 void get_subarchitecture(void){
2145 printf("%s", get_cpunamechar());
2148 void get_subdirname(void){
2156 char *get_corename(void){
2157 return corename[get_coretype()];
2160 void get_libname(void){
2161 printf("%s", corename_lower[get_coretype()]);
2164 /* This if for Makefile */
2169 features = get_cputype(GET_FEATURE);
2171 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
2172 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
2173 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
2174 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
2175 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
2176 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
2177 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
2178 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
2179 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
2180 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
2181 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
2182 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
2183 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");
2184 if (features & HAVE_FMA3 ) printf("HAVE_FMA3=1\n");