1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin. */
3 /* All rights reserved. */
5 /* Redistribution and use in source and binary forms, with or */
6 /* without modification, are permitted provided that the following */
7 /* conditions are met: */
9 /* 1. Redistributions of source code must retain the above */
10 /* copyright notice, this list of conditions and the following */
13 /* 2. Redistributions in binary form must reproduce the above */
14 /* copyright notice, this list of conditions and the following */
15 /* disclaimer in the documentation and/or other materials */
16 /* provided with the distribution. */
18 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
19 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
20 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
21 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
22 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
23 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
24 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
25 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
26 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
27 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
28 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
29 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
30 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
31 /* POSSIBILITY OF SUCH DAMAGE. */
33 /* The views and conclusions contained in the software and */
34 /* documentation are those of the authors and should not be */
35 /* interpreted as representing official policies, either expressed */
36 /* or implied, of The University of Texas at Austin. */
37 /*********************************************************************/
43 #if defined(_MSC_VER) && !defined(__clang__)
44 #define C_INLINE __inline
46 #define C_INLINE inline
51 #define CPUTYPE_HASWELL CPUTYPE_NEHALEM
52 #define CORE_HASWELL CORE_NEHALEM
53 #define CPUTYPE_SANDYBRIDGE CPUTYPE_NEHALEM
54 #define CORE_SANDYBRIDGE CORE_NEHALEM
55 #define CPUTYPE_BULLDOZER CPUTYPE_BARCELONA
56 #define CORE_BULLDOZER CORE_BARCELONA
57 #define CPUTYPE_PILEDRIVER CPUTYPE_BARCELONA
58 #define CORE_PILEDRIVER CORE_BARCELONA
62 #if defined(_MSC_VER) && !defined(__clang__)
64 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
66 int cpuInfo[4] = {-1};
74 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx)
76 int cpuInfo[4] = {-1};
77 __cpuidex(cpuInfo, op, count);
88 #if defined(__APPLE__) && defined(__i386__)
89 void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx);
90 void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, int *edx);
92 static C_INLINE void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx){
93 #if defined(__i386__) && defined(__PIC__)
98 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
101 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (op) : "cc");
105 static C_INLINE void cpuid_count(int op, int count ,int *eax, int *ebx, int *ecx, int *edx){
106 #if defined(__i386__) && defined(__PIC__)
110 "xchgl %%ebx, %%edi;"
111 : "=a" (*eax), "=D" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
114 ("cpuid": "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "2" (count) : "cc");
122 unsigned int id, a, b, c, d;
131 extern idlist_t idlist[];
132 extern vendor_t vendor[];
134 static int cv = VENDOR;
136 void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx){
138 static int current = 0;
140 int start = vendor[cv].start;
141 int stop = vendor[cv].stop;
142 int count = stop - start;
144 if ((current < start) || (current > stop)) current = start;
146 while ((count > 0) && (idlist[current].id != op)) {
149 if (current > stop) current = start;
154 *eax = idlist[current].a;
155 *ebx = idlist[current].b;
156 *ecx = idlist[current].c;
157 *edx = idlist[current].d;
160 void cpuid_count (unsigned int op, unsigned int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
161 return cpuid (op, eax, ebx, ecx, edx);
168 static C_INLINE int have_cpuid(void){
169 int eax, ebx, ecx, edx;
171 cpuid(0, &eax, &ebx, &ecx, &edx);
175 static C_INLINE int have_excpuid(void){
176 int eax, ebx, ecx, edx;
178 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
183 static C_INLINE void xgetbv(int op, int * eax, int * edx){
184 //Use binary code for xgetbv
185 #if defined(_MSC_VER) && !defined(__clang__)
189 (".byte 0x0f, 0x01, 0xd0": "=a" (*eax), "=d" (*edx) : "c" (op) : "cc");
196 int eax, ebx, ecx, edx;
199 cpuid(1, &eax, &ebx, &ecx, &edx);
200 if ((ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0){
201 xgetbv(0, &eax, &edx);
203 ret=1; //OS support AVX
213 int get_vendor(void){
214 int eax, ebx, ecx, edx;
217 cpuid(0, &eax, &ebx, &ecx, &edx);
219 *(int *)(&vendor[0]) = ebx;
220 *(int *)(&vendor[4]) = edx;
221 *(int *)(&vendor[8]) = ecx;
222 vendor[12] = (char)0;
224 if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
225 if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
226 if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
227 if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
228 if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
229 if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
230 if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
231 if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
232 if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
233 if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
235 if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
237 return VENDOR_UNKNOWN;
240 int get_cputype(int gettype){
241 int eax, ebx, ecx, edx;
242 int extend_family, family;
243 int extend_model, model;
247 cpuid(1, &eax, &ebx, &ecx, &edx);
251 return BITMASK(eax, 20, 0xff);
253 return BITMASK(eax, 16, 0x0f);
255 return BITMASK(eax, 12, 0x03);
257 return BITMASK(eax, 8, 0x0f);
259 return BITMASK(eax, 4, 0x0f);
261 return BITMASK(ebx, 24, 0x0f);
263 return BITMASK(ebx, 16, 0x0f);
265 return BITMASK(ebx, 8, 0x0f);
267 return BITMASK(eax, 0, 0x0f);
269 return BITMASK(ebx, 0, 0xff);
271 if (have_cpuid() < 4) return 0;
272 cpuid(4, &eax, &ebx, &ecx, &edx);
273 return BITMASK(eax, 14, 0xfff);
275 if (have_cpuid() < 4) return 0;
276 cpuid(4, &eax, &ebx, &ecx, &edx);
277 return BITMASK(eax, 26, 0x3f);
280 if ((edx & (1 << 3)) != 0) feature |= HAVE_PSE;
281 if ((edx & (1 << 15)) != 0) feature |= HAVE_CMOV;
282 if ((edx & (1 << 19)) != 0) feature |= HAVE_CFLUSH;
283 if ((edx & (1 << 23)) != 0) feature |= HAVE_MMX;
284 if ((edx & (1 << 25)) != 0) feature |= HAVE_SSE;
285 if ((edx & (1 << 26)) != 0) feature |= HAVE_SSE2;
286 if ((edx & (1 << 27)) != 0) {
287 if (BITMASK(ebx, 16, 0x0f) > 0) feature |= HAVE_HIT;
289 if ((ecx & (1 << 0)) != 0) feature |= HAVE_SSE3;
290 if ((ecx & (1 << 9)) != 0) feature |= HAVE_SSSE3;
291 if ((ecx & (1 << 19)) != 0) feature |= HAVE_SSE4_1;
292 if ((ecx & (1 << 20)) != 0) feature |= HAVE_SSE4_2;
294 if (support_avx()) feature |= HAVE_AVX;
295 if ((ecx & (1 << 12)) != 0) feature |= HAVE_FMA3;
298 if (have_excpuid() >= 0x01) {
299 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
300 if ((ecx & (1 << 6)) != 0) feature |= HAVE_SSE4A;
301 if ((ecx & (1 << 7)) != 0) feature |= HAVE_MISALIGNSSE;
303 if ((ecx & (1 << 16)) != 0) feature |= HAVE_FMA4;
305 if ((edx & (1 << 30)) != 0) feature |= HAVE_3DNOWEX;
306 if ((edx & (1 << 31)) != 0) feature |= HAVE_3DNOW;
309 if (have_excpuid() >= 0x1a) {
310 cpuid(0x8000001a, &eax, &ebx, &ecx, &edx);
311 if ((eax & (1 << 0)) != 0) feature |= HAVE_128BITFPU;
312 if ((eax & (1 << 1)) != 0) feature |= HAVE_FASTMOVU;
319 int get_cacheinfo(int type, cache_info_t *cacheinfo){
320 int eax, ebx, ecx, edx, cpuid_level;
323 cache_info_t LC1, LD1, L2, L3,
324 ITB, DTB, LITB, LDTB,
325 L2ITB, L2DTB, L2LITB, L2LDTB;
327 LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
328 LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
329 L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
330 L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
331 ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
332 DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
333 LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
334 LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
335 L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
336 L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
337 L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
338 L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
340 cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
342 if (cpuid_level > 1) {
344 cpuid(2, &eax, &ebx, &ecx, &edx);
345 numcalls = BITMASK(eax, 0, 0xff); //FIXME some systems may require repeated calls to read all entries
346 info[ 0] = BITMASK(eax, 8, 0xff);
347 info[ 1] = BITMASK(eax, 16, 0xff);
348 info[ 2] = BITMASK(eax, 24, 0xff);
350 info[ 3] = BITMASK(ebx, 0, 0xff);
351 info[ 4] = BITMASK(ebx, 8, 0xff);
352 info[ 5] = BITMASK(ebx, 16, 0xff);
353 info[ 6] = BITMASK(ebx, 24, 0xff);
355 info[ 7] = BITMASK(ecx, 0, 0xff);
356 info[ 8] = BITMASK(ecx, 8, 0xff);
357 info[ 9] = BITMASK(ecx, 16, 0xff);
358 info[10] = BITMASK(ecx, 24, 0xff);
360 info[11] = BITMASK(edx, 0, 0xff);
361 info[12] = BITMASK(edx, 8, 0xff);
362 info[13] = BITMASK(edx, 16, 0xff);
363 info[14] = BITMASK(edx, 24, 0xff);
365 for (i = 0; i < 15; i++){
368 /* This table is from http://www.sandpile.org/ia32/cpuid.htm */
377 LITB.associative = 0;
387 LDTB.associative = 4;
392 LDTB.associative = 4;
551 if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
596 LITB.associative = 0;
605 LITB.associative = 0;
614 LITB.associative = 0;
620 LITB.associative = 0;
626 LDTB.associative = 4;
631 LDTB.associative = 4;
639 LDTB.associative = 0;
648 LDTB.associative = 0;
657 LDTB.associative = 0;
825 L2DTB.associative = 0;
835 LITB.associative = 4;
922 if (get_vendor() == VENDOR_INTEL) {
923 if(LD1.size<=0 || LC1.size<=0){
924 //If we didn't detect L1 correctly before,
926 for (count=0;count <4;count++) {
927 cpuid_count(4, count, &eax, &ebx, &ecx, &edx);
934 switch ((eax >>5) &0x07)
938 // fprintf(stderr,"L1 data cache...\n");
940 int lines = (ebx & 0x0fff) +1;
942 int part = (ebx&0x03ff)+1;
944 int assoc = (ebx&0x03ff)+1;
945 LD1.size = (assoc*part*lines*sets)/1024;
946 LD1.associative = assoc;
957 switch ((eax >>5) &0x07)
961 // fprintf(stderr,"L1 instruction cache...\n");
963 int lines = (ebx & 0x0fff) +1;
965 int part = (ebx&0x03ff)+1;
967 int assoc = (ebx&0x03ff)+1;
968 LC1.size = (assoc*part*lines*sets)/1024;
969 LC1.associative = assoc;
984 cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
985 if (cpuid_level >= 0x80000006) {
987 //If we didn't detect L2 correctly before,
988 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
990 L2.size = BITMASK(ecx, 16, 0xffff);
991 L2.associative = BITMASK(ecx, 12, 0x0f);
993 switch (L2.associative){
1002 L2.linesize = BITMASK(ecx, 0, 0xff);
1007 if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
1008 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1011 LDTB.associative = BITMASK(eax, 24, 0xff);
1012 if (LDTB.associative == 0xff) LDTB.associative = 0;
1013 LDTB.linesize = BITMASK(eax, 16, 0xff);
1016 LITB.associative = BITMASK(eax, 8, 0xff);
1017 if (LITB.associative == 0xff) LITB.associative = 0;
1018 LITB.linesize = BITMASK(eax, 0, 0xff);
1021 DTB.associative = BITMASK(ebx, 24, 0xff);
1022 if (DTB.associative == 0xff) DTB.associative = 0;
1023 DTB.linesize = BITMASK(ebx, 16, 0xff);
1026 ITB.associative = BITMASK(ebx, 8, 0xff);
1027 if (ITB.associative == 0xff) ITB.associative = 0;
1028 ITB.linesize = BITMASK(ebx, 0, 0xff);
1030 LD1.size = BITMASK(ecx, 24, 0xff);
1031 LD1.associative = BITMASK(ecx, 16, 0xff);
1032 if (LD1.associative == 0xff) LD1.associative = 0;
1033 LD1.linesize = BITMASK(ecx, 0, 0xff);
1035 LC1.size = BITMASK(ecx, 24, 0xff);
1036 LC1.associative = BITMASK(ecx, 16, 0xff);
1037 if (LC1.associative == 0xff) LC1.associative = 0;
1038 LC1.linesize = BITMASK(ecx, 0, 0xff);
1040 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1043 L2LDTB.associative = BITMASK(eax, 24, 0xff);
1044 if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
1045 L2LDTB.linesize = BITMASK(eax, 16, 0xff);
1048 L2LITB.associative = BITMASK(eax, 8, 0xff);
1049 if (L2LITB.associative == 0xff) L2LITB.associative = 0;
1050 L2LITB.linesize = BITMASK(eax, 0, 0xff);
1053 L2DTB.associative = BITMASK(ebx, 24, 0xff);
1054 if (L2DTB.associative == 0xff) L2DTB.associative = 0;
1055 L2DTB.linesize = BITMASK(ebx, 16, 0xff);
1058 L2ITB.associative = BITMASK(ebx, 8, 0xff);
1059 if (L2ITB.associative == 0xff) L2ITB.associative = 0;
1060 L2ITB.linesize = BITMASK(ebx, 0, 0xff);
1063 //If we didn't detect L2 correctly before,
1064 L2.size = BITMASK(ecx, 16, 0xffff);
1065 L2.associative = BITMASK(ecx, 12, 0xf);
1066 switch (L2.associative){
1071 L2.associative = 16;
1075 if (L2.associative == 0xff) L2.associative = 0;
1076 L2.linesize = BITMASK(ecx, 0, 0xff);
1079 L3.size = BITMASK(edx, 18, 0x3fff) * 512;
1080 L3.associative = BITMASK(edx, 12, 0xf);
1081 if (L3.associative == 0xff) L2.associative = 0;
1082 L3.linesize = BITMASK(edx, 0, 0xff);
1088 case CACHE_INFO_L1_I :
1091 case CACHE_INFO_L1_D :
1094 case CACHE_INFO_L2 :
1097 case CACHE_INFO_L3 :
1100 case CACHE_INFO_L1_DTB :
1103 case CACHE_INFO_L1_ITB :
1106 case CACHE_INFO_L1_LDTB :
1109 case CACHE_INFO_L1_LITB :
1112 case CACHE_INFO_L2_DTB :
1115 case CACHE_INFO_L2_ITB :
1118 case CACHE_INFO_L2_LDTB :
1119 *cacheinfo = L2LDTB;
1121 case CACHE_INFO_L2_LITB :
1122 *cacheinfo = L2LITB;
1128 int get_cpuname(void){
1130 int family, exfamily, model, vendor, exmodel;
1132 if (!have_cpuid()) return CPUTYPE_80386;
1134 family = get_cputype(GET_FAMILY);
1135 exfamily = get_cputype(GET_EXFAMILY);
1136 model = get_cputype(GET_MODEL);
1137 exmodel = get_cputype(GET_EXMODEL);
1139 vendor = get_vendor();
1141 if (vendor == VENDOR_INTEL){
1144 return CPUTYPE_80486;
1146 return CPUTYPE_PENTIUM;
1155 return CPUTYPE_PENTIUM2;
1160 return CPUTYPE_PENTIUM3;
1164 return CPUTYPE_PENTIUMM;
1166 return CPUTYPE_CORE2;
1172 return CPUTYPE_CORE2;
1174 return CPUTYPE_PENRYN;
1179 return CPUTYPE_NEHALEM;
1181 return CPUTYPE_ATOM;
1183 return CPUTYPE_DUNNINGTON;
1189 //Intel Core (Clarkdale) / Core (Arrandale)
1190 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1191 // Xeon (Clarkdale), 32nm
1192 return CPUTYPE_NEHALEM;
1194 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1196 return CPUTYPE_SANDYBRIDGE;
1198 return CPUTYPE_NEHALEM; //OS doesn't support AVX
1200 //Xeon Processor 5600 (Westmere-EP)
1201 return CPUTYPE_NEHALEM;
1203 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1205 return CPUTYPE_SANDYBRIDGE;
1207 return CPUTYPE_NEHALEM;
1211 //Xeon Processor E7 (Westmere-EX)
1212 return CPUTYPE_NEHALEM;
1219 return CPUTYPE_ATOM;
1224 return CPUTYPE_SANDYBRIDGE;
1226 return CPUTYPE_NEHALEM;
1231 return CPUTYPE_HASWELL;
1233 return CPUTYPE_SANDYBRIDGE;
1236 return CPUTYPE_NEHALEM;
1241 return CPUTYPE_HASWELL;
1243 return CPUTYPE_SANDYBRIDGE;
1246 return CPUTYPE_NEHALEM;
1255 return CPUTYPE_HASWELL;
1257 return CPUTYPE_SANDYBRIDGE;
1260 return CPUTYPE_NEHALEM;
1266 return CPUTYPE_HASWELL;
1268 return CPUTYPE_SANDYBRIDGE;
1271 return CPUTYPE_NEHALEM;
1276 return CPUTYPE_HASWELL;
1278 return CPUTYPE_SANDYBRIDGE;
1281 return CPUTYPE_NEHALEM;
1286 return CPUTYPE_NEHALEM;
1295 return CPUTYPE_HASWELL;
1297 return CPUTYPE_SANDYBRIDGE;
1300 return CPUTYPE_NEHALEM;
1306 return CPUTYPE_HASWELL;
1308 return CPUTYPE_SANDYBRIDGE;
1311 return CPUTYPE_NEHALEM;
1313 // Xeon Phi Knights Landing
1316 return CPUTYPE_HASWELL;
1318 return CPUTYPE_SANDYBRIDGE;
1321 return CPUTYPE_NEHALEM;
1324 return CPUTYPE_NEHALEM;
1330 case 14: // Kaby Lake
1333 return CPUTYPE_HASWELL;
1335 return CPUTYPE_SANDYBRIDGE;
1338 return CPUTYPE_NEHALEM;
1344 return CPUTYPE_ITANIUM;
1348 return CPUTYPE_PENTIUM4;
1350 return CPUTYPE_ITANIUM;
1354 return CPUTYPE_INTEL_UNKNOWN;
1357 if (vendor == VENDOR_AMD){
1360 return CPUTYPE_AMD5X86;
1362 return CPUTYPE_AMDK6;
1364 return CPUTYPE_ATHLON;
1369 return CPUTYPE_OPTERON;
1374 return CPUTYPE_BARCELONA;
1376 return CPUTYPE_BOBCAT;
1380 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1382 return CPUTYPE_BULLDOZER;
1384 return CPUTYPE_BARCELONA; //OS don't support AVX.
1385 case 2: //AMD Piledriver
1386 case 3: //AMD Richland
1388 return CPUTYPE_PILEDRIVER;
1390 return CPUTYPE_BARCELONA; //OS don't support AVX.
1391 case 5: // New EXCAVATOR CPUS
1393 return CPUTYPE_EXCAVATOR;
1395 return CPUTYPE_BARCELONA; //OS don't support AVX.
1399 case 1: //AMD Trinity
1401 return CPUTYPE_PILEDRIVER;
1403 return CPUTYPE_BARCELONA; //OS don't support AVX.
1406 return CPUTYPE_STEAMROLLER;
1408 return CPUTYPE_BARCELONA; //OS don't support AVX.
1412 return CPUTYPE_EXCAVATOR;
1414 return CPUTYPE_BARCELONA; //OS don't support AVX.
1427 return CPUTYPE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1430 return CPUTYPE_BARCELONA;
1435 return CPUTYPE_AMD_UNKNOWN;
1438 if (vendor == VENDOR_CYRIX){
1441 return CPUTYPE_CYRIX5X86;
1443 return CPUTYPE_CYRIXM1;
1445 return CPUTYPE_CYRIXM2;
1447 return CPUTYPE_CYRIX_UNKNOWN;
1450 if (vendor == VENDOR_NEXGEN){
1453 return CPUTYPE_NEXGENNX586;
1455 return CPUTYPE_NEXGEN_UNKNOWN;
1458 if (vendor == VENDOR_CENTAUR){
1461 return CPUTYPE_CENTAURC6;
1464 return CPUTYPE_NANO;
1468 return CPUTYPE_VIAC3;
1471 if (vendor == VENDOR_RISE){
1474 return CPUTYPE_RISEMP6;
1476 return CPUTYPE_RISE_UNKNOWN;
1479 if (vendor == VENDOR_SIS){
1482 return CPUTYPE_SYS55X;
1484 return CPUTYPE_SIS_UNKNOWN;
1487 if (vendor == VENDOR_TRANSMETA){
1490 return CPUTYPE_CRUSOETM3X;
1492 return CPUTYPE_TRANSMETA_UNKNOWN;
1495 if (vendor == VENDOR_NSC){
1498 return CPUTYPE_NSGEODE;
1500 return CPUTYPE_NSC_UNKNOWN;
1503 return CPUTYPE_UNKNOWN;
1506 static char *cpuname[] = {
1516 "TRANSMETA_UNKNOWN",
1561 static char *lowercpuname[] = {
1571 "transmeta_unknown",
1615 static char *corename[] = {
1646 static char *corename_lower[] = {
1678 char *get_cpunamechar(void){
1679 return cpuname[get_cpuname()];
1682 char *get_lower_cpunamechar(void){
1683 return lowercpuname[get_cpuname()];
1687 int get_coretype(void){
1689 int family, exfamily, model, exmodel, vendor;
1691 if (!have_cpuid()) return CORE_80486;
1693 family = get_cputype(GET_FAMILY);
1694 exfamily = get_cputype(GET_EXFAMILY);
1695 model = get_cputype(GET_MODEL);
1696 exmodel = get_cputype(GET_EXMODEL);
1698 vendor = get_vendor();
1700 if (vendor == VENDOR_INTEL){
1723 return CORE_COPPERMINE;
1742 return CORE_NEHALEM;
1746 return CORE_DUNNINGTON;
1752 //Intel Core (Clarkdale) / Core (Arrandale)
1753 // Pentium (Clarkdale) / Pentium Mobile (Arrandale)
1754 // Xeon (Clarkdale), 32nm
1755 return CORE_NEHALEM;
1757 //Intel Core i5-2000 /i7-2000 (Sandy Bridge)
1759 return CORE_SANDYBRIDGE;
1761 return CORE_NEHALEM; //OS doesn't support AVX
1763 //Xeon Processor 5600 (Westmere-EP)
1764 return CORE_NEHALEM;
1766 //Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
1768 return CORE_SANDYBRIDGE;
1770 return CORE_NEHALEM; //OS doesn't support AVX
1774 //Xeon Processor E7 (Westmere-EX)
1775 return CORE_NEHALEM;
1783 return CORE_SANDYBRIDGE;
1785 return CORE_NEHALEM; //OS doesn't support AVX
1790 return CORE_HASWELL;
1792 return CORE_SANDYBRIDGE;
1795 return CORE_NEHALEM;
1800 return CORE_HASWELL;
1802 return CORE_SANDYBRIDGE;
1805 return CORE_NEHALEM;
1814 return CORE_HASWELL;
1816 return CORE_SANDYBRIDGE;
1819 return CORE_NEHALEM;
1825 return CORE_HASWELL;
1827 return CORE_SANDYBRIDGE;
1830 return CORE_NEHALEM;
1835 return CORE_HASWELL;
1837 return CORE_SANDYBRIDGE;
1840 return CORE_NEHALEM;
1845 return CORE_NEHALEM;
1854 return CORE_HASWELL;
1856 return CORE_SANDYBRIDGE;
1859 return CORE_NEHALEM;
1865 return CORE_HASWELL;
1867 return CORE_SANDYBRIDGE;
1870 return CORE_NEHALEM;
1872 // Phi Knights Landing
1875 return CORE_HASWELL;
1877 return CORE_SANDYBRIDGE;
1880 return CORE_NEHALEM;
1883 return CORE_NEHALEM;
1888 if (model == 14) { // Kaby Lake
1891 return CORE_HASWELL;
1893 return CORE_SANDYBRIDGE;
1896 return CORE_NEHALEM;
1902 if (model <= 0x2) return CORE_NORTHWOOD;
1903 else return CORE_PRESCOTT;
1907 if (vendor == VENDOR_AMD){
1908 if (family <= 0x5) return CORE_80486;
1909 if (family <= 0xe) return CORE_ATHLON;
1911 if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
1912 else if (exfamily == 5) return CORE_BOBCAT;
1913 else if (exfamily == 6) {
1916 //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
1918 return CORE_BULLDOZER;
1920 return CORE_BARCELONA; //OS don't support AVX.
1921 case 2: //AMD Piledriver
1922 case 3: //AMD Richland
1924 return CORE_PILEDRIVER;
1926 return CORE_BARCELONA; //OS don't support AVX.
1927 case 5: // New EXCAVATOR
1929 return CORE_EXCAVATOR;
1931 return CORE_BARCELONA; //OS don't support AVX.
1935 case 1: //AMD Trinity
1937 return CORE_PILEDRIVER;
1939 return CORE_BARCELONA; //OS don't support AVX.
1943 return CORE_STEAMROLLER;
1945 return CORE_BARCELONA; //OS don't support AVX.
1949 return CORE_EXCAVATOR;
1951 return CORE_BARCELONA; //OS don't support AVX.
1955 } else if (exfamily == 8) {
1963 return CORE_SANDYBRIDGE; // Zen is closer in architecture to Sandy Bridge than to Excavator
1966 return CORE_BARCELONA;
1969 return CORE_BARCELONA;
1974 if (vendor == VENDOR_CENTAUR) {
1983 return CORE_UNKNOWN;
1986 void get_cpuconfig(void){
1991 printf("#define %s\n", cpuname[get_cpuname()]);
1994 if (get_coretype() != CORE_P5) {
1996 get_cacheinfo(CACHE_INFO_L1_I, &info);
1997 if (info.size > 0) {
1998 printf("#define L1_CODE_SIZE %d\n", info.size * 1024);
1999 printf("#define L1_CODE_ASSOCIATIVE %d\n", info.associative);
2000 printf("#define L1_CODE_LINESIZE %d\n", info.linesize);
2003 get_cacheinfo(CACHE_INFO_L1_D, &info);
2004 if (info.size > 0) {
2005 printf("#define L1_DATA_SIZE %d\n", info.size * 1024);
2006 printf("#define L1_DATA_ASSOCIATIVE %d\n", info.associative);
2007 printf("#define L1_DATA_LINESIZE %d\n", info.linesize);
2010 get_cacheinfo(CACHE_INFO_L2, &info);
2011 if (info.size > 0) {
2012 printf("#define L2_SIZE %d\n", info.size * 1024);
2013 printf("#define L2_ASSOCIATIVE %d\n", info.associative);
2014 printf("#define L2_LINESIZE %d\n", info.linesize);
2016 //fall back for some virtual machines.
2017 printf("#define L2_SIZE 1048576\n");
2018 printf("#define L2_ASSOCIATIVE 6\n");
2019 printf("#define L2_LINESIZE 64\n");
2023 get_cacheinfo(CACHE_INFO_L3, &info);
2024 if (info.size > 0) {
2025 printf("#define L3_SIZE %d\n", info.size * 1024);
2026 printf("#define L3_ASSOCIATIVE %d\n", info.associative);
2027 printf("#define L3_LINESIZE %d\n", info.linesize);
2030 get_cacheinfo(CACHE_INFO_L1_ITB, &info);
2031 if (info.size > 0) {
2032 printf("#define ITB_SIZE %d\n", info.size * 1024);
2033 printf("#define ITB_ASSOCIATIVE %d\n", info.associative);
2034 printf("#define ITB_ENTRIES %d\n", info.linesize);
2037 get_cacheinfo(CACHE_INFO_L1_DTB, &info);
2038 if (info.size > 0) {
2039 printf("#define DTB_SIZE %d\n", info.size * 1024);
2040 printf("#define DTB_ASSOCIATIVE %d\n", info.associative);
2041 printf("#define DTB_DEFAULT_ENTRIES %d\n", info.linesize);
2043 //fall back for some virtual machines.
2044 printf("#define DTB_DEFAULT_ENTRIES 32\n");
2047 features = get_cputype(GET_FEATURE);
2049 if (features & HAVE_CMOV ) printf("#define HAVE_CMOV\n");
2050 if (features & HAVE_MMX ) printf("#define HAVE_MMX\n");
2051 if (features & HAVE_SSE ) printf("#define HAVE_SSE\n");
2052 if (features & HAVE_SSE2 ) printf("#define HAVE_SSE2\n");
2053 if (features & HAVE_SSE3 ) printf("#define HAVE_SSE3\n");
2054 if (features & HAVE_SSSE3) printf("#define HAVE_SSSE3\n");
2055 if (features & HAVE_SSE4_1) printf("#define HAVE_SSE4_1\n");
2056 if (features & HAVE_SSE4_2) printf("#define HAVE_SSE4_2\n");
2057 if (features & HAVE_SSE4A) printf("#define HAVE_SSE4A\n");
2058 if (features & HAVE_SSE5 ) printf("#define HAVE_SSSE5\n");
2059 if (features & HAVE_AVX ) printf("#define HAVE_AVX\n");
2060 if (features & HAVE_3DNOWEX) printf("#define HAVE_3DNOWEX\n");
2061 if (features & HAVE_3DNOW) printf("#define HAVE_3DNOW\n");
2062 if (features & HAVE_FMA4 ) printf("#define HAVE_FMA4\n");
2063 if (features & HAVE_FMA3 ) printf("#define HAVE_FMA3\n");
2064 if (features & HAVE_CFLUSH) printf("#define HAVE_CFLUSH\n");
2065 if (features & HAVE_HIT) printf("#define HAVE_HIT 1\n");
2066 if (features & HAVE_MISALIGNSSE) printf("#define HAVE_MISALIGNSSE\n");
2067 if (features & HAVE_128BITFPU) printf("#define HAVE_128BITFPU\n");
2068 if (features & HAVE_FASTMOVU) printf("#define HAVE_FASTMOVU\n");
2070 printf("#define NUM_SHAREDCACHE %d\n", get_cputype(GET_NUMSHARE) + 1);
2071 printf("#define NUM_CORES %d\n", get_cputype(GET_NUMCORES) + 1);
2073 features = get_coretype();
2074 if (features > 0) printf("#define CORE_%s\n", corename[features]);
2076 printf("#define DTB_DEFAULT_ENTRIES 16\n");
2077 printf("#define L1_CODE_SIZE 8192\n");
2078 printf("#define L1_DATA_SIZE 8192\n");
2079 printf("#define L2_SIZE 0\n");
2083 void get_architecture(void){
2091 void get_subarchitecture(void){
2092 printf("%s", get_cpunamechar());
2095 void get_subdirname(void){
2103 char *get_corename(void){
2104 return corename[get_coretype()];
2107 void get_libname(void){
2108 printf("%s", corename_lower[get_coretype()]);
2111 /* This if for Makefile */
2116 features = get_cputype(GET_FEATURE);
2118 if (features & HAVE_MMX ) printf("HAVE_MMX=1\n");
2119 if (features & HAVE_SSE ) printf("HAVE_SSE=1\n");
2120 if (features & HAVE_SSE2 ) printf("HAVE_SSE2=1\n");
2121 if (features & HAVE_SSE3 ) printf("HAVE_SSE3=1\n");
2122 if (features & HAVE_SSSE3) printf("HAVE_SSSE3=1\n");
2123 if (features & HAVE_SSE4_1) printf("HAVE_SSE4_1=1\n");
2124 if (features & HAVE_SSE4_2) printf("HAVE_SSE4_2=1\n");
2125 if (features & HAVE_SSE4A) printf("HAVE_SSE4A=1\n");
2126 if (features & HAVE_SSE5 ) printf("HAVE_SSSE5=1\n");
2127 if (features & HAVE_AVX ) printf("HAVE_AVX=1\n");
2128 if (features & HAVE_3DNOWEX) printf("HAVE_3DNOWEX=1\n");
2129 if (features & HAVE_3DNOW) printf("HAVE_3DNOW=1\n");
2130 if (features & HAVE_FMA4 ) printf("HAVE_FMA4=1\n");
2131 if (features & HAVE_FMA3 ) printf("HAVE_FMA3=1\n");