2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
153 static inline TranslationBlock *tb_find_fast(void)
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
197 #elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
201 #elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
206 #error unsupported CPU
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
225 /* main execution loop */
227 int cpu_exec(CPUState *env1)
229 #define DECLARE_HOST_REGS 1
230 #include "hostregs_helper.h"
231 #if defined(TARGET_SPARC)
232 #if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
236 #if defined(__sparc__) && !defined(HOST_SOLARIS)
240 int ret, interrupt_request;
241 void (*gen_func)(void);
242 TranslationBlock *tb;
245 #if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
256 #elif defined(TARGET_PPC)
258 if (env1->msr[MSR_EE] &&
259 (env1->interrupt_request &
260 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
266 #elif defined(TARGET_SPARC)
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->psret != 0)) {
275 #elif defined(TARGET_ARM)
277 /* An interrupt wakes the CPU even if the I and F CPSR bits are
279 if (env1->interrupt_request
280 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
286 #elif defined(TARGET_MIPS)
288 if (env1->interrupt_request &
289 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
297 cpu_single_env = env1;
299 /* first we save global registers */
300 #define SAVE_HOST_REGS 1
301 #include "hostregs_helper.h"
303 #if defined(__sparc__) && !defined(HOST_SOLARIS)
304 /* we also save i7 because longjmp may not restore it */
305 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
308 #if defined(TARGET_I386)
310 /* put eflags in CPU temporary format */
311 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
312 DF = 1 - (2 * ((env->eflags >> 10) & 1));
313 CC_OP = CC_OP_EFLAGS;
314 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
315 #elif defined(TARGET_ARM)
316 #elif defined(TARGET_SPARC)
317 #if defined(reg_REGWPTR)
318 saved_regwptr = REGWPTR;
320 #elif defined(TARGET_PPC)
321 #elif defined(TARGET_M68K)
322 env->cc_op = CC_OP_FLAGS;
323 env->cc_dest = env->sr & 0xf;
324 env->cc_x = (env->sr >> 4) & 1;
325 #elif defined(TARGET_MIPS)
326 #elif defined(TARGET_SH4)
329 #error unsupported target CPU
331 env->exception_index = -1;
333 /* prepare setjmp context for exception handling */
335 if (setjmp(env->jmp_env) == 0) {
336 env->current_tb = NULL;
337 /* if an exception is pending, we execute it here */
338 if (env->exception_index >= 0) {
339 if (env->exception_index >= EXCP_INTERRUPT) {
340 /* exit request from the cpu execution loop */
341 ret = env->exception_index;
343 } else if (env->user_mode_only) {
344 /* if user mode only, we simulate a fake exception
345 which will be handled outside the cpu execution
347 #if defined(TARGET_I386)
348 do_interrupt_user(env->exception_index,
349 env->exception_is_int,
351 env->exception_next_eip);
353 ret = env->exception_index;
356 #if defined(TARGET_I386)
357 /* simulate a real cpu exception. On i386, it can
358 trigger new exceptions, but we do not handle
359 double or triple faults yet. */
360 do_interrupt(env->exception_index,
361 env->exception_is_int,
363 env->exception_next_eip, 0);
364 #elif defined(TARGET_PPC)
366 #elif defined(TARGET_MIPS)
368 #elif defined(TARGET_SPARC)
369 do_interrupt(env->exception_index);
370 #elif defined(TARGET_ARM)
372 #elif defined(TARGET_SH4)
376 env->exception_index = -1;
379 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
381 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
382 ret = kqemu_cpu_exec(env);
383 /* put eflags in CPU temporary format */
384 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
385 DF = 1 - (2 * ((env->eflags >> 10) & 1));
386 CC_OP = CC_OP_EFLAGS;
387 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
390 longjmp(env->jmp_env, 1);
391 } else if (ret == 2) {
392 /* softmmu execution needed */
394 if (env->interrupt_request != 0) {
395 /* hardware interrupt will be executed just after */
397 /* otherwise, we restart */
398 longjmp(env->jmp_env, 1);
404 T0 = 0; /* force lookup of first TB */
406 #if defined(__sparc__) && !defined(HOST_SOLARIS)
407 /* g1 can be modified by some libc? functions */
410 interrupt_request = env->interrupt_request;
411 if (__builtin_expect(interrupt_request, 0)) {
412 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
413 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
414 env->exception_index = EXCP_DEBUG;
417 #if defined(TARGET_I386)
418 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
419 !(env->hflags & HF_SMM_MASK)) {
420 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
422 #if defined(__sparc__) && !defined(HOST_SOLARIS)
427 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
428 (env->eflags & IF_MASK) &&
429 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
431 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
432 intno = cpu_get_pic_interrupt(env);
433 if (loglevel & CPU_LOG_TB_IN_ASM) {
434 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
436 do_interrupt(intno, 0, 0, 0, 1);
437 /* ensure that no TB jump will be modified as
438 the program flow was changed */
439 #if defined(__sparc__) && !defined(HOST_SOLARIS)
445 #elif defined(TARGET_PPC)
447 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
452 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
454 env->exception_index = EXCP_EXTERNAL;
457 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
458 #if defined(__sparc__) && !defined(HOST_SOLARIS)
463 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
465 env->exception_index = EXCP_DECR;
468 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
469 #if defined(__sparc__) && !defined(HOST_SOLARIS)
476 #elif defined(TARGET_MIPS)
477 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
478 (env->CP0_Status & (1 << CP0St_IE)) &&
479 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
480 !(env->hflags & MIPS_HFLAG_EXL) &&
481 !(env->hflags & MIPS_HFLAG_ERL) &&
482 !(env->hflags & MIPS_HFLAG_DM)) {
484 env->exception_index = EXCP_EXT_INTERRUPT;
487 #if defined(__sparc__) && !defined(HOST_SOLARIS)
493 #elif defined(TARGET_SPARC)
494 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
496 int pil = env->interrupt_index & 15;
497 int type = env->interrupt_index & 0xf0;
499 if (((type == TT_EXTINT) &&
500 (pil == 15 || pil > env->psrpil)) ||
502 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
503 do_interrupt(env->interrupt_index);
504 env->interrupt_index = 0;
505 #if defined(__sparc__) && !defined(HOST_SOLARIS)
511 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
512 //do_interrupt(0, 0, 0, 0, 0);
513 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
514 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
515 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
517 env->exception_index = EXCP_HLT;
520 #elif defined(TARGET_ARM)
521 if (interrupt_request & CPU_INTERRUPT_FIQ
522 && !(env->uncached_cpsr & CPSR_F)) {
523 env->exception_index = EXCP_FIQ;
526 if (interrupt_request & CPU_INTERRUPT_HARD
527 && !(env->uncached_cpsr & CPSR_I)) {
528 env->exception_index = EXCP_IRQ;
531 #elif defined(TARGET_SH4)
534 /* Don't use the cached interupt_request value,
535 do_interrupt may have updated the EXITTB flag. */
536 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
537 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
538 /* ensure that no TB jump will be modified as
539 the program flow was changed */
540 #if defined(__sparc__) && !defined(HOST_SOLARIS)
546 if (interrupt_request & CPU_INTERRUPT_EXIT) {
547 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
548 env->exception_index = EXCP_INTERRUPT;
553 if ((loglevel & CPU_LOG_TB_CPU)) {
554 #if defined(TARGET_I386)
555 /* restore flags in standard format */
557 env->regs[R_EAX] = EAX;
560 env->regs[R_EBX] = EBX;
563 env->regs[R_ECX] = ECX;
566 env->regs[R_EDX] = EDX;
569 env->regs[R_ESI] = ESI;
572 env->regs[R_EDI] = EDI;
575 env->regs[R_EBP] = EBP;
578 env->regs[R_ESP] = ESP;
580 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
581 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
582 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
583 #elif defined(TARGET_ARM)
584 cpu_dump_state(env, logfile, fprintf, 0);
585 #elif defined(TARGET_SPARC)
586 REGWPTR = env->regbase + (env->cwp * 16);
587 env->regwptr = REGWPTR;
588 cpu_dump_state(env, logfile, fprintf, 0);
589 #elif defined(TARGET_PPC)
590 cpu_dump_state(env, logfile, fprintf, 0);
591 #elif defined(TARGET_M68K)
592 cpu_m68k_flush_flags(env, env->cc_op);
593 env->cc_op = CC_OP_FLAGS;
594 env->sr = (env->sr & 0xffe0)
595 | env->cc_dest | (env->cc_x << 4);
596 cpu_dump_state(env, logfile, fprintf, 0);
597 #elif defined(TARGET_MIPS)
598 cpu_dump_state(env, logfile, fprintf, 0);
599 #elif defined(TARGET_SH4)
600 cpu_dump_state(env, logfile, fprintf, 0);
602 #error unsupported target CPU
608 if ((loglevel & CPU_LOG_EXEC)) {
609 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
610 (long)tb->tc_ptr, tb->pc,
611 lookup_symbol(tb->pc));
614 #if defined(__sparc__) && !defined(HOST_SOLARIS)
617 /* see if we can patch the calling TB. When the TB
618 spans two pages, we cannot safely do a direct
623 (env->kqemu_enabled != 2) &&
625 tb->page_addr[1] == -1
626 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
627 && (tb->cflags & CF_CODE_COPY) ==
628 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
632 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
633 #if defined(USE_CODE_COPY)
634 /* propagates the FP use info */
635 ((TranslationBlock *)(T0 & ~3))->cflags |=
636 (tb->cflags & CF_FP_USED);
638 spin_unlock(&tb_lock);
642 env->current_tb = tb;
643 /* execute the generated code */
644 gen_func = (void *)tc_ptr;
645 #if defined(__sparc__)
646 __asm__ __volatile__("call %0\n\t"
650 : "i0", "i1", "i2", "i3", "i4", "i5",
651 "o0", "o1", "o2", "o3", "o4", "o5",
652 "l0", "l1", "l2", "l3", "l4", "l5",
654 #elif defined(__arm__)
655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
661 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
663 if (!(tb->cflags & CF_CODE_COPY)) {
664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
735 #elif defined(__ia64)
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
747 env->current_tb = NULL;
748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
753 /* do not allow linking to another block */
757 #if defined(USE_KQEMU)
758 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
759 if (kqemu_is_ok(env) &&
760 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
771 #if defined(TARGET_I386)
772 #if defined(USE_CODE_COPY)
773 if (env->native_fp_regs) {
774 save_native_fp_state(env);
777 /* restore flags in standard format */
778 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
779 #elif defined(TARGET_ARM)
780 /* XXX: Save/restore host fpu exception state?. */
781 #elif defined(TARGET_SPARC)
782 #if defined(reg_REGWPTR)
783 REGWPTR = saved_regwptr;
785 #elif defined(TARGET_PPC)
786 #elif defined(TARGET_M68K)
787 cpu_m68k_flush_flags(env, env->cc_op);
788 env->cc_op = CC_OP_FLAGS;
789 env->sr = (env->sr & 0xffe0)
790 | env->cc_dest | (env->cc_x << 4);
791 #elif defined(TARGET_MIPS)
792 #elif defined(TARGET_SH4)
795 #error unsupported target CPU
798 /* restore global registers */
799 #if defined(__sparc__) && !defined(HOST_SOLARIS)
800 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
802 #include "hostregs_helper.h"
804 /* fail safe : never use cpu_single_env outside cpu_exec() */
805 cpu_single_env = NULL;
809 /* must only be called from the generated code as an exception can be
811 void tb_invalidate_page_range(target_ulong start, target_ulong end)
813 /* XXX: cannot enable it yet because it yields to MMU exception
814 where NIP != read address on PowerPC */
816 target_ulong phys_addr;
817 phys_addr = get_phys_addr_code(env, start);
818 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
822 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
824 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
826 CPUX86State *saved_env;
830 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
832 cpu_x86_load_seg_cache(env, seg_reg, selector,
833 (selector << 4), 0xffff, 0);
835 load_seg(seg_reg, selector);
840 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
842 CPUX86State *saved_env;
847 helper_fsave((target_ulong)ptr, data32);
852 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
854 CPUX86State *saved_env;
859 helper_frstor((target_ulong)ptr, data32);
864 #endif /* TARGET_I386 */
866 #if !defined(CONFIG_SOFTMMU)
868 #if defined(TARGET_I386)
870 /* 'pc' is the host PC at which the exception was raised. 'address' is
871 the effective address of the memory exception. 'is_write' is 1 if a
872 write caused the exception and otherwise 0'. 'old_set' is the
873 signal set which should be restored */
874 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
875 int is_write, sigset_t *old_set,
878 TranslationBlock *tb;
882 env = cpu_single_env; /* XXX: find a correct solution for multithread */
883 #if defined(DEBUG_SIGNAL)
884 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
885 pc, address, is_write, *(unsigned long *)old_set);
887 /* XXX: locking issue */
888 if (is_write && page_unprotect(h2g(address), pc, puc)) {
892 /* see if it is an MMU fault */
893 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
894 ((env->hflags & HF_CPL_MASK) == 3), 0);
896 return 0; /* not an MMU fault */
898 return 1; /* the MMU fault was handled without causing real CPU fault */
899 /* now we have a real cpu fault */
902 /* the PC is inside the translated code. It means that we have
903 a virtual CPU fault */
904 cpu_restore_state(tb, env, pc, puc);
908 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
909 env->eip, env->cr[2], env->error_code);
911 /* we restore the process signal mask as the sigreturn should
912 do it (XXX: use sigsetjmp) */
913 sigprocmask(SIG_SETMASK, old_set, NULL);
914 raise_exception_err(env->exception_index, env->error_code);
916 /* activate soft MMU for this block */
917 env->hflags |= HF_SOFTMMU_MASK;
918 cpu_resume_from_signal(env, puc);
920 /* never comes here */
924 #elif defined(TARGET_ARM)
925 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
926 int is_write, sigset_t *old_set,
929 TranslationBlock *tb;
933 env = cpu_single_env; /* XXX: find a correct solution for multithread */
934 #if defined(DEBUG_SIGNAL)
935 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
936 pc, address, is_write, *(unsigned long *)old_set);
938 /* XXX: locking issue */
939 if (is_write && page_unprotect(h2g(address), pc, puc)) {
942 /* see if it is an MMU fault */
943 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
945 return 0; /* not an MMU fault */
947 return 1; /* the MMU fault was handled without causing real CPU fault */
948 /* now we have a real cpu fault */
951 /* the PC is inside the translated code. It means that we have
952 a virtual CPU fault */
953 cpu_restore_state(tb, env, pc, puc);
955 /* we restore the process signal mask as the sigreturn should
956 do it (XXX: use sigsetjmp) */
957 sigprocmask(SIG_SETMASK, old_set, NULL);
960 #elif defined(TARGET_SPARC)
961 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
962 int is_write, sigset_t *old_set,
965 TranslationBlock *tb;
969 env = cpu_single_env; /* XXX: find a correct solution for multithread */
970 #if defined(DEBUG_SIGNAL)
971 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
972 pc, address, is_write, *(unsigned long *)old_set);
974 /* XXX: locking issue */
975 if (is_write && page_unprotect(h2g(address), pc, puc)) {
978 /* see if it is an MMU fault */
979 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
981 return 0; /* not an MMU fault */
983 return 1; /* the MMU fault was handled without causing real CPU fault */
984 /* now we have a real cpu fault */
987 /* the PC is inside the translated code. It means that we have
988 a virtual CPU fault */
989 cpu_restore_state(tb, env, pc, puc);
991 /* we restore the process signal mask as the sigreturn should
992 do it (XXX: use sigsetjmp) */
993 sigprocmask(SIG_SETMASK, old_set, NULL);
996 #elif defined (TARGET_PPC)
997 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
998 int is_write, sigset_t *old_set,
1001 TranslationBlock *tb;
1005 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1006 #if defined(DEBUG_SIGNAL)
1007 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1008 pc, address, is_write, *(unsigned long *)old_set);
1010 /* XXX: locking issue */
1011 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1015 /* see if it is an MMU fault */
1016 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1018 return 0; /* not an MMU fault */
1020 return 1; /* the MMU fault was handled without causing real CPU fault */
1022 /* now we have a real cpu fault */
1023 tb = tb_find_pc(pc);
1025 /* the PC is inside the translated code. It means that we have
1026 a virtual CPU fault */
1027 cpu_restore_state(tb, env, pc, puc);
1031 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1032 env->nip, env->error_code, tb);
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
1036 sigprocmask(SIG_SETMASK, old_set, NULL);
1037 do_raise_exception_err(env->exception_index, env->error_code);
1039 /* activate soft MMU for this block */
1040 cpu_resume_from_signal(env, puc);
1042 /* never comes here */
1046 #elif defined(TARGET_M68K)
1047 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1048 int is_write, sigset_t *old_set,
1051 TranslationBlock *tb;
1055 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1056 #if defined(DEBUG_SIGNAL)
1057 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1058 pc, address, is_write, *(unsigned long *)old_set);
1060 /* XXX: locking issue */
1061 if (is_write && page_unprotect(address, pc, puc)) {
1064 /* see if it is an MMU fault */
1065 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1067 return 0; /* not an MMU fault */
1069 return 1; /* the MMU fault was handled without causing real CPU fault */
1070 /* now we have a real cpu fault */
1071 tb = tb_find_pc(pc);
1073 /* the PC is inside the translated code. It means that we have
1074 a virtual CPU fault */
1075 cpu_restore_state(tb, env, pc, puc);
1077 /* we restore the process signal mask as the sigreturn should
1078 do it (XXX: use sigsetjmp) */
1079 sigprocmask(SIG_SETMASK, old_set, NULL);
1081 /* never comes here */
1085 #elif defined (TARGET_MIPS)
1086 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1087 int is_write, sigset_t *old_set,
1090 TranslationBlock *tb;
1094 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1095 #if defined(DEBUG_SIGNAL)
1096 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1097 pc, address, is_write, *(unsigned long *)old_set);
1099 /* XXX: locking issue */
1100 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1104 /* see if it is an MMU fault */
1105 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1107 return 0; /* not an MMU fault */
1109 return 1; /* the MMU fault was handled without causing real CPU fault */
1111 /* now we have a real cpu fault */
1112 tb = tb_find_pc(pc);
1114 /* the PC is inside the translated code. It means that we have
1115 a virtual CPU fault */
1116 cpu_restore_state(tb, env, pc, puc);
1120 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1121 env->nip, env->error_code, tb);
1123 /* we restore the process signal mask as the sigreturn should
1124 do it (XXX: use sigsetjmp) */
1125 sigprocmask(SIG_SETMASK, old_set, NULL);
1126 do_raise_exception_err(env->exception_index, env->error_code);
1128 /* activate soft MMU for this block */
1129 cpu_resume_from_signal(env, puc);
1131 /* never comes here */
1135 #elif defined (TARGET_SH4)
1136 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1137 int is_write, sigset_t *old_set,
1140 TranslationBlock *tb;
1144 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1145 #if defined(DEBUG_SIGNAL)
1146 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1147 pc, address, is_write, *(unsigned long *)old_set);
1149 /* XXX: locking issue */
1150 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1154 /* see if it is an MMU fault */
1155 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1157 return 0; /* not an MMU fault */
1159 return 1; /* the MMU fault was handled without causing real CPU fault */
1161 /* now we have a real cpu fault */
1162 tb = tb_find_pc(pc);
1164 /* the PC is inside the translated code. It means that we have
1165 a virtual CPU fault */
1166 cpu_restore_state(tb, env, pc, puc);
1169 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1170 env->nip, env->error_code, tb);
1172 /* we restore the process signal mask as the sigreturn should
1173 do it (XXX: use sigsetjmp) */
1174 sigprocmask(SIG_SETMASK, old_set, NULL);
1176 /* never comes here */
1180 #error unsupported target CPU
1183 #if defined(__i386__)
1185 #if defined(__APPLE__)
1186 # include <sys/ucontext.h>
1188 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1189 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1190 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1192 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1193 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1194 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1197 #if defined(USE_CODE_COPY)
1198 static void cpu_send_trap(unsigned long pc, int trap,
1199 struct ucontext *uc)
1201 TranslationBlock *tb;
1204 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1205 /* now we have a real cpu fault */
1206 tb = tb_find_pc(pc);
1208 /* the PC is inside the translated code. It means that we have
1209 a virtual CPU fault */
1210 cpu_restore_state(tb, env, pc, uc);
1212 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1213 raise_exception_err(trap, env->error_code);
1217 int cpu_signal_handler(int host_signum, void *pinfo,
1220 siginfo_t *info = pinfo;
1221 struct ucontext *uc = puc;
1229 #define REG_TRAPNO TRAPNO
1232 trapno = TRAP_sig(uc);
1233 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1234 if (trapno == 0x00 || trapno == 0x05) {
1235 /* send division by zero or bound exception */
1236 cpu_send_trap(pc, trapno, uc);
1240 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1242 (ERROR_sig(uc) >> 1) & 1 : 0,
1243 &uc->uc_sigmask, puc);
1246 #elif defined(__x86_64__)
1248 int cpu_signal_handler(int host_signum, void *pinfo,
1251 siginfo_t *info = pinfo;
1252 struct ucontext *uc = puc;
1255 pc = uc->uc_mcontext.gregs[REG_RIP];
1256 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1257 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1258 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1259 &uc->uc_sigmask, puc);
1262 #elif defined(__powerpc__)
1264 /***********************************************************************
1265 * signal context platform-specific definitions
1269 /* All Registers access - only for local access */
1270 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1271 /* Gpr Registers access */
1272 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1273 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1274 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1275 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1276 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1277 # define LR_sig(context) REG_sig(link, context) /* Link register */
1278 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1279 /* Float Registers access */
1280 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1281 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1282 /* Exception Registers access */
1283 # define DAR_sig(context) REG_sig(dar, context)
1284 # define DSISR_sig(context) REG_sig(dsisr, context)
1285 # define TRAP_sig(context) REG_sig(trap, context)
1289 # include <sys/ucontext.h>
1290 typedef struct ucontext SIGCONTEXT;
1291 /* All Registers access - only for local access */
1292 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1293 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1294 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1295 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1296 /* Gpr Registers access */
1297 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1298 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1299 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1300 # define CTR_sig(context) REG_sig(ctr, context)
1301 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1302 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1303 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1304 /* Float Registers access */
1305 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1306 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1307 /* Exception Registers access */
1308 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1309 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1310 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1311 #endif /* __APPLE__ */
1313 int cpu_signal_handler(int host_signum, void *pinfo,
1316 siginfo_t *info = pinfo;
1317 struct ucontext *uc = puc;
1325 if (DSISR_sig(uc) & 0x00800000)
1328 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1331 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1332 is_write, &uc->uc_sigmask, puc);
1335 #elif defined(__alpha__)
1337 int cpu_signal_handler(int host_signum, void *pinfo,
1340 siginfo_t *info = pinfo;
1341 struct ucontext *uc = puc;
1342 uint32_t *pc = uc->uc_mcontext.sc_pc;
1343 uint32_t insn = *pc;
1346 /* XXX: need kernel patch to get write flag faster */
1347 switch (insn >> 26) {
1362 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1363 is_write, &uc->uc_sigmask, puc);
1365 #elif defined(__sparc__)
1367 int cpu_signal_handler(int host_signum, void *pinfo,
1370 siginfo_t *info = pinfo;
1371 uint32_t *regs = (uint32_t *)(info + 1);
1372 void *sigmask = (regs + 20);
1377 /* XXX: is there a standard glibc define ? */
1379 /* XXX: need kernel patch to get write flag faster */
1381 insn = *(uint32_t *)pc;
1382 if ((insn >> 30) == 3) {
1383 switch((insn >> 19) & 0x3f) {
1395 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1396 is_write, sigmask, NULL);
1399 #elif defined(__arm__)
1401 int cpu_signal_handler(int host_signum, void *pinfo,
1404 siginfo_t *info = pinfo;
1405 struct ucontext *uc = puc;
1409 pc = uc->uc_mcontext.gregs[R15];
1410 /* XXX: compute is_write */
1412 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1414 &uc->uc_sigmask, puc);
1417 #elif defined(__mc68000)
1419 int cpu_signal_handler(int host_signum, void *pinfo,
1422 siginfo_t *info = pinfo;
1423 struct ucontext *uc = puc;
1427 pc = uc->uc_mcontext.gregs[16];
1428 /* XXX: compute is_write */
1430 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1432 &uc->uc_sigmask, puc);
1435 #elif defined(__ia64)
1438 /* This ought to be in <bits/siginfo.h>... */
1439 # define __ISR_VALID 1
1442 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1444 siginfo_t *info = pinfo;
1445 struct ucontext *uc = puc;
1449 ip = uc->uc_mcontext.sc_ip;
1450 switch (host_signum) {
1456 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1457 /* ISR.W (write-access) is bit 33: */
1458 is_write = (info->si_isr >> 33) & 1;
1464 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1466 &uc->uc_sigmask, puc);
1469 #elif defined(__s390__)
1471 int cpu_signal_handler(int host_signum, void *pinfo,
1474 siginfo_t *info = pinfo;
1475 struct ucontext *uc = puc;
1479 pc = uc->uc_mcontext.psw.addr;
1480 /* XXX: compute is_write */
1482 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1484 &uc->uc_sigmask, puc);
1489 #error host CPU specific signal handler needed
1493 #endif /* !defined(CONFIG_SOFTMMU) */