2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #define CPU_NO_GLOBAL_REGS
26 #if !defined(CONFIG_SOFTMMU)
37 #include <sys/ucontext.h>
40 int tb_invalidated_flag;
41 static unsigned long next_tb;
44 //#define DEBUG_SIGNAL
46 #define SAVE_GLOBALS()
47 #define RESTORE_GLOBALS()
49 #if defined(__sparc__) && !defined(HOST_SOLARIS)
51 #if defined(__GLIBC__) && ((__GLIBC__ < 2) || \
52 ((__GLIBC__ == 2) && (__GLIBC_MINOR__ <= 90)))
53 // Work around ugly bugs in glibc that mangle global register contents
55 static volatile void *saved_env;
56 static volatile unsigned long saved_t0, saved_i7;
58 #define SAVE_GLOBALS() do { \
61 asm volatile ("st %%i7, [%0]" : : "r" (&saved_i7)); \
64 #undef RESTORE_GLOBALS
65 #define RESTORE_GLOBALS() do { \
66 env = (void *)saved_env; \
68 asm volatile ("ld [%0], %%i7" : : "r" (&saved_i7)); \
71 static int sparc_setjmp(jmp_buf buf)
81 #define setjmp(jmp_buf) sparc_setjmp(jmp_buf)
83 static void sparc_longjmp(jmp_buf buf, int val)
88 #define longjmp(jmp_buf, val) sparc_longjmp(jmp_buf, val)
92 void cpu_loop_exit(void)
94 /* NOTE: the register at this point must be saved by hand because
95 longjmp restore them */
97 longjmp(env->jmp_env, 1);
100 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
104 /* exit the current TB from a signal handler. The host registers are
105 restored in a state compatible with the CPU emulator
107 void cpu_resume_from_signal(CPUState *env1, void *puc)
109 #if !defined(CONFIG_SOFTMMU)
110 struct ucontext *uc = puc;
115 /* XXX: restore cpu registers saved in host registers */
117 #if !defined(CONFIG_SOFTMMU)
119 /* XXX: use siglongjmp ? */
120 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
123 longjmp(env->jmp_env, 1);
126 static TranslationBlock *tb_find_slow(target_ulong pc,
127 target_ulong cs_base,
130 TranslationBlock *tb, **ptb1;
133 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
138 tb_invalidated_flag = 0;
140 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
142 /* find translated block using physical mappings */
143 phys_pc = get_phys_addr_code(env, pc);
144 phys_page1 = phys_pc & TARGET_PAGE_MASK;
146 h = tb_phys_hash_func(phys_pc);
147 ptb1 = &tb_phys_hash[h];
153 tb->page_addr[0] == phys_page1 &&
154 tb->cs_base == cs_base &&
155 tb->flags == flags) {
156 /* check next page if needed */
157 if (tb->page_addr[1] != -1) {
158 virt_page2 = (pc & TARGET_PAGE_MASK) +
160 phys_page2 = get_phys_addr_code(env, virt_page2);
161 if (tb->page_addr[1] == phys_page2)
167 ptb1 = &tb->phys_hash_next;
170 /* if no translated code available, then translate it now */
173 /* flush must be done */
175 /* cannot fail at this point */
177 /* don't forget to invalidate previous TB info */
178 tb_invalidated_flag = 1;
180 tc_ptr = code_gen_ptr;
182 tb->cs_base = cs_base;
185 cpu_gen_code(env, tb, &code_gen_size);
187 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
189 /* check next page if needed */
190 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
192 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
193 phys_page2 = get_phys_addr_code(env, virt_page2);
195 tb_link_phys(tb, phys_pc, phys_page2);
198 /* we add the TB in the virtual pc hash table */
199 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
200 spin_unlock(&tb_lock);
204 static inline TranslationBlock *tb_find_fast(void)
206 TranslationBlock *tb;
207 target_ulong cs_base, pc;
210 /* we record a subset of the CPU state. It will
211 always be the same before a given translated block
213 #if defined(TARGET_I386)
215 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
216 flags |= env->intercept;
217 cs_base = env->segs[R_CS].base;
218 pc = cs_base + env->eip;
219 #elif defined(TARGET_ARM)
220 flags = env->thumb | (env->vfp.vec_len << 1)
221 | (env->vfp.vec_stride << 4);
222 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
224 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
226 flags |= (env->condexec_bits << 8);
229 #elif defined(TARGET_SPARC)
230 #ifdef TARGET_SPARC64
231 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
232 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
233 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
235 // FPU enable . Supervisor
236 flags = (env->psref << 4) | env->psrs;
240 #elif defined(TARGET_PPC)
244 #elif defined(TARGET_MIPS)
245 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
247 pc = env->PC[env->current_tc];
248 #elif defined(TARGET_M68K)
249 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
250 | (env->sr & SR_S) /* Bit 13 */
251 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
254 #elif defined(TARGET_SH4)
258 #elif defined(TARGET_ALPHA)
262 #elif defined(TARGET_CRIS)
263 flags = env->pregs[PR_CCS] & U_FLAG;
268 #error unsupported CPU
270 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
271 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
272 tb->flags != flags, 0)) {
273 tb = tb_find_slow(pc, cs_base, flags);
274 /* Note: we do it here to avoid a gcc bug on Mac OS X when
275 doing it in tb_find_slow */
276 if (tb_invalidated_flag) {
277 /* as some TB could have been invalidated because
278 of memory exceptions while generating the code, we
279 must recompute the hash index here */
286 /* main execution loop */
288 int cpu_exec(CPUState *env1)
290 #define DECLARE_HOST_REGS 1
291 #include "hostregs_helper.h"
292 #if defined(TARGET_SPARC)
293 #if defined(reg_REGWPTR)
294 uint32_t *saved_regwptr;
297 int ret, interrupt_request;
298 TranslationBlock *tb;
301 if (cpu_halted(env1) == EXCP_HALTED)
304 cpu_single_env = env1;
306 /* first we save global registers */
307 #define SAVE_HOST_REGS 1
308 #include "hostregs_helper.h"
313 #if defined(TARGET_I386)
314 /* put eflags in CPU temporary format */
315 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
316 DF = 1 - (2 * ((env->eflags >> 10) & 1));
317 CC_OP = CC_OP_EFLAGS;
318 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
319 #elif defined(TARGET_SPARC)
320 #if defined(reg_REGWPTR)
321 saved_regwptr = REGWPTR;
323 #elif defined(TARGET_M68K)
324 env->cc_op = CC_OP_FLAGS;
325 env->cc_dest = env->sr & 0xf;
326 env->cc_x = (env->sr >> 4) & 1;
327 #elif defined(TARGET_ALPHA)
328 #elif defined(TARGET_ARM)
329 #elif defined(TARGET_PPC)
330 #elif defined(TARGET_MIPS)
331 #elif defined(TARGET_SH4)
332 #elif defined(TARGET_CRIS)
335 #error unsupported target CPU
337 env->exception_index = -1;
339 /* prepare setjmp context for exception handling */
341 if (setjmp(env->jmp_env) == 0) {
342 env->current_tb = NULL;
343 /* if an exception is pending, we execute it here */
344 if (env->exception_index >= 0) {
345 if (env->exception_index >= EXCP_INTERRUPT) {
346 /* exit request from the cpu execution loop */
347 ret = env->exception_index;
349 } else if (env->user_mode_only) {
350 /* if user mode only, we simulate a fake exception
351 which will be handled outside the cpu execution
353 #if defined(TARGET_I386)
354 do_interrupt_user(env->exception_index,
355 env->exception_is_int,
357 env->exception_next_eip);
358 /* successfully delivered */
359 env->old_exception = -1;
361 ret = env->exception_index;
364 #if defined(TARGET_I386)
365 /* simulate a real cpu exception. On i386, it can
366 trigger new exceptions, but we do not handle
367 double or triple faults yet. */
368 do_interrupt(env->exception_index,
369 env->exception_is_int,
371 env->exception_next_eip, 0);
372 /* successfully delivered */
373 env->old_exception = -1;
374 #elif defined(TARGET_PPC)
376 #elif defined(TARGET_MIPS)
378 #elif defined(TARGET_SPARC)
379 do_interrupt(env->exception_index);
380 #elif defined(TARGET_ARM)
382 #elif defined(TARGET_SH4)
384 #elif defined(TARGET_ALPHA)
386 #elif defined(TARGET_CRIS)
388 #elif defined(TARGET_M68K)
392 env->exception_index = -1;
395 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
397 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
398 ret = kqemu_cpu_exec(env);
399 /* put eflags in CPU temporary format */
400 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
401 DF = 1 - (2 * ((env->eflags >> 10) & 1));
402 CC_OP = CC_OP_EFLAGS;
403 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
406 longjmp(env->jmp_env, 1);
407 } else if (ret == 2) {
408 /* softmmu execution needed */
410 if (env->interrupt_request != 0) {
411 /* hardware interrupt will be executed just after */
413 /* otherwise, we restart */
414 longjmp(env->jmp_env, 1);
420 next_tb = 0; /* force lookup of first TB */
423 interrupt_request = env->interrupt_request;
424 if (__builtin_expect(interrupt_request, 0)
425 #if defined(TARGET_I386)
426 && env->hflags & HF_GIF_MASK
428 && !(env->singlestep_enabled & SSTEP_NOIRQ)) {
429 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
430 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
431 env->exception_index = EXCP_DEBUG;
434 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
435 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
436 if (interrupt_request & CPU_INTERRUPT_HALT) {
437 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
439 env->exception_index = EXCP_HLT;
443 #if defined(TARGET_I386)
444 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
445 !(env->hflags & HF_SMM_MASK)) {
446 svm_check_intercept(SVM_EXIT_SMI);
447 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
450 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
451 !(env->hflags & HF_NMI_MASK)) {
452 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
453 env->hflags |= HF_NMI_MASK;
454 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
456 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
457 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
458 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
460 svm_check_intercept(SVM_EXIT_INTR);
461 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
462 intno = cpu_get_pic_interrupt(env);
463 if (loglevel & CPU_LOG_TB_IN_ASM) {
464 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
466 do_interrupt(intno, 0, 0, 0, 1);
467 /* ensure that no TB jump will be modified as
468 the program flow was changed */
470 #if !defined(CONFIG_USER_ONLY)
471 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
472 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
474 /* FIXME: this should respect TPR */
475 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
476 svm_check_intercept(SVM_EXIT_VINTR);
477 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
478 if (loglevel & CPU_LOG_TB_IN_ASM)
479 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
480 do_interrupt(intno, 0, 0, -1, 1);
481 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
482 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
486 #elif defined(TARGET_PPC)
488 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
492 if (interrupt_request & CPU_INTERRUPT_HARD) {
493 ppc_hw_interrupt(env);
494 if (env->pending_interrupts == 0)
495 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
498 #elif defined(TARGET_MIPS)
499 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
500 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
501 (env->CP0_Status & (1 << CP0St_IE)) &&
502 !(env->CP0_Status & (1 << CP0St_EXL)) &&
503 !(env->CP0_Status & (1 << CP0St_ERL)) &&
504 !(env->hflags & MIPS_HFLAG_DM)) {
506 env->exception_index = EXCP_EXT_INTERRUPT;
511 #elif defined(TARGET_SPARC)
512 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
514 int pil = env->interrupt_index & 15;
515 int type = env->interrupt_index & 0xf0;
517 if (((type == TT_EXTINT) &&
518 (pil == 15 || pil > env->psrpil)) ||
520 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
521 do_interrupt(env->interrupt_index);
522 env->interrupt_index = 0;
523 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
528 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
529 //do_interrupt(0, 0, 0, 0, 0);
530 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
532 #elif defined(TARGET_ARM)
533 if (interrupt_request & CPU_INTERRUPT_FIQ
534 && !(env->uncached_cpsr & CPSR_F)) {
535 env->exception_index = EXCP_FIQ;
539 /* ARMv7-M interrupt return works by loading a magic value
540 into the PC. On real hardware the load causes the
541 return to occur. The qemu implementation performs the
542 jump normally, then does the exception return when the
543 CPU tries to execute code at the magic address.
544 This will cause the magic PC value to be pushed to
545 the stack if an interrupt occured at the wrong time.
546 We avoid this by disabling interrupts when
547 pc contains a magic address. */
548 if (interrupt_request & CPU_INTERRUPT_HARD
549 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
550 || !(env->uncached_cpsr & CPSR_I))) {
551 env->exception_index = EXCP_IRQ;
555 #elif defined(TARGET_SH4)
556 if (interrupt_request & CPU_INTERRUPT_HARD) {
560 #elif defined(TARGET_ALPHA)
561 if (interrupt_request & CPU_INTERRUPT_HARD) {
565 #elif defined(TARGET_CRIS)
566 if (interrupt_request & CPU_INTERRUPT_HARD) {
570 #elif defined(TARGET_M68K)
571 if (interrupt_request & CPU_INTERRUPT_HARD
572 && ((env->sr & SR_I) >> SR_I_SHIFT)
573 < env->pending_level) {
574 /* Real hardware gets the interrupt vector via an
575 IACK cycle at this point. Current emulated
576 hardware doesn't rely on this, so we
577 provide/save the vector when the interrupt is
579 env->exception_index = env->pending_vector;
584 /* Don't use the cached interupt_request value,
585 do_interrupt may have updated the EXITTB flag. */
586 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
587 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
588 /* ensure that no TB jump will be modified as
589 the program flow was changed */
592 if (interrupt_request & CPU_INTERRUPT_EXIT) {
593 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
594 env->exception_index = EXCP_INTERRUPT;
599 if ((loglevel & CPU_LOG_TB_CPU)) {
600 /* restore flags in standard format */
602 #if defined(TARGET_I386)
603 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
604 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
605 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
606 #elif defined(TARGET_ARM)
607 cpu_dump_state(env, logfile, fprintf, 0);
608 #elif defined(TARGET_SPARC)
609 REGWPTR = env->regbase + (env->cwp * 16);
610 env->regwptr = REGWPTR;
611 cpu_dump_state(env, logfile, fprintf, 0);
612 #elif defined(TARGET_PPC)
613 cpu_dump_state(env, logfile, fprintf, 0);
614 #elif defined(TARGET_M68K)
615 cpu_m68k_flush_flags(env, env->cc_op);
616 env->cc_op = CC_OP_FLAGS;
617 env->sr = (env->sr & 0xffe0)
618 | env->cc_dest | (env->cc_x << 4);
619 cpu_dump_state(env, logfile, fprintf, 0);
620 #elif defined(TARGET_MIPS)
621 cpu_dump_state(env, logfile, fprintf, 0);
622 #elif defined(TARGET_SH4)
623 cpu_dump_state(env, logfile, fprintf, 0);
624 #elif defined(TARGET_ALPHA)
625 cpu_dump_state(env, logfile, fprintf, 0);
626 #elif defined(TARGET_CRIS)
627 cpu_dump_state(env, logfile, fprintf, 0);
629 #error unsupported target CPU
635 if ((loglevel & CPU_LOG_EXEC)) {
636 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
637 (long)tb->tc_ptr, tb->pc,
638 lookup_symbol(tb->pc));
642 /* see if we can patch the calling TB. When the TB
643 spans two pages, we cannot safely do a direct
648 (env->kqemu_enabled != 2) &&
650 tb->page_addr[1] == -1) {
652 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
653 spin_unlock(&tb_lock);
657 env->current_tb = tb;
658 /* execute the generated code */
659 next_tb = tcg_qemu_tb_exec(tc_ptr);
660 env->current_tb = NULL;
661 /* reset soft MMU for next block (it can currently
662 only be set by a memory fault) */
663 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
664 if (env->hflags & HF_SOFTMMU_MASK) {
665 env->hflags &= ~HF_SOFTMMU_MASK;
666 /* do not allow linking to another block */
670 #if defined(USE_KQEMU)
671 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
672 if (kqemu_is_ok(env) &&
673 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
684 #if defined(TARGET_I386)
685 /* restore flags in standard format */
686 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
687 #elif defined(TARGET_ARM)
688 /* XXX: Save/restore host fpu exception state?. */
689 #elif defined(TARGET_SPARC)
690 #if defined(reg_REGWPTR)
691 REGWPTR = saved_regwptr;
693 #elif defined(TARGET_PPC)
694 #elif defined(TARGET_M68K)
695 cpu_m68k_flush_flags(env, env->cc_op);
696 env->cc_op = CC_OP_FLAGS;
697 env->sr = (env->sr & 0xffe0)
698 | env->cc_dest | (env->cc_x << 4);
699 #elif defined(TARGET_MIPS)
700 #elif defined(TARGET_SH4)
701 #elif defined(TARGET_ALPHA)
702 #elif defined(TARGET_CRIS)
705 #error unsupported target CPU
708 /* restore global registers */
710 #include "hostregs_helper.h"
712 /* fail safe : never use cpu_single_env outside cpu_exec() */
713 cpu_single_env = NULL;
717 /* must only be called from the generated code as an exception can be
719 void tb_invalidate_page_range(target_ulong start, target_ulong end)
721 /* XXX: cannot enable it yet because it yields to MMU exception
722 where NIP != read address on PowerPC */
724 target_ulong phys_addr;
725 phys_addr = get_phys_addr_code(env, start);
726 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
730 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
732 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
734 CPUX86State *saved_env;
738 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
740 cpu_x86_load_seg_cache(env, seg_reg, selector,
741 (selector << 4), 0xffff, 0);
743 helper_load_seg(seg_reg, selector);
748 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
750 CPUX86State *saved_env;
755 helper_fsave(ptr, data32);
760 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
762 CPUX86State *saved_env;
767 helper_frstor(ptr, data32);
772 #endif /* TARGET_I386 */
774 #if !defined(CONFIG_SOFTMMU)
776 #if defined(TARGET_I386)
778 /* 'pc' is the host PC at which the exception was raised. 'address' is
779 the effective address of the memory exception. 'is_write' is 1 if a
780 write caused the exception and otherwise 0'. 'old_set' is the
781 signal set which should be restored */
782 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
783 int is_write, sigset_t *old_set,
786 TranslationBlock *tb;
790 env = cpu_single_env; /* XXX: find a correct solution for multithread */
791 #if defined(DEBUG_SIGNAL)
792 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
793 pc, address, is_write, *(unsigned long *)old_set);
795 /* XXX: locking issue */
796 if (is_write && page_unprotect(h2g(address), pc, puc)) {
800 /* see if it is an MMU fault */
801 ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
803 return 0; /* not an MMU fault */
805 return 1; /* the MMU fault was handled without causing real CPU fault */
806 /* now we have a real cpu fault */
809 /* the PC is inside the translated code. It means that we have
810 a virtual CPU fault */
811 cpu_restore_state(tb, env, pc, puc);
815 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
816 env->eip, env->cr[2], env->error_code);
818 /* we restore the process signal mask as the sigreturn should
819 do it (XXX: use sigsetjmp) */
820 sigprocmask(SIG_SETMASK, old_set, NULL);
821 raise_exception_err(env->exception_index, env->error_code);
823 /* activate soft MMU for this block */
824 env->hflags |= HF_SOFTMMU_MASK;
825 cpu_resume_from_signal(env, puc);
827 /* never comes here */
831 #elif defined(TARGET_ARM)
832 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
833 int is_write, sigset_t *old_set,
836 TranslationBlock *tb;
840 env = cpu_single_env; /* XXX: find a correct solution for multithread */
841 #if defined(DEBUG_SIGNAL)
842 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
843 pc, address, is_write, *(unsigned long *)old_set);
845 /* XXX: locking issue */
846 if (is_write && page_unprotect(h2g(address), pc, puc)) {
849 /* see if it is an MMU fault */
850 ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
852 return 0; /* not an MMU fault */
854 return 1; /* the MMU fault was handled without causing real CPU fault */
855 /* now we have a real cpu fault */
858 /* the PC is inside the translated code. It means that we have
859 a virtual CPU fault */
860 cpu_restore_state(tb, env, pc, puc);
862 /* we restore the process signal mask as the sigreturn should
863 do it (XXX: use sigsetjmp) */
864 sigprocmask(SIG_SETMASK, old_set, NULL);
866 /* never comes here */
869 #elif defined(TARGET_SPARC)
870 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
871 int is_write, sigset_t *old_set,
874 TranslationBlock *tb;
878 env = cpu_single_env; /* XXX: find a correct solution for multithread */
879 #if defined(DEBUG_SIGNAL)
880 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
881 pc, address, is_write, *(unsigned long *)old_set);
883 /* XXX: locking issue */
884 if (is_write && page_unprotect(h2g(address), pc, puc)) {
887 /* see if it is an MMU fault */
888 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
890 return 0; /* not an MMU fault */
892 return 1; /* the MMU fault was handled without causing real CPU fault */
893 /* now we have a real cpu fault */
896 /* the PC is inside the translated code. It means that we have
897 a virtual CPU fault */
898 cpu_restore_state(tb, env, pc, puc);
900 /* we restore the process signal mask as the sigreturn should
901 do it (XXX: use sigsetjmp) */
902 sigprocmask(SIG_SETMASK, old_set, NULL);
904 /* never comes here */
907 #elif defined (TARGET_PPC)
908 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
909 int is_write, sigset_t *old_set,
912 TranslationBlock *tb;
916 env = cpu_single_env; /* XXX: find a correct solution for multithread */
917 #if defined(DEBUG_SIGNAL)
918 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
919 pc, address, is_write, *(unsigned long *)old_set);
921 /* XXX: locking issue */
922 if (is_write && page_unprotect(h2g(address), pc, puc)) {
926 /* see if it is an MMU fault */
927 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
929 return 0; /* not an MMU fault */
931 return 1; /* the MMU fault was handled without causing real CPU fault */
933 /* now we have a real cpu fault */
936 /* the PC is inside the translated code. It means that we have
937 a virtual CPU fault */
938 cpu_restore_state(tb, env, pc, puc);
942 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
943 env->nip, env->error_code, tb);
945 /* we restore the process signal mask as the sigreturn should
946 do it (XXX: use sigsetjmp) */
947 sigprocmask(SIG_SETMASK, old_set, NULL);
948 do_raise_exception_err(env->exception_index, env->error_code);
950 /* activate soft MMU for this block */
951 cpu_resume_from_signal(env, puc);
953 /* never comes here */
957 #elif defined(TARGET_M68K)
958 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
959 int is_write, sigset_t *old_set,
962 TranslationBlock *tb;
966 env = cpu_single_env; /* XXX: find a correct solution for multithread */
967 #if defined(DEBUG_SIGNAL)
968 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
969 pc, address, is_write, *(unsigned long *)old_set);
971 /* XXX: locking issue */
972 if (is_write && page_unprotect(address, pc, puc)) {
975 /* see if it is an MMU fault */
976 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
978 return 0; /* not an MMU fault */
980 return 1; /* the MMU fault was handled without causing real CPU fault */
981 /* now we have a real cpu fault */
984 /* the PC is inside the translated code. It means that we have
985 a virtual CPU fault */
986 cpu_restore_state(tb, env, pc, puc);
988 /* we restore the process signal mask as the sigreturn should
989 do it (XXX: use sigsetjmp) */
990 sigprocmask(SIG_SETMASK, old_set, NULL);
992 /* never comes here */
996 #elif defined (TARGET_MIPS)
997 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
998 int is_write, sigset_t *old_set,
1001 TranslationBlock *tb;
1005 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1006 #if defined(DEBUG_SIGNAL)
1007 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1008 pc, address, is_write, *(unsigned long *)old_set);
1010 /* XXX: locking issue */
1011 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1015 /* see if it is an MMU fault */
1016 ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1018 return 0; /* not an MMU fault */
1020 return 1; /* the MMU fault was handled without causing real CPU fault */
1022 /* now we have a real cpu fault */
1023 tb = tb_find_pc(pc);
1025 /* the PC is inside the translated code. It means that we have
1026 a virtual CPU fault */
1027 cpu_restore_state(tb, env, pc, puc);
1031 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1032 env->PC, env->error_code, tb);
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
1036 sigprocmask(SIG_SETMASK, old_set, NULL);
1037 do_raise_exception_err(env->exception_index, env->error_code);
1039 /* activate soft MMU for this block */
1040 cpu_resume_from_signal(env, puc);
1042 /* never comes here */
1046 #elif defined (TARGET_SH4)
1047 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1048 int is_write, sigset_t *old_set,
1051 TranslationBlock *tb;
1055 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1056 #if defined(DEBUG_SIGNAL)
1057 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1058 pc, address, is_write, *(unsigned long *)old_set);
1060 /* XXX: locking issue */
1061 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1065 /* see if it is an MMU fault */
1066 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1068 return 0; /* not an MMU fault */
1070 return 1; /* the MMU fault was handled without causing real CPU fault */
1072 /* now we have a real cpu fault */
1073 tb = tb_find_pc(pc);
1075 /* the PC is inside the translated code. It means that we have
1076 a virtual CPU fault */
1077 cpu_restore_state(tb, env, pc, puc);
1080 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1081 env->nip, env->error_code, tb);
1083 /* we restore the process signal mask as the sigreturn should
1084 do it (XXX: use sigsetjmp) */
1085 sigprocmask(SIG_SETMASK, old_set, NULL);
1087 /* never comes here */
1091 #elif defined (TARGET_ALPHA)
1092 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1093 int is_write, sigset_t *old_set,
1096 TranslationBlock *tb;
1100 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1101 #if defined(DEBUG_SIGNAL)
1102 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1103 pc, address, is_write, *(unsigned long *)old_set);
1105 /* XXX: locking issue */
1106 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1110 /* see if it is an MMU fault */
1111 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1113 return 0; /* not an MMU fault */
1115 return 1; /* the MMU fault was handled without causing real CPU fault */
1117 /* now we have a real cpu fault */
1118 tb = tb_find_pc(pc);
1120 /* the PC is inside the translated code. It means that we have
1121 a virtual CPU fault */
1122 cpu_restore_state(tb, env, pc, puc);
1125 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1126 env->nip, env->error_code, tb);
1128 /* we restore the process signal mask as the sigreturn should
1129 do it (XXX: use sigsetjmp) */
1130 sigprocmask(SIG_SETMASK, old_set, NULL);
1132 /* never comes here */
1135 #elif defined (TARGET_CRIS)
1136 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1137 int is_write, sigset_t *old_set,
1140 TranslationBlock *tb;
1144 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1145 #if defined(DEBUG_SIGNAL)
1146 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1147 pc, address, is_write, *(unsigned long *)old_set);
1149 /* XXX: locking issue */
1150 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1154 /* see if it is an MMU fault */
1155 ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1157 return 0; /* not an MMU fault */
1159 return 1; /* the MMU fault was handled without causing real CPU fault */
1161 /* now we have a real cpu fault */
1162 tb = tb_find_pc(pc);
1164 /* the PC is inside the translated code. It means that we have
1165 a virtual CPU fault */
1166 cpu_restore_state(tb, env, pc, puc);
1168 /* we restore the process signal mask as the sigreturn should
1169 do it (XXX: use sigsetjmp) */
1170 sigprocmask(SIG_SETMASK, old_set, NULL);
1172 /* never comes here */
1177 #error unsupported target CPU
1180 #if defined(__i386__)
1182 #if defined(__APPLE__)
1183 # include <sys/ucontext.h>
1185 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1186 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1187 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1189 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1190 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1191 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1194 int cpu_signal_handler(int host_signum, void *pinfo,
1197 siginfo_t *info = pinfo;
1198 struct ucontext *uc = puc;
1206 #define REG_TRAPNO TRAPNO
1209 trapno = TRAP_sig(uc);
1210 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1212 (ERROR_sig(uc) >> 1) & 1 : 0,
1213 &uc->uc_sigmask, puc);
1216 #elif defined(__x86_64__)
1218 int cpu_signal_handler(int host_signum, void *pinfo,
1221 siginfo_t *info = pinfo;
1222 struct ucontext *uc = puc;
1225 pc = uc->uc_mcontext.gregs[REG_RIP];
1226 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1227 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1228 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1229 &uc->uc_sigmask, puc);
1232 #elif defined(__powerpc__)
1234 /***********************************************************************
1235 * signal context platform-specific definitions
1239 /* All Registers access - only for local access */
1240 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1241 /* Gpr Registers access */
1242 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1243 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1244 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1245 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1246 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1247 # define LR_sig(context) REG_sig(link, context) /* Link register */
1248 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1249 /* Float Registers access */
1250 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1251 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1252 /* Exception Registers access */
1253 # define DAR_sig(context) REG_sig(dar, context)
1254 # define DSISR_sig(context) REG_sig(dsisr, context)
1255 # define TRAP_sig(context) REG_sig(trap, context)
1259 # include <sys/ucontext.h>
1260 typedef struct ucontext SIGCONTEXT;
1261 /* All Registers access - only for local access */
1262 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1263 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1264 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1265 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1266 /* Gpr Registers access */
1267 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1268 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1269 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1270 # define CTR_sig(context) REG_sig(ctr, context)
1271 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1272 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1273 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1274 /* Float Registers access */
1275 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1276 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1277 /* Exception Registers access */
1278 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1279 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1280 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1281 #endif /* __APPLE__ */
1283 int cpu_signal_handler(int host_signum, void *pinfo,
1286 siginfo_t *info = pinfo;
1287 struct ucontext *uc = puc;
1295 if (DSISR_sig(uc) & 0x00800000)
1298 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1301 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1302 is_write, &uc->uc_sigmask, puc);
1305 #elif defined(__alpha__)
1307 int cpu_signal_handler(int host_signum, void *pinfo,
1310 siginfo_t *info = pinfo;
1311 struct ucontext *uc = puc;
1312 uint32_t *pc = uc->uc_mcontext.sc_pc;
1313 uint32_t insn = *pc;
1316 /* XXX: need kernel patch to get write flag faster */
1317 switch (insn >> 26) {
1332 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1333 is_write, &uc->uc_sigmask, puc);
1335 #elif defined(__sparc__)
1337 int cpu_signal_handler(int host_signum, void *pinfo,
1340 siginfo_t *info = pinfo;
1341 uint32_t *regs = (uint32_t *)(info + 1);
1342 void *sigmask = (regs + 20);
1347 /* XXX: is there a standard glibc define ? */
1349 /* XXX: need kernel patch to get write flag faster */
1351 insn = *(uint32_t *)pc;
1352 if ((insn >> 30) == 3) {
1353 switch((insn >> 19) & 0x3f) {
1365 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1366 is_write, sigmask, NULL);
1369 #elif defined(__arm__)
1371 int cpu_signal_handler(int host_signum, void *pinfo,
1374 siginfo_t *info = pinfo;
1375 struct ucontext *uc = puc;
1379 pc = uc->uc_mcontext.arm_pc;
1380 /* XXX: compute is_write */
1382 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1384 &uc->uc_sigmask, puc);
1387 #elif defined(__mc68000)
1389 int cpu_signal_handler(int host_signum, void *pinfo,
1392 siginfo_t *info = pinfo;
1393 struct ucontext *uc = puc;
1397 pc = uc->uc_mcontext.gregs[16];
1398 /* XXX: compute is_write */
1400 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1402 &uc->uc_sigmask, puc);
1405 #elif defined(__ia64)
1408 /* This ought to be in <bits/siginfo.h>... */
1409 # define __ISR_VALID 1
1412 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1414 siginfo_t *info = pinfo;
1415 struct ucontext *uc = puc;
1419 ip = uc->uc_mcontext.sc_ip;
1420 switch (host_signum) {
1426 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1427 /* ISR.W (write-access) is bit 33: */
1428 is_write = (info->si_isr >> 33) & 1;
1434 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1436 &uc->uc_sigmask, puc);
1439 #elif defined(__s390__)
1441 int cpu_signal_handler(int host_signum, void *pinfo,
1444 siginfo_t *info = pinfo;
1445 struct ucontext *uc = puc;
1449 pc = uc->uc_mcontext.psw.addr;
1450 /* XXX: compute is_write */
1452 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1453 is_write, &uc->uc_sigmask, puc);
1456 #elif defined(__mips__)
1458 int cpu_signal_handler(int host_signum, void *pinfo,
1461 siginfo_t *info = pinfo;
1462 struct ucontext *uc = puc;
1463 greg_t pc = uc->uc_mcontext.pc;
1466 /* XXX: compute is_write */
1468 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1469 is_write, &uc->uc_sigmask, puc);
1472 #elif defined(__hppa__)
1474 int cpu_signal_handler(int host_signum, void *pinfo,
1477 struct siginfo *info = pinfo;
1478 struct ucontext *uc = puc;
1482 pc = uc->uc_mcontext.sc_iaoq[0];
1483 /* FIXME: compute is_write */
1485 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1487 &uc->uc_sigmask, puc);
1492 #error host CPU specific signal handler needed
1496 #endif /* !defined(CONFIG_SOFTMMU) */