4 * http://www.dave-tech.it
5 * http://www.wawnet.biz
6 * mailto:info@wawnet.biz
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * S3C44B0 CPU specific code
33 #include <asm/hardware.h>
35 static void s3c44b0_flush_cache(void)
39 for(i=0x10002000;i<0x10004800;i+=16)
53 int cleanup_before_linux (void)
56 cache memory should be enabled before calling
57 Linux to make the kernel uncompression faster
61 disable_interrupts ();
66 void reset_cpu (ulong addr)
69 reset the cpu using watchdog
72 /* Disable the watchdog.*/
75 /* set the timeout value to a short time... */
78 /* Enable the watchdog. */
87 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
89 disable_interrupts ();
96 void icache_enable (void)
100 s3c44b0_flush_cache();
104 Non-cacheable area (everything outside RAM)
105 0x0000:0000 - 0x0C00:0000
107 NCACHBE0 = 0xC0000000;
108 NCACHBE1 = 0x00000000;
114 reg |= 0x00000006; /* 8kB */
118 void icache_disable (void)
123 reg &= ~0x00000006; /* 8kB */
127 int icache_status (void)
132 void dcache_enable (void)
137 void dcache_disable (void)
142 int dcache_status (void)
144 return dcache_status();
152 #define BCD2HEX(n) ((n>>4)*10+(n&0x0f))
155 #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10)
158 int rtc_get (struct rtc_time* tm)
161 tm->tm_year = BCD2HEX(BCDYEAR);
162 tm->tm_mon = BCD2HEX(BCDMON);
163 tm->tm_wday = BCD2HEX(BCDDATE);
164 tm->tm_mday = BCD2HEX(BCDDAY);
165 tm->tm_hour = BCD2HEX(BCDHOUR);
166 tm->tm_min = BCD2HEX(BCDMIN);
167 tm->tm_sec = BCD2HEX(BCDSEC);
170 /* we have to re-read the rtc data because of the "one second deviation" problem */
171 /* see RTC datasheet for more info about it */
172 tm->tm_year = BCD2HEX(BCDYEAR);
173 tm->tm_mon = BCD2HEX(BCDMON);
174 tm->tm_mday = BCD2HEX(BCDDAY);
175 tm->tm_wday = BCD2HEX(BCDDATE);
176 tm->tm_hour = BCD2HEX(BCDHOUR);
177 tm->tm_min = BCD2HEX(BCDMIN);
178 tm->tm_sec = BCD2HEX(BCDSEC);
183 if(tm->tm_year >= 70)
191 void rtc_set (struct rtc_time* tm)
193 if(tm->tm_year < 2000)
199 BCDYEAR = HEX2BCD(tm->tm_year);
200 BCDMON = HEX2BCD(tm->tm_mon);
201 BCDDAY = HEX2BCD(tm->tm_mday);
202 BCDDATE = HEX2BCD(tm->tm_wday);
203 BCDHOUR = HEX2BCD(tm->tm_hour);
204 BCDMIN = HEX2BCD(tm->tm_min);
205 BCDSEC = HEX2BCD(tm->tm_sec);
209 void rtc_reset (void)
228 * Initialization, must be called once on start up, may be called
229 * repeatedly to change the speed and slave addresses.
231 void i2c_init(int speed, int slaveaddr)
234 setting up I2C support
236 unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
241 rPCONF = ((save_F & ~(0xF))| 0xa);
242 rPUPF = (save_PF | 0x3);
243 PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
244 PUPF = rPUPF; /* Disable pull-up */
246 /* Configuring pin for WC pin of EEprom */
256 Enable ACK, IICCLK=MCLK/16, enable interrupt
257 75Mhz/16/(12+1) = 390625 Hz
259 rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
266 * Probe the given I2C chip address. Returns 0 if a chip responded,
269 int i2c_probe(uchar chip)
275 printf("i2c_probe chip %d\n", (int) chip);
280 * Read/Write interface:
281 * chip: I2C chip address, range 0..127
282 * addr: Memory (register) address within the chip
283 * alen: Number of bytes to use for addr (typically 1, 2 for larger
284 * memories, 0 for register type devices with only one
286 * buffer: Where to read/write the data
287 * len: How many bytes to read/write
289 * Returns: 0 on success, not 0 on failure
292 #define S3C44B0X_rIIC_INTPEND (1<<4)
293 #define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0)
294 #define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5)
295 #define S3C44B0_IIC_TIMEOUT 100
297 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
304 send the device offset
310 IICDS = chip; /* this is a write operation... */
315 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
317 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
321 if (k==S3C44B0_IIC_TIMEOUT)
324 /* wait and check ACK */
326 if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
330 IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
332 /* wait and check ACK */
333 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
335 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
339 if (k==S3C44B0_IIC_TIMEOUT)
343 if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
347 now we can start with the read operation...
350 IICDS = chip | 0x01; /* this is a read operation... */
352 rIICSTAT = 0x90; /*master recv*/
356 IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
358 /* wait and check ACK */
359 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
361 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
365 if (k==S3C44B0_IIC_TIMEOUT)
369 if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
372 for (j=0; j<len-1; j++) {
374 /*clear pending bit to resume */
376 temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
379 /* wait and check ACK */
380 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
382 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
386 if (k==S3C44B0_IIC_TIMEOUT)
390 buffer[j] = IICDS; /*save readed data*/
395 reading the last data
398 temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
401 /* wait but NOT check ACK */
402 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
404 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
408 if (k==S3C44B0_IIC_TIMEOUT)
411 buffer[j] = IICDS; /*save readed data*/
413 rIICSTAT = 0x90; /*master recv*/
415 /* Write operation Terminate sending STOP */
417 /*Clear Int Pending Bit to RESUME*/
419 IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
421 IICCON = IICCON | (1<<7); /*restore ACK generation*/
426 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
433 send the device offset
439 IICDS = chip; /* this is a write operation... */
444 IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
446 /* wait and check ACK */
447 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
449 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
453 if (k==S3C44B0_IIC_TIMEOUT)
457 if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
461 IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
463 /* wait and check ACK */
464 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
466 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
470 if (k==S3C44B0_IIC_TIMEOUT)
474 if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
478 now we can start with the read write operation
480 for (j=0; j<len; j++) {
482 IICDS = buffer[j]; /*prerare data to write*/
484 /*clear pending bit to resume*/
486 temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
489 /* wait but NOT check ACK */
490 for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
492 if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
498 if (k==S3C44B0_IIC_TIMEOUT)
503 /* sending stop to terminate */
504 rIICSTAT = 0xD0; /*master send*/
506 /*Clear Int Pending Bit to RESUME*/
508 IICCON = temp & (~S3C44B0X_rIIC_INTPEND);