cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloehm <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from memory!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 _TEXT_BASE:
  65         .word   TEXT_BASE
  66
  67 .globl _armboot_start
  68 _armboot_start:
  69         .word _start
  70
  71 /*
  72  * Note: _armboot_end_data and _armboot_end are defined
  73  * by the (board-dependent) linker script.
  74  * _armboot_end_data is the first usable FLASH address after armboot
  75  */
  76 .globl _armboot_end_data
  77 _armboot_end_data:
  78         .word armboot_end_data
  79 .globl _armboot_end
  80 _armboot_end:
  81         .word armboot_end
  82
  83 /*
  84  * This is defined in the board specific linker script
  85  */
  86 .globl _bss_start
  87 _bss_start:
  88         .word bss_start
  89
  90 .globl _bss_end
  91 _bss_end:
  92         .word bss_end
  93
  94 /*
  95  * _armboot_real_end is the first usable RAM address behind armboot
  96  * and the various stacks
  97  */
  98 .globl _armboot_real_end
  99 _armboot_real_end:
 100         .word 0x0badc0de
 101
 102 /*
 103  * We relocate uboot to this address (end of RAM - 128 KiB)
 104  */
 105 .globl _uboot_reloc
 106 _uboot_reloc:
 107         .word TEXT_BASE
 108
 109 #ifdef CONFIG_USE_IRQ
 110 /* IRQ stack memory (calculated at run-time) */
 111 .globl IRQ_STACK_START
 112 IRQ_STACK_START:
 113         .word   0x0badc0de
 114
 115 /* IRQ stack memory (calculated at run-time) */
 116 .globl FIQ_STACK_START
 117 FIQ_STACK_START:
 118         .word 0x0badc0de
 119 #endif
 120
 121
 122 /****************************************************************************/
 123 /*                                                                          */
 124 /* the actual reset code                                                    */
 125 /*                                                                          */
 126 /****************************************************************************/
 127
 128 reset:
 129         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 130         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 131         orr     r0,r0,#0x13
 132         msr     cpsr,r0
 133
 134         bl      cpu_init_crit           /* we do sys-critical inits         */
 135
 136 relocate:                               /* relocate U-Boot to RAM           */
 137         adr     r0, _start              /* r0 <- current position of code   */
 138         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 139         cmp     r0, r1                  /* don't reloc during debug         */
 140         beq     stack_setup
 141
 142         ldr     r2, _armboot_start
 143         ldr     r3, _armboot_end
 144         sub     r2, r3, r2              /* r2 <- size of armboot            */
 145         add     r2, r0, r2              /* r2 <- source end address         */
 146
 147 copy_loop:
 148         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 149         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 150         cmp     r0, r2                  /* until source end addreee [r2]    */
 151         ble     copy_loop
 152
 153         /* Set up the stack                                                 */
 154
 155 stack_setup:
 156
 157         ldr     r0, _uboot_reloc        /* upper 128 KiB: relocated uboot   */
 158         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 159                                         /* FIXME: bdinfo should be here     */
 160         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 161
 162 clear_bss:
 163
 164         ldr     r0, _bss_start          /* find start of bss segment        */
 165         add     r0, r0, #4              /* start at first byte of bss       */
 166         ldr     r1, _bss_end            /* stop here                        */
 167         mov     r2, #0x00000000         /* clear                            */
 168
 169 clbss_l:str     r2, [r0]                /* clear loop...                    */
 170         add     r0, r0, #4
 171         cmp     r0, r1
 172         bne     clbss_l
 173
 174
 175         ldr     pc, _start_armboot
 176
 177 _start_armboot: .word start_armboot
 178
 179
 180 /****************************************************************************/
 181 /*                                                                          */
 182 /* CPU_init_critical registers                                              */
 183 /*                                                                          */
 184 /* - setup important registers                                              */
 185 /* - setup memory timing                                                    */
 186 /*                                                                          */
 187 /****************************************************************************/
 188
 189 /* Interrupt-Controller base address                                        */
 190 IC_BASE:           .word           0x40d00000
 191 #define ICMR    0x04
 192
 193 /* Reset-Controller */
 194 RST_BASE:       .word   0x40f00030
 195 #define RCSR    0x00
 196
 197 /* Operating System Timer */
 198 OSTIMER_BASE:   .word   0x40a00000
 199 #define OSMR3   0x0C
 200 #define OSCR    0x10
 201 #define OWER    0x18
 202 #define OIER    0x1C
 203
 204 /* Clock Manager Registers                                                  */
 205 CC_BASE:        .word   0x41300000
 206 #define CCCR    0x00
 207 cpuspeed:       .word   CFG_CPUSPEED
 208
 209
 210         /* RS: ???                                                          */
 211         .macro CPWAIT
 212         mrc  p15,0,r0,c2,c0,0
 213         mov  r0,r0
 214         sub  pc,pc,#4
 215         .endm
 216
 217
 218 cpu_init_crit:
 219
 220         /* mask all IRQs                                                    */
 221         ldr     r0, IC_BASE
 222         mov     r1, #0x00
 223         str     r1, [r0, #ICMR]
 224
 225 #if defined(CFG_CPUSPEED)
 226
 227         /* set clock speed */
 228         ldr     r0, CC_BASE
 229         ldr     r1, cpuspeed
 230         str     r1, [r0, #CCCR]
 231         mov     r0, #2
 232         mcr     p14, 0, r0, c6, c0, 0
 233
 234 setspeed_done:
 235 #endif
 236
 237         /*
 238          * before relocating, we have to setup RAM timing
 239          * because memory timing is board-dependend, you will
 240          * find a memsetup.S in your board directory.
 241          */
 242         mov     ip,     lr
 243         bl      memsetup
 244         mov     lr,     ip
 245
 246         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 247
 248         ldr     r0, =0x2001             /* enable access to all coproc.     */
 249         mcr     p15, 0, r0, c15, c1, 0
 250         CPWAIT
 251
 252         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 253         CPWAIT
 254
 255         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 256         CPWAIT
 257
 258         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 259         CPWAIT
 260
 261         /* Enable the Icache                                                */
 262 /*
 263         mrc     p15, 0, r0, c1, c0, 0
 264         orr     r0, r0, #0x1800
 265         mcr     p15, 0, r0, c1, c0, 0
 266         CPWAIT
 267 */
 268         mov     pc, lr
 269
 270
 271 /****************************************************************************/
 272 /*                                                                          */
 273 /* Interrupt handling                                                       */
 274 /*                                                                          */
 275 /****************************************************************************/
 276
 277 /* IRQ stack frame                                                          */
 278
 279 #define S_FRAME_SIZE    72
 280
 281 #define S_OLD_R0        68
 282 #define S_PSR           64
 283 #define S_PC            60
 284 #define S_LR            56
 285 #define S_SP            52
 286
 287 #define S_IP            48
 288 #define S_FP            44
 289 #define S_R10           40
 290 #define S_R9            36
 291 #define S_R8            32
 292 #define S_R7            28
 293 #define S_R6            24
 294 #define S_R5            20
 295 #define S_R4            16
 296 #define S_R3            12
 297 #define S_R2            8
 298 #define S_R1            4
 299 #define S_R0            0
 300
 301 #define MODE_SVC 0x13
 302
 303         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 304
 305         .macro  bad_save_user_regs
 306         sub     sp, sp, #S_FRAME_SIZE
 307         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 308         add     r8, sp, #S_PC
 309
 310         ldr     r2, _armboot_end
 311         add     r2, r2, #CONFIG_STACKSIZE
 312         sub     r2, r2, #8
 313         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 314         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 315
 316         add     r5, sp, #S_SP
 317         mov     r1, lr
 318         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 319         mov     r0, sp
 320         .endm
 321
 322
 323         /* use irq_save_user_regs / irq_restore_user_regs for                */
 324         /* IRQ/FIQ handling                                                  */
 325
 326         .macro  irq_save_user_regs
 327         sub     sp, sp, #S_FRAME_SIZE
 328         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 329         add     r8, sp, #S_PC
 330         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 331         str     lr, [r8, #0]                    /* Save calling PC           */
 332         mrs     r6, spsr
 333         str     r6, [r8, #4]                    /* Save CPSR                 */
 334         str     r0, [r8, #8]                    /* Save OLD_R0               */
 335         mov     r0, sp
 336         .endm
 337
 338         .macro  irq_restore_user_regs
 339         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 340         mov     r0, r0
 341         ldr     lr, [sp, #S_PC]                 @ Get PC
 342         add     sp, sp, #S_FRAME_SIZE
 343         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 344         .endm
 345
 346         .macro get_bad_stack
 347         ldr     r13, _armboot_end               @ setup our mode stack
 348         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 349         sub     r13, r13, #8
 350
 351         str     lr, [r13]                       @ save caller lr / spsr
 352         mrs     lr, spsr
 353         str     lr, [r13, #4]
 354
 355         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 356         msr     spsr_c, r13
 357         mov     lr, pc
 358         movs    pc, lr
 359         .endm
 360
 361         .macro get_irq_stack                    @ setup IRQ stack
 362         ldr     sp, IRQ_STACK_START
 363         .endm
 364
 365         .macro get_fiq_stack                    @ setup FIQ stack
 366         ldr     sp, FIQ_STACK_START
 367         .endm
 368
 369
 370 /****************************************************************************/
 371 /*                                                                          */
 372 /* exception handlers                                                       */
 373 /*                                                                          */
 374 /****************************************************************************/
 375
 376         .align  5
 377 undefined_instruction:
 378         get_bad_stack
 379         bad_save_user_regs
 380         bl      do_undefined_instruction
 381
 382         .align  5
 383 software_interrupt:
 384         get_bad_stack
 385         bad_save_user_regs
 386         bl      do_software_interrupt
 387
 388         .align  5
 389 prefetch_abort:
 390         get_bad_stack
 391         bad_save_user_regs
 392         bl      do_prefetch_abort
 393
 394         .align  5
 395 data_abort:
 396         get_bad_stack
 397         bad_save_user_regs
 398         bl      do_data_abort
 399
 400         .align  5
 401 not_used:
 402         get_bad_stack
 403         bad_save_user_regs
 404         bl      do_not_used
 405
 406 #ifdef CONFIG_USE_IRQ
 407
 408         .align  5
 409 irq:
 410         get_irq_stack
 411         irq_save_user_regs
 412         bl      do_irq
 413         irq_restore_user_regs
 414
 415         .align  5
 416 fiq:
 417         get_fiq_stack
 418         irq_save_user_regs              /* someone ought to write a more    */
 419         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 420         irq_restore_user_regs
 421
 422 #else
 423
 424         .align  5
 425 irq:
 426         get_bad_stack
 427         bad_save_user_regs
 428         bl      do_irq
 429
 430         .align  5
 431 fiq:
 432         get_bad_stack
 433         bad_save_user_regs
 434         bl      do_fiq
 435
 436 #endif
 437
 438 /****************************************************************************/
 439 /*                                                                          */
 440 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 441 /* perform a watchdog timeout for a soft reset.                             */
 442 /*                                                                          */
 443 /****************************************************************************/
 444
 445         .align  5
 446 .globl reset_cpu
 447
 448         /* FIXME: this code is PXA250 specific. How is this handled on      */
 449         /*        other XScale processors?                                  */
 450
 451 reset_cpu:
 452
 453         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 454
 455         ldr     r0, OSTIMER_BASE
 456         ldr     r1, [r0, #OWER]
 457         orr     r1, r1, #0x0001                 /* bit0: WME                */
 458         str     r1, [r0, #OWER]
 459
 460         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 461         /* the match register as well.                                      */
 462
 463         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 464         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 465         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 466         str     r1, [r0, #OSMR3]
 467
 468 reset_endless:
 469
 470         b       reset_endless