cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/pxa-regs.h>
  34
  35 .globl _start
  36 _start: b       reset
  37         ldr     pc, _undefined_instruction
  38         ldr     pc, _software_interrupt
  39         ldr     pc, _prefetch_abort
  40         ldr     pc, _data_abort
  41         ldr     pc, _not_used
  42         ldr     pc, _irq
  43         ldr     pc, _fiq
  44
  45 _undefined_instruction: .word undefined_instruction
  46 _software_interrupt:    .word software_interrupt
  47 _prefetch_abort:        .word prefetch_abort
  48 _data_abort:            .word data_abort
  49 _not_used:              .word not_used
  50 _irq:                   .word irq
  51 _fiq:                   .word fiq
  52
  53         .balignl 16,0xdeadbeef
  54
  55
  56 /*
  57  * Startup Code (reset vector)
  58  *
  59  * do important init only if we don't start from RAM!
  60  * - relocate armboot to ram
  61  * - setup stack
  62  * - jump to second stage
  63  */
  64
  65 _TEXT_BASE:
  66         .word   TEXT_BASE
  67
  68 .globl _armboot_start
  69 _armboot_start:
  70         .word _start
  71
  72 /*
  73  * These are defined in the board-specific linker script.
  74  */
  75 .globl _bss_start
  76 _bss_start:
  77         .word __bss_start
  78
  79 .globl _bss_end
  80 _bss_end:
  81         .word _end
  82
  83 #ifdef CONFIG_USE_IRQ
  84 /* IRQ stack memory (calculated at run-time) */
  85 .globl IRQ_STACK_START
  86 IRQ_STACK_START:
  87         .word   0x0badc0de
  88
  89 /* IRQ stack memory (calculated at run-time) */
  90 .globl FIQ_STACK_START
  91 FIQ_STACK_START:
  92         .word 0x0badc0de
  93 #endif
  94
  95
  96 /****************************************************************************/
  97 /*                                                                          */
  98 /* the actual reset code                                                    */
  99 /*                                                                          */
 100 /****************************************************************************/
 101
 102 reset:
 103         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 104         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 105         orr     r0,r0,#0x13
 106         msr     cpsr,r0
 107
 108         /*
 109          * we do sys-critical inits only at reboot,
 110          * not when booting from ram!
 111          */
 112 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 113         bl      cpu_init_crit           /* we do sys-critical inits         */
 114 #endif
 115
 116 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 117 relocate:                               /* relocate U-Boot to RAM           */
 118         adr     r0, _start              /* r0 <- current position of code   */
 119         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 120         cmp     r0, r1                  /* don't reloc during debug         */
 121         beq     stack_setup
 122
 123         ldr     r2, _armboot_start
 124         ldr     r3, _bss_start
 125         sub     r2, r3, r2              /* r2 <- size of armboot            */
 126         add     r2, r0, r2              /* r2 <- source end address         */
 127
 128 copy_loop:
 129         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 130         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 131         cmp     r0, r2                  /* until source end addreee [r2]    */
 132         ble     copy_loop
 133 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 134
 135         /* Set up the stack                                                 */
 136 stack_setup:
 137         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 138         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 139         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 140 #ifdef CONFIG_USE_IRQ
 141         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 142 #endif
 143         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 144
 145 clear_bss:
 146         ldr     r0, _bss_start          /* find start of bss segment        */
 147         ldr     r1, _bss_end            /* stop here                        */
 148         mov     r2, #0x00000000         /* clear                            */
 149
 150 clbss_l:str     r2, [r0]                /* clear loop...                    */
 151         add     r0, r0, #4
 152         cmp     r0, r1
 153         ble     clbss_l
 154
 155         ldr     pc, _start_armboot
 156
 157 _start_armboot: .word start_armboot
 158
 159
 160 /****************************************************************************/
 161 /*                                                                          */
 162 /* CPU_init_critical registers                                              */
 163 /*                                                                          */
 164 /* - setup important registers                                              */
 165 /* - setup memory timing                                                    */
 166 /*                                                                          */
 167 /****************************************************************************/
 168 /* mk@tbd: Fix this! */
 169 #ifdef CONFIG_CPU_MONAHANS
 170 #undef ICMR
 171 #undef OSMR3
 172 #undef OSCR
 173 #undef OWER
 174 #undef OIER
 175 #endif
 176
 177 /* Interrupt-Controller base address                                        */
 178 IC_BASE:           .word           0x40d00000
 179 #define ICMR    0x04
 180
 181 /* Reset-Controller */
 182 RST_BASE:       .word   0x40f00030
 183 #define RCSR    0x00
 184
 185 /* Operating System Timer */
 186 OSTIMER_BASE:   .word   0x40a00000
 187 #define OSMR3   0x0C
 188 #define OSCR    0x10
 189 #define OWER    0x18
 190 #define OIER    0x1C
 191
 192 /* Clock Manager Registers                                                  */
 193 #ifdef CFG_CPUSPEED
 194 CC_BASE:        .word   0x41300000
 195 #define CCCR    0x00
 196 cpuspeed:       .word   CFG_CPUSPEED
 197 #else
 198 #error "You have to define CFG_CPUSPEED!!"
 199 #endif
 200
 201         /* takes care the CP15 update has taken place */
 202         .macro CPWAIT reg
 203         mrc  p15,0,\reg,c2,c0,0
 204         mov  \reg,\reg
 205         sub  pc,pc,#4
 206         .endm
 207
 208 cpu_init_crit:
 209
 210         /* mask all IRQs                                                    */
 211 #ifndef CONFIG_CPU_MONAHANS
 212         ldr     r0, IC_BASE
 213         mov     r1, #0x00
 214         str     r1, [r0, #ICMR]
 215 #else
 216         /* Step 1 - Enable CP6 permission */
 217         mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
 218         orr     r1, r1, #0x40
 219                 mcr     p15, 0, r1, c15, c1, 0
 220         CPWAIT  r1
 221
 222         /* Step 2 - Mask ICMR & ICMR2 */
 223         mov     r1, #0
 224         mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 225         mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
 226
 227         /* turn off all clocks but the ones we will definitly require */
 228         ldr     r1, =CKENA
 229         ldr     r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
 230         str     r2, [r1]
 231         ldr     r1, =CKENB
 232         ldr     r2, =(CKENB_6_IRQ)
 233         str     r2, [r1]
 234 #endif
 235
 236 #ifndef CONFIG_CPU_MONAHANS
 237 #ifdef CFG_CPUSPEED
 238         /* set clock speed tbd@mk: required for monahans? */
 239         ldr     r0, CC_BASE
 240         ldr     r1, cpuspeed
 241         str     r1, [r0, #CCCR]
 242         mov     r0, #2
 243         mcr     p14, 0, r0, c6, c0, 0
 244
 245 setspeed_done:
 246
 247 #endif /* CFG_CPUSPEED */
 248 #endif /* CONFIG_CPU_MONAHANS */
 249
 250         /*
 251          * before relocating, we have to setup RAM timing
 252          * because memory timing is board-dependend, you will
 253          * find a lowlevel_init.S in your board directory.
 254          */
 255         mov     ip,     lr
 256         bl      lowlevel_init
 257         mov     lr,     ip
 258
 259         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 260         /* mk: hmm, this is not in the monahans docs, leave it now but
 261          *     check here if it doesn't work :-) */
 262
 263         ldr     r0, =0x2001             /* enable access to all coproc.     */
 264         mcr     p15, 0, r0, c15, c1, 0
 265         CPWAIT r0
 266
 267         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 268         CPWAIT r0
 269
 270         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 271         CPWAIT r0
 272
 273         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 274         CPWAIT r0
 275
 276         /* Enable the Icache                                                */
 277 /*
 278         mrc     p15, 0, r0, c1, c0, 0
 279         orr     r0, r0, #0x1800
 280         mcr     p15, 0, r0, c1, c0, 0
 281         CPWAIT
 282 */
 283         mov     pc, lr
 284
 285
 286 /****************************************************************************/
 287 /*                                                                          */
 288 /* Interrupt handling                                                       */
 289 /*                                                                          */
 290 /****************************************************************************/
 291
 292 /* IRQ stack frame                                                          */
 293
 294 #define S_FRAME_SIZE    72
 295
 296 #define S_OLD_R0        68
 297 #define S_PSR           64
 298 #define S_PC            60
 299 #define S_LR            56
 300 #define S_SP            52
 301
 302 #define S_IP            48
 303 #define S_FP            44
 304 #define S_R10           40
 305 #define S_R9            36
 306 #define S_R8            32
 307 #define S_R7            28
 308 #define S_R6            24
 309 #define S_R5            20
 310 #define S_R4            16
 311 #define S_R3            12
 312 #define S_R2            8
 313 #define S_R1            4
 314 #define S_R0            0
 315
 316 #define MODE_SVC 0x13
 317
 318         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 319
 320         .macro  bad_save_user_regs
 321         sub     sp, sp, #S_FRAME_SIZE
 322         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 323         add     r8, sp, #S_PC
 324
 325         ldr     r2, _armboot_start
 326         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 327         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 328         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 329         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 330
 331         add     r5, sp, #S_SP
 332         mov     r1, lr
 333         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 334         mov     r0, sp
 335         .endm
 336
 337
 338         /* use irq_save_user_regs / irq_restore_user_regs for                */
 339         /* IRQ/FIQ handling                                                  */
 340
 341         .macro  irq_save_user_regs
 342         sub     sp, sp, #S_FRAME_SIZE
 343         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 344         add     r8, sp, #S_PC
 345         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 346         str     lr, [r8, #0]                    /* Save calling PC           */
 347         mrs     r6, spsr
 348         str     r6, [r8, #4]                    /* Save CPSR                 */
 349         str     r0, [r8, #8]                    /* Save OLD_R0               */
 350         mov     r0, sp
 351         .endm
 352
 353         .macro  irq_restore_user_regs
 354         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 355         mov     r0, r0
 356         ldr     lr, [sp, #S_PC]                 @ Get PC
 357         add     sp, sp, #S_FRAME_SIZE
 358         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 359         .endm
 360
 361         .macro get_bad_stack
 362         ldr     r13, _armboot_start             @ setup our mode stack
 363         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 364         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 365
 366         str     lr, [r13]                       @ save caller lr / spsr
 367         mrs     lr, spsr
 368         str     lr, [r13, #4]
 369
 370         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 371         msr     spsr_c, r13
 372         mov     lr, pc
 373         movs    pc, lr
 374         .endm
 375
 376         .macro get_irq_stack                    @ setup IRQ stack
 377         ldr     sp, IRQ_STACK_START
 378         .endm
 379
 380         .macro get_fiq_stack                    @ setup FIQ stack
 381         ldr     sp, FIQ_STACK_START
 382         .endm
 383
 384
 385 /****************************************************************************/
 386 /*                                                                          */
 387 /* exception handlers                                                       */
 388 /*                                                                          */
 389 /****************************************************************************/
 390
 391         .align  5
 392 undefined_instruction:
 393         get_bad_stack
 394         bad_save_user_regs
 395         bl      do_undefined_instruction
 396
 397         .align  5
 398 software_interrupt:
 399         get_bad_stack
 400         bad_save_user_regs
 401         bl      do_software_interrupt
 402
 403         .align  5
 404 prefetch_abort:
 405         get_bad_stack
 406         bad_save_user_regs
 407         bl      do_prefetch_abort
 408
 409         .align  5
 410 data_abort:
 411         get_bad_stack
 412         bad_save_user_regs
 413         bl      do_data_abort
 414
 415         .align  5
 416 not_used:
 417         get_bad_stack
 418         bad_save_user_regs
 419         bl      do_not_used
 420
 421 #ifdef CONFIG_USE_IRQ
 422
 423         .align  5
 424 irq:
 425         get_irq_stack
 426         irq_save_user_regs
 427         bl      do_irq
 428         irq_restore_user_regs
 429
 430         .align  5
 431 fiq:
 432         get_fiq_stack
 433         irq_save_user_regs              /* someone ought to write a more    */
 434         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 435         irq_restore_user_regs
 436
 437 #else
 438
 439         .align  5
 440 irq:
 441         get_bad_stack
 442         bad_save_user_regs
 443         bl      do_irq
 444
 445         .align  5
 446 fiq:
 447         get_bad_stack
 448         bad_save_user_regs
 449         bl      do_fiq
 450
 451 #endif
 452
 453 /****************************************************************************/
 454 /*                                                                          */
 455 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 456 /* perform a watchdog timeout for a soft reset.                             */
 457 /*                                                                          */
 458 /****************************************************************************/
 459
 460         .align  5
 461 .globl reset_cpu
 462
 463         /* FIXME: this code is PXA250 specific. How is this handled on      */
 464         /*        other XScale processors?                                  */
 465
 466 reset_cpu:
 467
 468         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 469
 470         ldr     r0, OSTIMER_BASE
 471         ldr     r1, [r0, #OWER]
 472         orr     r1, r1, #0x0001                 /* bit0: WME                */
 473         str     r1, [r0, #OWER]
 474
 475         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 476         /* the match register as well.                                      */
 477
 478         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 479         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 480         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 481         str     r1, [r0, #OSMR3]
 482
 483 reset_endless:
 484
 485         b       reset_endless