cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from RAM!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 _TEXT_BASE:
  65         .word   TEXT_BASE
  66
  67 .globl _armboot_start
  68 _armboot_start:
  69         .word _start
  70
  71 /*
  72  * These are defined in the board-specific linker script.
  73  */
  74 .globl _bss_start
  75 _bss_start:
  76         .word __bss_start
  77
  78 .globl _bss_end
  79 _bss_end:
  80         .word _end
  81
  82 #ifdef CONFIG_USE_IRQ
  83 /* IRQ stack memory (calculated at run-time) */
  84 .globl IRQ_STACK_START
  85 IRQ_STACK_START:
  86         .word   0x0badc0de
  87
  88 /* IRQ stack memory (calculated at run-time) */
  89 .globl FIQ_STACK_START
  90 FIQ_STACK_START:
  91         .word 0x0badc0de
  92 #endif
  93
  94
  95 /****************************************************************************/
  96 /*                                                                          */
  97 /* the actual reset code                                                    */
  98 /*                                                                          */
  99 /****************************************************************************/
 100
 101 reset:
 102         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 103         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 104         orr     r0,r0,#0x13
 105         msr     cpsr,r0
 106
 107         /*
 108          * we do sys-critical inits only at reboot,
 109          * not when booting from ram!
 110          */
 111 #ifdef CONFIG_INIT_CRITICAL
 112         bl      cpu_init_crit           /* we do sys-critical inits         */
 113 #endif
 114
 115 relocate:                               /* relocate U-Boot to RAM           */
 116         adr     r0, _start              /* r0 <- current position of code   */
 117         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 118         cmp     r0, r1                  /* don't reloc during debug         */
 119         beq     stack_setup
 120
 121         ldr     r2, _armboot_start
 122         ldr     r3, _bss_start
 123         sub     r2, r3, r2              /* r2 <- size of armboot            */
 124         add     r2, r0, r2              /* r2 <- source end address         */
 125
 126 copy_loop:
 127         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 128         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 129         cmp     r0, r2                  /* until source end addreee [r2]    */
 130         ble     copy_loop
 131
 132         /* Set up the stack                                                 */
 133 stack_setup:
 134         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 135         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 136         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 137 #ifdef CONFIG_USE_IRQ
 138         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 139 #endif
 140         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 141
 142 clear_bss:
 143         ldr     r0, _bss_start          /* find start of bss segment        */
 144         ldr     r1, _bss_end            /* stop here                        */
 145         mov     r2, #0x00000000         /* clear                            */
 146
 147 clbss_l:str     r2, [r0]                /* clear loop...                    */
 148         add     r0, r0, #4
 149         cmp     r0, r1
 150         bne     clbss_l
 151
 152         ldr     pc, _start_armboot
 153
 154 _start_armboot: .word start_armboot
 155
 156
 157 /****************************************************************************/
 158 /*                                                                          */
 159 /* CPU_init_critical registers                                              */
 160 /*                                                                          */
 161 /* - setup important registers                                              */
 162 /* - setup memory timing                                                    */
 163 /*                                                                          */
 164 /****************************************************************************/
 165
 166 /* Interrupt-Controller base address                                        */
 167 IC_BASE:           .word           0x40d00000
 168 #define ICMR    0x04
 169
 170 /* Reset-Controller */
 171 RST_BASE:       .word   0x40f00030
 172 #define RCSR    0x00
 173
 174 /* Operating System Timer */
 175 OSTIMER_BASE:   .word   0x40a00000
 176 #define OSMR3   0x0C
 177 #define OSCR    0x10
 178 #define OWER    0x18
 179 #define OIER    0x1C
 180
 181 /* Clock Manager Registers                                                  */
 182 #ifdef CFG_CPUSPEED
 183 CC_BASE:        .word   0x41300000
 184 #define CCCR    0x00
 185 cpuspeed:       .word   CFG_CPUSPEED
 186 #else
 187 #error "You have to define CFG_CPUSPEED!!"
 188 #endif
 189
 190
 191         /* RS: ???                                                          */
 192         .macro CPWAIT
 193         mrc  p15,0,r0,c2,c0,0
 194         mov  r0,r0
 195         sub  pc,pc,#4
 196         .endm
 197
 198
 199 cpu_init_crit:
 200
 201         /* mask all IRQs                                                    */
 202         ldr     r0, IC_BASE
 203         mov     r1, #0x00
 204         str     r1, [r0, #ICMR]
 205
 206 #if defined(CFG_CPUSPEED)
 207
 208         /* set clock speed */
 209         ldr     r0, CC_BASE
 210         ldr     r1, cpuspeed
 211         str     r1, [r0, #CCCR]
 212         mov     r0, #2
 213         mcr     p14, 0, r0, c6, c0, 0
 214
 215 setspeed_done:
 216 #endif
 217
 218         /*
 219          * before relocating, we have to setup RAM timing
 220          * because memory timing is board-dependend, you will
 221          * find a memsetup.S in your board directory.
 222          */
 223         mov     ip,     lr
 224         bl      memsetup
 225         mov     lr,     ip
 226
 227         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 228
 229         ldr     r0, =0x2001             /* enable access to all coproc.     */
 230         mcr     p15, 0, r0, c15, c1, 0
 231         CPWAIT
 232
 233         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 234         CPWAIT
 235
 236         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 237         CPWAIT
 238
 239         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 240         CPWAIT
 241
 242         /* Enable the Icache                                                */
 243 /*
 244         mrc     p15, 0, r0, c1, c0, 0
 245         orr     r0, r0, #0x1800
 246         mcr     p15, 0, r0, c1, c0, 0
 247         CPWAIT
 248 */
 249         mov     pc, lr
 250
 251
 252 /****************************************************************************/
 253 /*                                                                          */
 254 /* Interrupt handling                                                       */
 255 /*                                                                          */
 256 /****************************************************************************/
 257
 258 /* IRQ stack frame                                                          */
 259
 260 #define S_FRAME_SIZE    72
 261
 262 #define S_OLD_R0        68
 263 #define S_PSR           64
 264 #define S_PC            60
 265 #define S_LR            56
 266 #define S_SP            52
 267
 268 #define S_IP            48
 269 #define S_FP            44
 270 #define S_R10           40
 271 #define S_R9            36
 272 #define S_R8            32
 273 #define S_R7            28
 274 #define S_R6            24
 275 #define S_R5            20
 276 #define S_R4            16
 277 #define S_R3            12
 278 #define S_R2            8
 279 #define S_R1            4
 280 #define S_R0            0
 281
 282 #define MODE_SVC 0x13
 283
 284         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 285
 286         .macro  bad_save_user_regs
 287         sub     sp, sp, #S_FRAME_SIZE
 288         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 289         add     r8, sp, #S_PC
 290
 291         ldr     r2, _armboot_start
 292         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 293         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 294         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 295         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 296
 297         add     r5, sp, #S_SP
 298         mov     r1, lr
 299         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 300         mov     r0, sp
 301         .endm
 302
 303
 304         /* use irq_save_user_regs / irq_restore_user_regs for                */
 305         /* IRQ/FIQ handling                                                  */
 306
 307         .macro  irq_save_user_regs
 308         sub     sp, sp, #S_FRAME_SIZE
 309         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 310         add     r8, sp, #S_PC
 311         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 312         str     lr, [r8, #0]                    /* Save calling PC           */
 313         mrs     r6, spsr
 314         str     r6, [r8, #4]                    /* Save CPSR                 */
 315         str     r0, [r8, #8]                    /* Save OLD_R0               */
 316         mov     r0, sp
 317         .endm
 318
 319         .macro  irq_restore_user_regs
 320         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 321         mov     r0, r0
 322         ldr     lr, [sp, #S_PC]                 @ Get PC
 323         add     sp, sp, #S_FRAME_SIZE
 324         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 325         .endm
 326
 327         .macro get_bad_stack
 328         ldr     r13, _armboot_start             @ setup our mode stack
 329         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 330         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 331
 332         str     lr, [r13]                       @ save caller lr / spsr
 333         mrs     lr, spsr
 334         str     lr, [r13, #4]
 335
 336         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 337         msr     spsr_c, r13
 338         mov     lr, pc
 339         movs    pc, lr
 340         .endm
 341
 342         .macro get_irq_stack                    @ setup IRQ stack
 343         ldr     sp, IRQ_STACK_START
 344         .endm
 345
 346         .macro get_fiq_stack                    @ setup FIQ stack
 347         ldr     sp, FIQ_STACK_START
 348         .endm
 349
 350
 351 /****************************************************************************/
 352 /*                                                                          */
 353 /* exception handlers                                                       */
 354 /*                                                                          */
 355 /****************************************************************************/
 356
 357         .align  5
 358 undefined_instruction:
 359         get_bad_stack
 360         bad_save_user_regs
 361         bl      do_undefined_instruction
 362
 363         .align  5
 364 software_interrupt:
 365         get_bad_stack
 366         bad_save_user_regs
 367         bl      do_software_interrupt
 368
 369         .align  5
 370 prefetch_abort:
 371         get_bad_stack
 372         bad_save_user_regs
 373         bl      do_prefetch_abort
 374
 375         .align  5
 376 data_abort:
 377         get_bad_stack
 378         bad_save_user_regs
 379         bl      do_data_abort
 380
 381         .align  5
 382 not_used:
 383         get_bad_stack
 384         bad_save_user_regs
 385         bl      do_not_used
 386
 387 #ifdef CONFIG_USE_IRQ
 388
 389         .align  5
 390 irq:
 391         get_irq_stack
 392         irq_save_user_regs
 393         bl      do_irq
 394         irq_restore_user_regs
 395
 396         .align  5
 397 fiq:
 398         get_fiq_stack
 399         irq_save_user_regs              /* someone ought to write a more    */
 400         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 401         irq_restore_user_regs
 402
 403 #else
 404
 405         .align  5
 406 irq:
 407         get_bad_stack
 408         bad_save_user_regs
 409         bl      do_irq
 410
 411         .align  5
 412 fiq:
 413         get_bad_stack
 414         bad_save_user_regs
 415         bl      do_fiq
 416
 417 #endif
 418
 419 /****************************************************************************/
 420 /*                                                                          */
 421 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 422 /* perform a watchdog timeout for a soft reset.                             */
 423 /*                                                                          */
 424 /****************************************************************************/
 425
 426         .align  5
 427 .globl reset_cpu
 428
 429         /* FIXME: this code is PXA250 specific. How is this handled on      */
 430         /*        other XScale processors?                                  */
 431
 432 reset_cpu:
 433
 434         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 435
 436         ldr     r0, OSTIMER_BASE
 437         ldr     r1, [r0, #OWER]
 438         orr     r1, r1, #0x0001                 /* bit0: WME                */
 439         str     r1, [r0, #OWER]
 440
 441         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 442         /* the match register as well.                                      */
 443
 444         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 445         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 446         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 447         str     r1, [r0, #OSMR3]
 448
 449 reset_endless:
 450
 451         b       reset_endless