2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/pxa-regs.h>
37 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
45 _undefined_instruction: .word undefined_instruction
46 _software_interrupt: .word software_interrupt
47 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
49 _not_used: .word not_used
53 .balignl 16,0xdeadbeef
57 * Startup Code (reset vector)
59 * do important init only if we don't start from RAM!
60 * - relocate armboot to ram
62 * - jump to second stage
73 * These are defined in the board-specific linker script.
84 /* IRQ stack memory (calculated at run-time) */
85 .globl IRQ_STACK_START
89 /* IRQ stack memory (calculated at run-time) */
90 .globl FIQ_STACK_START
96 /****************************************************************************/
98 /* the actual reset code */
100 /****************************************************************************/
103 mrs r0,cpsr /* set the cpu to SVC32 mode */
104 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
109 * we do sys-critical inits only at reboot,
110 * not when booting from ram!
112 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
113 bl cpu_init_crit /* we do sys-critical inits */
116 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
117 relocate: /* relocate U-Boot to RAM */
118 adr r0, _start /* r0 <- current position of code */
119 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
120 cmp r0, r1 /* don't reloc during debug */
123 ldr r2, _armboot_start
125 sub r2, r3, r2 /* r2 <- size of armboot */
126 add r2, r0, r2 /* r2 <- source end address */
129 ldmia r0!, {r3-r10} /* copy from source address [r0] */
130 stmia r1!, {r3-r10} /* copy to target address [r1] */
131 cmp r0, r2 /* until source end addreee [r2] */
133 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
135 /* Set up the stack */
137 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
138 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
139 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
140 #ifdef CONFIG_USE_IRQ
141 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
143 sub sp, r0, #12 /* leave 3 words for abort-stack */
146 ldr r0, _bss_start /* find start of bss segment */
147 ldr r1, _bss_end /* stop here */
148 mov r2, #0x00000000 /* clear */
150 clbss_l:str r2, [r0] /* clear loop... */
155 ldr pc, _start_armboot
157 _start_armboot: .word start_armboot
160 /****************************************************************************/
162 /* CPU_init_critical registers */
164 /* - setup important registers */
165 /* - setup memory timing */
167 /****************************************************************************/
168 /* mk@tbd: Fix this! */
169 #ifdef CONFIG_CPU_MONAHANS
177 /* Interrupt-Controller base address */
178 IC_BASE: .word 0x40d00000
181 /* Reset-Controller */
182 RST_BASE: .word 0x40f00030
185 /* Operating System Timer */
186 OSTIMER_BASE: .word 0x40a00000
192 /* Clock Manager Registers */
194 CC_BASE: .word 0x41300000
196 cpuspeed: .word CFG_CPUSPEED
198 #error "You have to define CFG_CPUSPEED!!"
202 /* takes care the CP15 update has taken place */
204 mrc p15,0,\reg,c2,c0,0
213 #ifndef CONFIG_CPU_MONAHANS
219 /* Step 1 - Enable CP6 permission */
220 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
222 mcr p15, 0, r1, c15, c1, 0
225 /* Step 2 - Mask ICMR & ICMR2 */
227 mcr p6, 0, r1, c1, c0, 0 @ ICMR
228 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
230 /* turn off all clocks but the ones we will definitly require */
232 ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
235 ldr r2, =(CKENB_6_IRQ)
240 #ifndef CONFIG_CPU_MONAHANS
243 /* set clock speed tbd@mk: required for monahans? */
248 mcr p14, 0, r0, c6, c0, 0
252 #endif /* CFG_CPUSPEED */
253 #endif /* CONFIG_CPU_MONAHANS */
257 * before relocating, we have to setup RAM timing
258 * because memory timing is board-dependend, you will
259 * find a lowlevel_init.S in your board directory.
265 /* Memory interfaces are working. Disable MMU and enable I-cache. */
266 /* mk: hmm, this is not in the monahans docs, leave it now but
267 * check here if it doesn't work :-) */
269 ldr r0, =0x2001 /* enable access to all coproc. */
270 mcr p15, 0, r0, c15, c1, 0
273 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
276 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
279 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
282 /* Enable the Icache */
284 mrc p15, 0, r0, c1, c0, 0
286 mcr p15, 0, r0, c1, c0, 0
292 /****************************************************************************/
294 /* Interrupt handling */
296 /****************************************************************************/
298 /* IRQ stack frame */
300 #define S_FRAME_SIZE 72
322 #define MODE_SVC 0x13
324 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
326 .macro bad_save_user_regs
327 sub sp, sp, #S_FRAME_SIZE
328 stmia sp, {r0 - r12} /* Calling r0-r12 */
331 ldr r2, _armboot_start
332 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
333 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
334 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
335 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
339 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
344 /* use irq_save_user_regs / irq_restore_user_regs for */
345 /* IRQ/FIQ handling */
347 .macro irq_save_user_regs
348 sub sp, sp, #S_FRAME_SIZE
349 stmia sp, {r0 - r12} /* Calling r0-r12 */
351 stmdb r8, {sp, lr}^ /* Calling SP, LR */
352 str lr, [r8, #0] /* Save calling PC */
354 str r6, [r8, #4] /* Save CPSR */
355 str r0, [r8, #8] /* Save OLD_R0 */
359 .macro irq_restore_user_regs
360 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
362 ldr lr, [sp, #S_PC] @ Get PC
363 add sp, sp, #S_FRAME_SIZE
364 subs pc, lr, #4 @ return & move spsr_svc into cpsr
368 ldr r13, _armboot_start @ setup our mode stack
369 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
370 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
372 str lr, [r13] @ save caller lr / spsr
376 mov r13, #MODE_SVC @ prepare SVC-Mode
382 .macro get_irq_stack @ setup IRQ stack
383 ldr sp, IRQ_STACK_START
386 .macro get_fiq_stack @ setup FIQ stack
387 ldr sp, FIQ_STACK_START
391 /****************************************************************************/
393 /* exception handlers */
395 /****************************************************************************/
398 undefined_instruction:
401 bl do_undefined_instruction
407 bl do_software_interrupt
427 #ifdef CONFIG_USE_IRQ
434 irq_restore_user_regs
439 irq_save_user_regs /* someone ought to write a more */
440 bl do_fiq /* effiction fiq_save_user_regs */
441 irq_restore_user_regs
459 /****************************************************************************/
461 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
462 /* perform a watchdog timeout for a soft reset. */
464 /****************************************************************************/
469 /* FIXME: this code is PXA250 specific. How is this handled on */
470 /* other XScale processors? */
474 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
478 orr r1, r1, #0x0001 /* bit0: WME */
481 /* OS timer does only wrap every 1165 seconds, so we have to set */
482 /* the match register as well. */
484 ldr r1, [r0, #OSCR] /* read OS timer */
485 add r1, r1, #0x800 /* let OSMR3 match after */
486 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */