3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
13 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #include <asm/arch/pxa-regs.h>
35 void serial_setbrg (void)
37 DECLARE_GLOBAL_DATA_PTR;
39 unsigned int quot = 0;
41 if (gd->baudrate == 1200)
43 else if (gd->baudrate == 9600)
45 else if (gd->baudrate == 19200)
47 else if (gd->baudrate == 38400)
49 else if (gd->baudrate == 57600)
51 else if (gd->baudrate == 115200)
57 #ifdef CONFIG_CPU_MONAHANS
58 CKENA |= CKENA_22_FFUART;
61 #endif /* CONFIG_CPU_MONAHANS */
63 FFIER = 0; /* Disable for now */
64 FFFCR = 0; /* No fifos enabled */
67 FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
70 FFLCR = LCR_WLS0 | LCR_WLS1;
72 FFIER = IER_UUE; /* Enable FFUART */
74 #elif defined(CONFIG_BTUART)
75 #ifdef CONFIG_CPU_MONAHANS
76 CKENA |= CKENA_21_BTUART;
79 #endif /* CONFIG_CPU_MONAHANS */
88 BTLCR = LCR_WLS0 | LCR_WLS1;
90 BTIER = IER_UUE; /* Enable BFUART */
92 #elif defined(CONFIG_STUART)
93 #ifdef CONFIG_CPU_MONAHANS
94 CKENA |= CKENA_23_STUART;
97 #endif /* CONFIG_CPU_MONAHANS */
106 STLCR = LCR_WLS0 | LCR_WLS1;
108 STIER = IER_UUE; /* Enable STUART */
111 #error "Bad: you didn't configure serial ..."
117 * Initialise the serial port with the given baudrate. The settings
118 * are always 8 data bits, no parity, 1 stop bit, no start bits.
121 int serial_init (void)
130 * Output a single byte to the serial port.
132 void serial_putc (const char c)
135 /* wait for room in the tx FIFO on FFUART */
136 while ((FFLSR & LSR_TEMT) == 0)
137 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
139 #elif defined(CONFIG_BTUART)
140 while ((BTLSR & LSR_TEMT ) == 0 )
141 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
143 #elif defined(CONFIG_STUART)
144 while ((STLSR & LSR_TEMT ) == 0 )
145 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
149 /* If \n, also do \r */
155 * Read a single byte from the serial port. Returns 1 on success, 0
156 * otherwise. When the function is succesfull, the character read is
157 * written into its argument c.
159 int serial_tstc (void)
162 return FFLSR & LSR_DR;
163 #elif defined(CONFIG_BTUART)
164 return BTLSR & LSR_DR;
165 #elif defined(CONFIG_STUART)
166 return STLSR & LSR_DR;
171 * Read a single byte from the serial port. Returns 1 on success, 0
172 * otherwise. When the function is succesfull, the character read is
173 * written into its argument c.
175 int serial_getc (void)
178 while (!(FFLSR & LSR_DR))
179 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
180 return (char) FFRBR & 0xff;
181 #elif defined(CONFIG_BTUART)
182 while (!(BTLSR & LSR_DR))
183 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
184 return (char) BTRBR & 0xff;
185 #elif defined(CONFIG_STUART)
186 while (!(STLSR & LSR_DR))
187 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
188 return (char) STRBR & 0xff;
193 serial_puts (const char *s)