cpu/ppc4xx/tlb.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #if defined(CONFIG_440)
  27
  28 #include <ppc440.h>
  29 #include <asm/io.h>
  30 #include <asm/mmu.h>
  31
  32 typedef struct region {
  33         unsigned long base;
  34         unsigned long size;
  35         unsigned long tlb_word2_i_value;
  36 } region_t;
  37
  38 void remove_tlb(u32 vaddr, u32 size)
  39 {
  40         int i;
  41         u32 tlb_word0_value;
  42         u32 tlb_vaddr;
  43         u32 tlb_size = 0;
  44
  45         /* First, find the index of a TLB entry not being used */
  46         for (i=0; i<PPC4XX_TLB_SIZE; i++) {
  47                 tlb_word0_value = mftlb1(i);
  48                 tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
  49                 if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
  50                     (tlb_vaddr >= vaddr)) {
  51                         /*
  52                          * TLB is enabled and start address is lower or equal
  53                          * than the area we are looking for. Now we only have
  54                          * to check the size/end address for a match.
  55                          */
  56                         switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
  57                         case TLB_WORD0_SIZE_1KB:
  58                                 tlb_size = 1 << 10;
  59                                 break;
  60                         case TLB_WORD0_SIZE_4KB:
  61                                 tlb_size = 4 << 10;
  62                                 break;
  63                         case TLB_WORD0_SIZE_16KB:
  64                                 tlb_size = 16 << 10;
  65                                 break;
  66                         case TLB_WORD0_SIZE_64KB:
  67                                 tlb_size = 64 << 10;
  68                                 break;
  69                         case TLB_WORD0_SIZE_256KB:
  70                                 tlb_size = 256 << 10;
  71                                 break;
  72                         case TLB_WORD0_SIZE_1MB:
  73                                 tlb_size = 1 << 20;
  74                                 break;
  75                         case TLB_WORD0_SIZE_16MB:
  76                                 tlb_size = 16 << 20;
  77                                 break;
  78                         case TLB_WORD0_SIZE_256MB:
  79                                 tlb_size = 256 << 20;
  80                                 break;
  81                         }
  82
  83                         /*
  84                          * Now check the end-address if it's in the range
  85                          */
  86                         if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
  87                                 /*
  88                                  * Found a TLB in the range.
  89                                  * Disable it by writing 0 to tlb0 word.
  90                                  */
  91                                 mttlb1(i, 0);
  92                 }
  93         }
  94
  95         /* Execute an ISYNC instruction so that the new TLB entry takes effect */
  96         asm("isync");
  97 }
  98
  99 static int add_tlb_entry(unsigned long phys_addr,
 100                          unsigned long virt_addr,
 101                          unsigned long tlb_word0_size_value,
 102                          unsigned long tlb_word2_i_value)
 103 {
 104         int i;
 105         unsigned long tlb_word0_value;
 106         unsigned long tlb_word1_value;
 107         unsigned long tlb_word2_value;
 108
 109         /* First, find the index of a TLB entry not being used */
 110         for (i=0; i<PPC4XX_TLB_SIZE; i++) {
 111                 tlb_word0_value = mftlb1(i);
 112                 if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
 113                         break;
 114         }
 115         if (i >= PPC4XX_TLB_SIZE)
 116                 return -1;
 117
 118         /* Second, create the TLB entry */
 119         tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
 120                 TLB_WORD0_TS_0 | tlb_word0_size_value;
 121         tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
 122         tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 123                 TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 124                 TLB_WORD2_W_DISABLE | tlb_word2_i_value |
 125                 TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
 126                 TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
 127                 TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
 128                 TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
 129                 TLB_WORD2_SR_ENABLE;
 130
 131         /* Wait for all memory accesses to complete */
 132         sync();
 133
 134         /* Third, add the TLB entries */
 135         mttlb1(i, tlb_word0_value);
 136         mttlb2(i, tlb_word1_value);
 137         mttlb3(i, tlb_word2_value);
 138
 139         /* Execute an ISYNC instruction so that the new TLB entry takes effect */
 140         asm("isync");
 141
 142         return 0;
 143 }
 144
 145 static void program_tlb_addr(unsigned long phys_addr,
 146                              unsigned long virt_addr,
 147                              unsigned long mem_size,
 148                              unsigned long tlb_word2_i_value)
 149 {
 150         int rc;
 151         int tlb_i;
 152
 153         tlb_i = tlb_word2_i_value;
 154         while (mem_size != 0) {
 155                 rc = 0;
 156                 /* Add the TLB entries in to map the region. */
 157                 if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
 158                     (mem_size >= TLB_256MB_SIZE)) {
 159                         /* Add a 256MB TLB entry */
 160                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 161                                                 TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
 162                                 mem_size -= TLB_256MB_SIZE;
 163                                 phys_addr += TLB_256MB_SIZE;
 164                                 virt_addr += TLB_256MB_SIZE;
 165                         }
 166                 } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
 167                            (mem_size >= TLB_16MB_SIZE)) {
 168                         /* Add a 16MB TLB entry */
 169                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 170                                                 TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
 171                                 mem_size -= TLB_16MB_SIZE;
 172                                 phys_addr += TLB_16MB_SIZE;
 173                                 virt_addr += TLB_16MB_SIZE;
 174                         }
 175                 } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
 176                            (mem_size >= TLB_1MB_SIZE)) {
 177                         /* Add a 1MB TLB entry */
 178                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 179                                                 TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
 180                                 mem_size -= TLB_1MB_SIZE;
 181                                 phys_addr += TLB_1MB_SIZE;
 182                                 virt_addr += TLB_1MB_SIZE;
 183                         }
 184                 } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
 185                            (mem_size >= TLB_256KB_SIZE)) {
 186                         /* Add a 256KB TLB entry */
 187                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 188                                                 TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
 189                                 mem_size -= TLB_256KB_SIZE;
 190                                 phys_addr += TLB_256KB_SIZE;
 191                                 virt_addr += TLB_256KB_SIZE;
 192                         }
 193                 } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
 194                            (mem_size >= TLB_64KB_SIZE)) {
 195                         /* Add a 64KB TLB entry */
 196                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 197                                                 TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
 198                                 mem_size -= TLB_64KB_SIZE;
 199                                 phys_addr += TLB_64KB_SIZE;
 200                                 virt_addr += TLB_64KB_SIZE;
 201                         }
 202                 } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
 203                            (mem_size >= TLB_16KB_SIZE)) {
 204                         /* Add a 16KB TLB entry */
 205                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 206                                                 TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
 207                                 mem_size -= TLB_16KB_SIZE;
 208                                 phys_addr += TLB_16KB_SIZE;
 209                                 virt_addr += TLB_16KB_SIZE;
 210                         }
 211                 } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
 212                            (mem_size >= TLB_4KB_SIZE)) {
 213                         /* Add a 4KB TLB entry */
 214                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 215                                                 TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
 216                                 mem_size -= TLB_4KB_SIZE;
 217                                 phys_addr += TLB_4KB_SIZE;
 218                                 virt_addr += TLB_4KB_SIZE;
 219                         }
 220                 } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
 221                            (mem_size >= TLB_1KB_SIZE)) {
 222                         /* Add a 1KB TLB entry */
 223                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 224                                                 TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
 225                                 mem_size -= TLB_1KB_SIZE;
 226                                 phys_addr += TLB_1KB_SIZE;
 227                                 virt_addr += TLB_1KB_SIZE;
 228                         }
 229                 } else {
 230                         printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
 231                                 phys_addr);
 232                 }
 233
 234                 if (rc != 0)
 235                         printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
 236                                 phys_addr);
 237         }
 238
 239         return;
 240 }
 241
 242 /*
 243  * Program one (or multiple) TLB entries for one memory region
 244  *
 245  * Common usage for boards with SDRAM DIMM modules to dynamically
 246  * configure the TLB's for the SDRAM
 247  */
 248 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 249 {
 250         region_t region_array;
 251
 252         region_array.base = phys_addr;
 253         region_array.size = size;
 254         region_array.tlb_word2_i_value = tlb_word2_i_value;     /* en-/disable cache */
 255
 256         /* Call the routine to add in the tlb entries for the memory regions */
 257         program_tlb_addr(region_array.base, virt_addr, region_array.size,
 258                          region_array.tlb_word2_i_value);
 259
 260         return;
 261 }
 262
 263 #endif /* CONFIG_440 */