cpu/ppc4xx/tlb.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #if defined(CONFIG_440)
  27
  28 #include <ppc4xx.h>
  29 #include <ppc440.h>
  30 #include <asm/io.h>
  31 #include <asm/mmu.h>
  32
  33 typedef struct region {
  34         unsigned long base;
  35         unsigned long size;
  36         unsigned long tlb_word2_i_value;
  37 } region_t;
  38
  39 static int add_tlb_entry(unsigned long phys_addr,
  40                          unsigned long virt_addr,
  41                          unsigned long tlb_word0_size_value,
  42                          unsigned long tlb_word2_i_value)
  43 {
  44         int i;
  45         unsigned long tlb_word0_value;
  46         unsigned long tlb_word1_value;
  47         unsigned long tlb_word2_value;
  48
  49         /* First, find the index of a TLB entry not being used */
  50         for (i=0; i<PPC4XX_TLB_SIZE; i++) {
  51                 tlb_word0_value = mftlb1(i);
  52                 if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
  53                         break;
  54         }
  55         if (i >= PPC4XX_TLB_SIZE)
  56                 return -1;
  57
  58         /* Second, create the TLB entry */
  59         tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
  60                 TLB_WORD0_TS_0 | tlb_word0_size_value;
  61         tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
  62         tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
  63                 TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
  64                 TLB_WORD2_W_DISABLE | tlb_word2_i_value |
  65                 TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
  66                 TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
  67                 TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
  68                 TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
  69                 TLB_WORD2_SR_ENABLE;
  70
  71         /* Wait for all memory accesses to complete */
  72         sync();
  73
  74         /* Third, add the TLB entries */
  75         mttlb1(i, tlb_word0_value);
  76         mttlb2(i, tlb_word1_value);
  77         mttlb3(i, tlb_word2_value);
  78
  79         /* Execute an ISYNC instruction so that the new TLB entry takes effect */
  80         asm("isync");
  81
  82         return 0;
  83 }
  84
  85 static void program_tlb_addr(unsigned long phys_addr,
  86                              unsigned long virt_addr,
  87                              unsigned long mem_size,
  88                              unsigned long tlb_word2_i_value)
  89 {
  90         int rc;
  91         int tlb_i;
  92
  93         tlb_i = tlb_word2_i_value;
  94         while (mem_size != 0) {
  95                 rc = 0;
  96                 /* Add the TLB entries in to map the region. */
  97                 if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
  98                     (mem_size >= TLB_256MB_SIZE)) {
  99                         /* Add a 256MB TLB entry */
 100                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 101                                                 TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
 102                                 mem_size -= TLB_256MB_SIZE;
 103                                 phys_addr += TLB_256MB_SIZE;
 104                                 virt_addr += TLB_256MB_SIZE;
 105                         }
 106                 } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
 107                            (mem_size >= TLB_16MB_SIZE)) {
 108                         /* Add a 16MB TLB entry */
 109                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 110                                                 TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
 111                                 mem_size -= TLB_16MB_SIZE;
 112                                 phys_addr += TLB_16MB_SIZE;
 113                                 virt_addr += TLB_16MB_SIZE;
 114                         }
 115                 } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
 116                            (mem_size >= TLB_1MB_SIZE)) {
 117                         /* Add a 1MB TLB entry */
 118                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 119                                                 TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
 120                                 mem_size -= TLB_1MB_SIZE;
 121                                 phys_addr += TLB_1MB_SIZE;
 122                                 virt_addr += TLB_1MB_SIZE;
 123                         }
 124                 } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
 125                            (mem_size >= TLB_256KB_SIZE)) {
 126                         /* Add a 256KB TLB entry */
 127                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 128                                                 TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
 129                                 mem_size -= TLB_256KB_SIZE;
 130                                 phys_addr += TLB_256KB_SIZE;
 131                                 virt_addr += TLB_256KB_SIZE;
 132                         }
 133                 } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
 134                            (mem_size >= TLB_64KB_SIZE)) {
 135                         /* Add a 64KB TLB entry */
 136                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 137                                                 TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
 138                                 mem_size -= TLB_64KB_SIZE;
 139                                 phys_addr += TLB_64KB_SIZE;
 140                                 virt_addr += TLB_64KB_SIZE;
 141                         }
 142                 } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
 143                            (mem_size >= TLB_16KB_SIZE)) {
 144                         /* Add a 16KB TLB entry */
 145                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 146                                                 TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
 147                                 mem_size -= TLB_16KB_SIZE;
 148                                 phys_addr += TLB_16KB_SIZE;
 149                                 virt_addr += TLB_16KB_SIZE;
 150                         }
 151                 } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
 152                            (mem_size >= TLB_4KB_SIZE)) {
 153                         /* Add a 4KB TLB entry */
 154                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 155                                                 TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
 156                                 mem_size -= TLB_4KB_SIZE;
 157                                 phys_addr += TLB_4KB_SIZE;
 158                                 virt_addr += TLB_4KB_SIZE;
 159                         }
 160                 } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
 161                            (mem_size >= TLB_1KB_SIZE)) {
 162                         /* Add a 1KB TLB entry */
 163                         if ((rc = add_tlb_entry(phys_addr, virt_addr,
 164                                                 TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
 165                                 mem_size -= TLB_1KB_SIZE;
 166                                 phys_addr += TLB_1KB_SIZE;
 167                                 virt_addr += TLB_1KB_SIZE;
 168                         }
 169                 } else {
 170                         printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
 171                                 phys_addr);
 172                 }
 173
 174                 if (rc != 0)
 175                         printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
 176                                 phys_addr);
 177         }
 178
 179         return;
 180 }
 181
 182 /*
 183  * Program one (or multiple) TLB entries for one memory region
 184  *
 185  * Common usage for boards with SDRAM DIMM modules to dynamically
 186  * configure the TLB's for the SDRAM
 187  */
 188 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 189 {
 190         region_t region_array;
 191
 192         region_array.base = phys_addr;
 193         region_array.size = size;
 194         region_array.tlb_word2_i_value = tlb_word2_i_value;     /* en-/disable cache */
 195
 196         /* Call the routine to add in the tlb entries for the memory regions */
 197         program_tlb_addr(region_array.base, virt_addr, region_array.size,
 198                          region_array.tlb_word2_i_value);
 199
 200         return;
 201 }
 202
 203 #endif /* CONFIG_440 */