2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
66 #include <timestamp.h>
69 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
71 #include <ppc_asm.tmpl>
74 #include <asm/cache.h>
76 #include <asm/ppc4xx-isram.h>
78 #ifndef CONFIG_IDENT_STRING
79 #define CONFIG_IDENT_STRING ""
82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
86 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
87 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
88 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
94 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
95 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
96 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
102 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
103 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
104 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
110 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
111 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
112 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
118 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
119 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
120 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
126 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
127 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
128 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
134 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
135 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
136 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
142 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
143 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
144 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
154 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
155 * used as temporary stack pointer for the primordial stack
157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
158 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
159 EBC_BXAP_TWT_ENCODE(7) | \
160 EBC_BXAP_BCE_DISABLE | \
161 EBC_BXAP_BCT_2TRANS | \
162 EBC_BXAP_CSN_ENCODE(0) | \
163 EBC_BXAP_OEN_ENCODE(0) | \
164 EBC_BXAP_WBN_ENCODE(0) | \
165 EBC_BXAP_WBF_ENCODE(0) | \
166 EBC_BXAP_TH_ENCODE(2) | \
167 EBC_BXAP_RE_DISABLED | \
168 EBC_BXAP_SOR_NONDELAYED | \
169 EBC_BXAP_BEM_WRITEONLY | \
170 EBC_BXAP_PEN_DISABLED)
171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
173 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
179 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
188 * Unless otherwise overriden, enable two 128MB cachable instruction regions
189 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
190 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
192 #if !defined(CONFIG_SYS_FLASH_BASE)
193 /* If not already defined, set it to the "last" 128MByte region */
194 # define CONFIG_SYS_FLASH_BASE 0xf8000000
196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
197 # define CONFIG_SYS_ICACHE_SACR_VALUE \
198 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
199 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
200 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
204 # define CONFIG_SYS_DCACHE_SACR_VALUE \
206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
208 #define function_prolog(func_name) .text; \
212 #define function_epilog(func_name) .type func_name,@function; \
213 .size func_name,.-func_name
215 /* We don't want the MMU yet.
218 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
221 .extern ext_bus_cntlr_init
222 #ifdef CONFIG_NAND_U_BOOT
223 .extern reconfig_tlb0
227 * Set up GOT: Global Offset Table
229 * Use r14 to access the GOT
231 #if !defined(CONFIG_NAND_SPL)
233 GOT_ENTRY(_GOT2_TABLE_)
234 GOT_ENTRY(_FIXUP_TABLE_)
237 GOT_ENTRY(_start_of_vectors)
238 GOT_ENTRY(_end_of_vectors)
239 GOT_ENTRY(transfer_to_handler)
241 GOT_ENTRY(__init_end)
243 GOT_ENTRY(__bss_start)
245 #endif /* CONFIG_NAND_SPL */
247 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
249 * NAND U-Boot image is started from offset 0
252 #if defined(CONFIG_440)
256 bl cpu_init_f /* run low-level CPU init code (from Flash) */
260 #if defined(CONFIG_SYS_RAMBOOT)
262 * 4xx RAM-booting U-Boot image is started from offset 0
269 * 440 Startup -- on reset only the top 4k of the effective
270 * address space is mapped in by an entry in the instruction
271 * and data shadow TLB. The .bootpg section is located in the
272 * top 4k & does only what's necessary to map in the the rest
273 * of the boot rom. Once the boot rom is mapped in we can
274 * proceed with normal startup.
276 * NOTE: CS0 only covers the top 2MB of the effective address
280 #if defined(CONFIG_440)
281 #if !defined(CONFIG_NAND_SPL)
282 .section .bootpg,"ax"
286 /**************************************************************************/
288 /*--------------------------------------------------------------------+
289 | 440EPX BUP Change - Hardware team request
290 +--------------------------------------------------------------------*/
291 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
296 /*----------------------------------------------------------------+
297 | Core bug fix. Clear the esr
298 +-----------------------------------------------------------------*/
301 /*----------------------------------------------------------------*/
302 /* Clear and set up some registers. */
303 /*----------------------------------------------------------------*/
304 iccci r0,r0 /* NOTE: operands not used for 440 */
305 dccci r0,r0 /* NOTE: operands not used for 440 */
312 /* NOTE: 440GX adds machine check status regs */
313 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
320 /*----------------------------------------------------------------*/
322 /*----------------------------------------------------------------*/
323 /* Disable store gathering & broadcast, guarantee inst/data
324 * cache block touch, force load/store alignment
325 * (see errata 1.12: 440_33)
327 lis r1,0x0030 /* store gathering & broadcast disable */
328 ori r1,r1,0x6000 /* cache touch */
331 /*----------------------------------------------------------------*/
332 /* Initialize debug */
333 /*----------------------------------------------------------------*/
335 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
336 bne skip_debug_init /* if set, don't clear debug register */
349 mtspr dbsr,r1 /* Clear all valid bits */
352 #if defined (CONFIG_440SPE)
353 /*----------------------------------------------------------------+
354 | Initialize Core Configuration Reg1.
355 | a. ICDPEI: Record even parity. Normal operation.
356 | b. ICTPEI: Record even parity. Normal operation.
357 | c. DCTPEI: Record even parity. Normal operation.
358 | d. DCDPEI: Record even parity. Normal operation.
359 | e. DCUPEI: Record even parity. Normal operation.
360 | f. DCMPEI: Record even parity. Normal operation.
361 | g. FCOM: Normal operation
362 | h. MMUPEI: Record even parity. Normal operation.
363 | i. FFF: Flush only as much data as necessary.
364 | j. TCS: Timebase increments from CPU clock.
365 +-----------------------------------------------------------------*/
369 /*----------------------------------------------------------------+
370 | Reset the timebase.
371 | The previous write to CCR1 sets the timebase source.
372 +-----------------------------------------------------------------*/
377 /*----------------------------------------------------------------*/
378 /* Setup interrupt vectors */
379 /*----------------------------------------------------------------*/
380 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
382 mtspr ivor0,r1 /* Critical input */
384 mtspr ivor1,r1 /* Machine check */
386 mtspr ivor2,r1 /* Data storage */
388 mtspr ivor3,r1 /* Instruction storage */
390 mtspr ivor4,r1 /* External interrupt */
392 mtspr ivor5,r1 /* Alignment */
394 mtspr ivor6,r1 /* Program check */
396 mtspr ivor7,r1 /* Floating point unavailable */
398 mtspr ivor8,r1 /* System call */
400 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
402 mtspr ivor10,r1 /* Decrementer */
404 mtspr ivor13,r1 /* Data TLB error */
406 mtspr ivor14,r1 /* Instr TLB error */
408 mtspr ivor15,r1 /* Debug */
410 /*----------------------------------------------------------------*/
411 /* Configure cache regions */
412 /*----------------------------------------------------------------*/
430 /*----------------------------------------------------------------*/
431 /* Cache victim limits */
432 /*----------------------------------------------------------------*/
433 /* floors 0, ceiling max to use the entire cache -- nothing locked
440 /*----------------------------------------------------------------+
441 |Initialize MMUCR[STID] = 0.
442 +-----------------------------------------------------------------*/
449 /*----------------------------------------------------------------*/
450 /* Clear all TLB entries -- TID = 0, TS = 0 */
451 /*----------------------------------------------------------------*/
453 #ifdef CONFIG_SYS_RAMBOOT
454 li r4,0 /* Start with TLB #0 */
456 li r4,1 /* Start with TLB #1 */
458 li r1,64 /* 64 TLB entries */
459 sub r1,r1,r4 /* calculate last TLB # */
462 #ifdef CONFIG_SYS_RAMBOOT
463 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
464 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
465 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
467 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
470 tlbnxt: addi r4,r4,1 /* Next TLB */
473 /*----------------------------------------------------------------*/
474 /* TLB entry setup -- step thru tlbtab */
475 /*----------------------------------------------------------------*/
476 #if defined(CONFIG_440SPE)
477 /*----------------------------------------------------------------*/
478 /* We have different TLB tables for revA and rev B of 440SPe */
479 /*----------------------------------------------------------------*/
491 bl tlbtab /* Get tlbtab pointer */
494 li r1,0x003f /* 64 TLB entries max */
500 #ifdef CONFIG_SYS_RAMBOOT
501 tlbre r3,r4,0 /* Read contents from TLB word #0 */
502 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
503 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
507 beq 2f /* 0 marks end */
510 tlbwe r0,r4,0 /* TLB Word 0 */
511 tlbwe r1,r4,1 /* TLB Word 1 */
512 tlbwe r2,r4,2 /* TLB Word 2 */
513 tlbnx2: addi r4,r4,1 /* Next TLB */
516 /*----------------------------------------------------------------*/
517 /* Continue from 'normal' start */
518 /*----------------------------------------------------------------*/
524 mtspr srr1,r0 /* Keep things disabled for now */
528 #endif /* CONFIG_440 */
531 * r3 - 1st arg to board_init(): IMMP pointer
532 * r4 - 2nd arg to board_init(): boot flag
534 #ifndef CONFIG_NAND_SPL
536 .long 0x27051956 /* U-Boot Magic Number */
537 .globl version_string
539 .ascii U_BOOT_VERSION
540 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
541 .ascii CONFIG_IDENT_STRING, "\0"
543 . = EXC_OFF_SYS_RESET
544 .globl _start_of_vectors
547 /* Critical input. */
548 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
552 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
554 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
555 #endif /* CONFIG_440 */
557 /* Data Storage exception. */
558 STD_EXCEPTION(0x300, DataStorage, UnknownException)
560 /* Instruction Storage exception. */
561 STD_EXCEPTION(0x400, InstStorage, UnknownException)
563 /* External Interrupt exception. */
564 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
566 /* Alignment exception. */
569 EXCEPTION_PROLOG(SRR0, SRR1)
574 addi r3,r1,STACK_FRAME_OVERHEAD
576 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
577 lwz r6,GOT(transfer_to_handler)
581 .long AlignmentException - _start + _START_OFFSET
582 .long int_return - _start + _START_OFFSET
584 /* Program check exception */
587 EXCEPTION_PROLOG(SRR0, SRR1)
588 addi r3,r1,STACK_FRAME_OVERHEAD
590 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
591 lwz r6,GOT(transfer_to_handler)
595 .long ProgramCheckException - _start + _START_OFFSET
596 .long int_return - _start + _START_OFFSET
599 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
600 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
601 STD_EXCEPTION(0xa00, APU, UnknownException)
603 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
606 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
607 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
609 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
610 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
611 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
613 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
615 .globl _end_of_vectors
622 /*****************************************************************************/
623 #if defined(CONFIG_440)
625 /*----------------------------------------------------------------*/
626 /* Clear and set up some registers. */
627 /*----------------------------------------------------------------*/
630 mtspr dec,r0 /* prevent dec exceptions */
631 mtspr tbl,r0 /* prevent fit & wdt exceptions */
633 mtspr tsr,r1 /* clear all timer exception status */
634 mtspr tcr,r0 /* disable all */
635 mtspr esr,r0 /* clear exception syndrome register */
636 mtxer r0 /* clear integer exception register */
638 /*----------------------------------------------------------------*/
639 /* Debug setup -- some (not very good) ice's need an event*/
640 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
641 /* value you need in this case 0x8cff 0000 should do the trick */
642 /*----------------------------------------------------------------*/
643 #if defined(CONFIG_SYS_INIT_DBCR)
646 mtspr dbsr,r1 /* Clear all status bits */
647 lis r0,CONFIG_SYS_INIT_DBCR@h
648 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
653 /*----------------------------------------------------------------*/
654 /* Setup the internal SRAM */
655 /*----------------------------------------------------------------*/
658 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
659 /* Clear Dcache to use as RAM */
660 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
661 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
662 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
663 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
664 rlwinm. r5,r4,0,27,31
676 * Lock the init-ram/stack in d-cache, so that other regions
677 * may use d-cache as well
678 * Note, that this current implementation locks exactly 4k
679 * of d-cache, so please make sure that you don't define a
680 * bigger init-ram area. Take a look at the lwmon5 440EPx
681 * implementation as a reference.
685 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
701 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
703 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
704 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
705 /* not all PPC's have internal SRAM usable as L2-cache */
706 #if defined(CONFIG_440GX) || \
707 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
708 defined(CONFIG_460SX)
709 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
710 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
712 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
713 mtdcr L2_CACHE_CFG,r1
719 and r1,r1,r2 /* Disable parity check */
722 and r1,r1,r2 /* Disable pwr mgmt */
725 lis r1,0x8000 /* BAS = 8000_0000 */
726 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
727 ori r1,r1,0x0980 /* first 64k */
728 mtdcr ISRAM0_SB0CR,r1
730 ori r1,r1,0x0980 /* second 64k */
731 mtdcr ISRAM0_SB1CR,r1
733 ori r1,r1, 0x0980 /* third 64k */
734 mtdcr ISRAM0_SB2CR,r1
736 ori r1,r1, 0x0980 /* fourth 64k */
737 mtdcr ISRAM0_SB3CR,r1
738 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
739 lis r1,0x0000 /* BAS = X_0000_0000 */
740 ori r1,r1,0x0984 /* first 64k */
741 mtdcr ISRAM0_SB0CR,r1
743 ori r1,r1,0x0984 /* second 64k */
744 mtdcr ISRAM0_SB1CR,r1
746 ori r1,r1, 0x0984 /* third 64k */
747 mtdcr ISRAM0_SB2CR,r1
749 ori r1,r1, 0x0984 /* fourth 64k */
750 mtdcr ISRAM0_SB3CR,r1
751 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
755 and r1,r1,r2 /* Disable parity check */
758 and r1,r1,r2 /* Disable pwr mgmt */
761 lis r1,0x0004 /* BAS = 4_0004_0000 */
762 ori r1,r1,0x0984 /* 64k */
763 mtdcr ISRAM1_SB0CR,r1
765 #elif defined(CONFIG_460SX)
766 lis r1,0x0000 /* BAS = 0000_0000 */
767 ori r1,r1,0x0B84 /* first 128k */
768 mtdcr ISRAM0_SB0CR,r1
770 ori r1,r1,0x0B84 /* second 128k */
771 mtdcr ISRAM0_SB1CR,r1
773 ori r1,r1, 0x0B84 /* third 128k */
774 mtdcr ISRAM0_SB2CR,r1
776 ori r1,r1, 0x0B84 /* fourth 128k */
777 mtdcr ISRAM0_SB3CR,r1
778 #elif defined(CONFIG_440GP)
779 ori r1,r1,0x0380 /* 8k rw */
780 mtdcr ISRAM0_SB0CR,r1
781 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
783 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
785 /*----------------------------------------------------------------*/
786 /* Setup the stack in internal SRAM */
787 /*----------------------------------------------------------------*/
788 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
789 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
792 stwu r0,-4(r1) /* Terminate call chain */
794 stwu r1,-8(r1) /* Save back chain and move SP */
795 lis r0,RESET_VECTOR@h /* Address of reset vector */
796 ori r0,r0, RESET_VECTOR@l
797 stwu r1,-8(r1) /* Save back chain and move SP */
798 stw r0,+12(r1) /* Save return addr (underflow vect) */
800 #ifdef CONFIG_NAND_SPL
801 bl nand_boot_common /* will not return */
805 bl cpu_init_f /* run low-level CPU init code (from Flash) */
809 #endif /* CONFIG_440 */
811 /*****************************************************************************/
813 /*----------------------------------------------------------------------- */
814 /* Set up some machine state registers. */
815 /*----------------------------------------------------------------------- */
816 addi r0,r0,0x0000 /* initialize r0 to zero */
817 mtspr esr,r0 /* clear Exception Syndrome Reg */
818 mttcr r0 /* timer control register */
819 mtexier r0 /* disable all interrupts */
820 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
821 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
822 mtdbsr r4 /* clear/reset the dbsr */
823 mtexisr r4 /* clear all pending interrupts */
825 mtexier r4 /* enable critical exceptions */
826 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
827 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
828 mtiocr r4 /* since bit not used) & DRC to latch */
829 /* data bus on rising edge of CAS */
830 /*----------------------------------------------------------------------- */
832 /*----------------------------------------------------------------------- */
834 /*----------------------------------------------------------------------- */
835 /* Invalidate i-cache and d-cache TAG arrays. */
836 /*----------------------------------------------------------------------- */
837 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
838 addi r4,0,1024 /* 1/4 of I-cache */
843 addic. r3,r3,-16 /* move back one cache line */
844 bne ..cloop /* loop back to do rest until r3 = 0 */
847 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
848 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
851 /* first copy IOP480 register base address into r3 */
852 addis r3,0,0x5000 /* IOP480 register base address hi */
853 /* ori r3,r3,0x0000 / IOP480 register base address lo */
856 /* use r4 as the working variable */
857 /* turn on CS3 (LOCCTL.7) */
858 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
859 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
860 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
863 #ifdef CONFIG_DASA_SIM
864 /* use r4 as the working variable */
865 /* turn on MA17 (LOCCTL.7) */
866 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
867 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
868 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
871 /* turn on MA16..13 (LCS0BRD.12 = 0) */
872 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
873 andi. r4,r4,0xefff /* make bit 12 = 0 */
874 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
876 /* make sure above stores all comlete before going on */
879 /* last thing, set local init status done bit (DEVINIT.31) */
880 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
881 oris r4,r4,0x8000 /* make bit 31 = 1 */
882 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
884 /* clear all pending interrupts and disable all interrupts */
885 li r4,-1 /* set p1 to 0xffffffff */
886 stw r4,0x1b0(r3) /* clear all pending interrupts */
887 stw r4,0x1b8(r3) /* clear all pending interrupts */
888 li r4,0 /* set r4 to 0 */
889 stw r4,0x1b4(r3) /* disable all interrupts */
890 stw r4,0x1bc(r3) /* disable all interrupts */
892 /* make sure above stores all comlete before going on */
895 /* Set-up icache cacheability. */
896 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
897 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
901 /* Set-up dcache cacheability. */
902 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
903 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
906 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
907 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
908 li r0, 0 /* Make room for stack frame header and */
909 stwu r0, -4(r1) /* clear final stack frame so that */
910 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
912 GET_GOT /* initialize GOT access */
914 bl board_init_f /* run first part of init code (from Flash) */
916 #endif /* CONFIG_IOP480 */
918 /*****************************************************************************/
919 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
920 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
921 defined(CONFIG_405EX) || defined(CONFIG_405)
922 /*----------------------------------------------------------------------- */
923 /* Clear and set up some registers. */
924 /*----------------------------------------------------------------------- */
926 #if !defined(CONFIG_405EX)
930 * On 405EX, completely clearing the SGR leads to PPC hangup
931 * upon PCIe configuration access. The PCIe memory regions
932 * need to be guarded!
939 mtesr r4 /* clear Exception Syndrome Reg */
940 mttcr r4 /* clear Timer Control Reg */
941 mtxer r4 /* clear Fixed-Point Exception Reg */
942 mtevpr r4 /* clear Exception Vector Prefix Reg */
943 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
944 /* dbsr is cleared by setting bits to 1) */
945 mtdbsr r4 /* clear/reset the dbsr */
947 /* Invalidate the i- and d-caches. */
951 /* Set-up icache cacheability. */
952 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
953 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
957 /* Set-up dcache cacheability. */
958 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
959 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
962 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
963 && !defined (CONFIG_XILINX_405)
964 /*----------------------------------------------------------------------- */
965 /* Tune the speed and size for flash CS0 */
966 /*----------------------------------------------------------------------- */
967 bl ext_bus_cntlr_init
970 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
972 * For boards that don't have OCM and can't use the data cache
973 * for their primordial stack, setup stack here directly after the
974 * SDRAM is initialized in ext_bus_cntlr_init.
976 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
977 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
979 li r0, 0 /* Make room for stack frame header and */
980 stwu r0, -4(r1) /* clear final stack frame so that */
981 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
983 * Set up a dummy frame to store reset vector as return address.
984 * this causes stack underflow to reset board.
986 stwu r1, -8(r1) /* Save back chain and move SP */
987 lis r0, RESET_VECTOR@h /* Address of reset vector */
988 ori r0, r0, RESET_VECTOR@l
989 stwu r1, -8(r1) /* Save back chain and move SP */
990 stw r0, +12(r1) /* Save return addr (underflow vect) */
991 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
993 #if defined(CONFIG_405EP)
994 /*----------------------------------------------------------------------- */
995 /* DMA Status, clear to come up clean */
996 /*----------------------------------------------------------------------- */
997 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
1001 bl ppc405ep_init /* do ppc405ep specific init */
1002 #endif /* CONFIG_405EP */
1004 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1005 #if defined(CONFIG_405EZ)
1006 /********************************************************************
1007 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1008 *******************************************************************/
1010 * We can map the OCM on the PLB3, so map it at
1011 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1013 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1014 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1015 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1016 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
1017 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1018 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
1021 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1022 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1023 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1024 mtdcr ocmdscr1, r3 /* Set Data Side */
1025 mtdcr ocmiscr1, r3 /* Set Instruction Side */
1026 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1027 mtdcr ocmdscr2, r3 /* Set Data Side */
1028 mtdcr ocmiscr2, r3 /* Set Instruction Side */
1029 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1033 #else /* CONFIG_405EZ */
1034 /********************************************************************
1035 * Setup OCM - On Chip Memory
1036 *******************************************************************/
1040 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
1041 mfdcr r4, ocmdscntl /* get data-side IRAM config */
1042 and r3, r3, r0 /* disable data-side IRAM */
1043 and r4, r4, r0 /* disable data-side IRAM */
1044 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
1045 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1048 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1049 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1051 addis r4, 0, 0xC000 /* OCM data area enabled */
1054 #endif /* CONFIG_405EZ */
1057 /*----------------------------------------------------------------------- */
1058 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1059 /*----------------------------------------------------------------------- */
1060 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1063 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1064 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1069 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1070 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1074 * Enable the data cache for the 128MB storage access control region
1075 * at CONFIG_SYS_INIT_RAM_ADDR.
1078 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1079 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1083 * Preallocate data cache lines to be used to avoid a subsequent
1084 * cache miss and an ensuing machine check exception when exceptions
1089 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1090 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1092 lis r4, CONFIG_SYS_INIT_RAM_END@h
1093 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1096 * Convert the size, in bytes, to the number of cache lines/blocks
1099 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1100 srwi r5, r4, L1_CACHE_SHIFT
1106 /* Preallocate the computed number of cache blocks. */
1107 ..alloc_dcache_block:
1109 addi r3, r3, L1_CACHE_BYTES
1110 bdnz ..alloc_dcache_block
1114 * Load the initial stack pointer and data area and convert the size,
1115 * in bytes, to the number of words to initialize to a known value.
1117 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1118 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1120 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1121 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1124 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1125 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1127 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1128 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1135 * Make room for stack frame header and clear final stack frame so
1136 * that stack backtraces terminate cleanly.
1142 * Set up a dummy frame to store reset vector as return address.
1143 * this causes stack underflow to reset board.
1145 stwu r1, -8(r1) /* Save back chain and move SP */
1146 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1147 ori r0, r0, RESET_VECTOR@l
1148 stwu r1, -8(r1) /* Save back chain and move SP */
1149 stw r0, +12(r1) /* Save return addr (underflow vect) */
1151 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1152 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1157 /* Set up Stack at top of OCM */
1158 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1159 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1161 /* Set up a zeroized stack frame so that backtrace works right */
1167 * Set up a dummy frame to store reset vector as return address.
1168 * this causes stack underflow to reset board.
1170 stwu r1, -8(r1) /* Save back chain and move SP */
1171 lis r0, RESET_VECTOR@h /* Address of reset vector */
1172 ori r0, r0, RESET_VECTOR@l
1173 stwu r1, -8(r1) /* Save back chain and move SP */
1174 stw r0, +12(r1) /* Save return addr (underflow vect) */
1175 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1177 #ifdef CONFIG_NAND_SPL
1178 bl nand_boot_common /* will not return */
1180 GET_GOT /* initialize GOT access */
1182 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1184 /* NEVER RETURNS! */
1185 bl board_init_f /* run first part of init code (from Flash) */
1186 #endif /* CONFIG_NAND_SPL */
1188 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1189 /*----------------------------------------------------------------------- */
1192 #ifndef CONFIG_NAND_SPL
1194 * This code finishes saving the registers to the exception frame
1195 * and jumps to the appropriate handler for the exception.
1196 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1198 .globl transfer_to_handler
1199 transfer_to_handler:
1209 andi. r24,r23,0x3f00 /* get vector offset */
1213 mtspr SPRG2,r22 /* r1 is now kernel sp */
1214 lwz r24,0(r23) /* virtual address of handler */
1215 lwz r23,4(r23) /* where to go when done */
1220 rfi /* jump to handler, enable MMU */
1223 mfmsr r28 /* Disable interrupts */
1227 SYNC /* Some chip revs need this... */
1242 lwz r2,_NIP(r1) /* Restore environment */
1253 mfmsr r28 /* Disable interrupts */
1257 SYNC /* Some chip revs need this... */
1272 lwz r2,_NIP(r1) /* Restore environment */
1284 mfmsr r28 /* Disable interrupts */
1288 SYNC /* Some chip revs need this... */
1303 lwz r2,_NIP(r1) /* Restore environment */
1312 #endif /* CONFIG_440 */
1320 /*------------------------------------------------------------------------------- */
1321 /* Function: out16 */
1322 /* Description: Output 16 bits */
1323 /*------------------------------------------------------------------------------- */
1329 /*------------------------------------------------------------------------------- */
1330 /* Function: out16r */
1331 /* Description: Byte reverse and output 16 bits */
1332 /*------------------------------------------------------------------------------- */
1338 /*------------------------------------------------------------------------------- */
1339 /* Function: out32r */
1340 /* Description: Byte reverse and output 32 bits */
1341 /*------------------------------------------------------------------------------- */
1347 /*------------------------------------------------------------------------------- */
1348 /* Function: in16 */
1349 /* Description: Input 16 bits */
1350 /*------------------------------------------------------------------------------- */
1356 /*------------------------------------------------------------------------------- */
1357 /* Function: in16r */
1358 /* Description: Input 16 bits and byte reverse */
1359 /*------------------------------------------------------------------------------- */
1365 /*------------------------------------------------------------------------------- */
1366 /* Function: in32r */
1367 /* Description: Input 32 bits and byte reverse */
1368 /*------------------------------------------------------------------------------- */
1375 * void relocate_code (addr_sp, gd, addr_moni)
1377 * This "function" does not return, instead it continues in RAM
1378 * after relocating the monitor code.
1380 * r3 = Relocated stack pointer
1381 * r4 = Relocated global data pointer
1382 * r5 = Relocated text pointer
1384 .globl relocate_code
1386 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1388 * We need to flush the initial global data (gd_t) before the dcache
1389 * will be invalidated.
1392 /* Save registers */
1397 /* Flush initial global data range */
1399 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1400 bl flush_dcache_range
1402 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1404 * Undo the earlier data cache set-up for the primordial stack and
1405 * data area. First, invalidate the data cache and then disable data
1406 * cacheability for that area. Finally, restore the EBC values, if
1410 /* Invalidate the primordial stack and data area in cache */
1411 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1412 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1414 lis r4, CONFIG_SYS_INIT_RAM_END@h
1415 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1418 bl invalidate_dcache_range
1420 /* Disable cacheability for the region */
1422 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1423 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1427 /* Restore the EBC parameters */
1431 ori r3, r3, PBxAP_VAL@l
1437 ori r3, r3, PBxCR_VAL@l
1439 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1441 /* Restore registers */
1445 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1447 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1449 * Unlock the previously locked d-cache
1453 /* set TFLOOR/NFLOOR to 0 again */
1469 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1471 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1472 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1473 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1474 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1475 defined(CONFIG_460SX)
1477 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1478 * to speed up the boot process. Now this cache needs to be disabled.
1480 iccci 0,0 /* Invalidate inst cache */
1481 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1485 /* Clear all potential pending exceptions */
1488 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1489 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1491 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1492 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1493 tlbre r0,r1,0x0002 /* Read contents */
1494 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1495 tlbwe r0,r1,0x0002 /* Save it out */
1498 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1499 mr r1, r3 /* Set new stack pointer */
1500 mr r9, r4 /* Save copy of Init Data pointer */
1501 mr r10, r5 /* Save copy of Destination Address */
1503 mr r3, r5 /* Destination Address */
1504 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1505 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1506 lwz r5, GOT(__init_end)
1508 li r6, L1_CACHE_BYTES /* Cache Line Size */
1513 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1519 /* First our own GOT */
1521 /* then the one used by the C code */
1531 beq cr1,4f /* In place copy is not necessary */
1532 beq 7f /* Protect against 0 count */
1551 * Now flush the cache: note that we must start from a cache aligned
1552 * address. Otherwise we might miss one cache line.
1556 beq 7f /* Always flush prefetch queue in any case */
1564 sync /* Wait for all dcbst to complete on bus */
1570 7: sync /* Wait for all icbi to complete on bus */
1574 * We are done. Do not return, instead branch to second part of board
1575 * initialization, now running from RAM.
1578 addi r0, r10, in_ram - _start + _START_OFFSET
1580 blr /* NEVER RETURNS! */
1585 * Relocation Function, r14 point to got2+0x8000
1587 * Adjust got2 pointers, no need to check for 0, this code
1588 * already puts a few entries in the table.
1590 li r0,__got2_entries@sectoff@l
1591 la r3,GOT(_GOT2_TABLE_)
1592 lwz r11,GOT(_GOT2_TABLE_)
1602 * Now adjust the fixups and the pointers to the fixups
1603 * in case we need to move ourselves again.
1605 2: li r0,__fixup_entries@sectoff@l
1606 lwz r3,GOT(_FIXUP_TABLE_)
1620 * Now clear BSS segment
1622 lwz r3,GOT(__bss_start)
1645 mr r3, r9 /* Init Data pointer */
1646 mr r4, r10 /* Destination Address */
1650 * Copy exception vector code to low memory
1653 * r7: source address, r8: end address, r9: target address
1657 lwz r7, GOT(_start_of_vectors)
1658 lwz r8, GOT(_end_of_vectors)
1660 li r9, 0x100 /* reset vector always at 0x100 */
1663 bgelr /* return if r7>=r8 - just in case */
1665 mflr r4 /* save link register */
1675 * relocate `hdlr' and `int_return' entries
1677 li r7, .L_MachineCheck - _start + _START_OFFSET
1678 li r8, Alignment - _start + _START_OFFSET
1681 addi r7, r7, 0x100 /* next exception vector */
1685 li r7, .L_Alignment - _start + _START_OFFSET
1688 li r7, .L_ProgramCheck - _start + _START_OFFSET
1692 li r7, .L_FPUnavailable - _start + _START_OFFSET
1695 li r7, .L_Decrementer - _start + _START_OFFSET
1698 li r7, .L_APU - _start + _START_OFFSET
1701 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1704 li r7, .L_DataTLBError - _start + _START_OFFSET
1706 #else /* CONFIG_440 */
1707 li r7, .L_PIT - _start + _START_OFFSET
1710 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1713 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1715 #endif /* CONFIG_440 */
1717 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1720 #if !defined(CONFIG_440)
1721 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1722 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1723 mtmsr r7 /* change MSR */
1726 b __440_msr_continue
1729 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1730 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1738 mtlr r4 /* restore link register */
1742 * Function: relocate entries for one exception vector
1745 lwz r0, 0(r7) /* hdlr ... */
1746 add r0, r0, r3 /* ... += dest_addr */
1749 lwz r0, 4(r7) /* int_return ... */
1750 add r0, r0, r3 /* ... += dest_addr */
1755 #if defined(CONFIG_440)
1756 /*----------------------------------------------------------------------------+
1758 +----------------------------------------------------------------------------*/
1759 function_prolog(dcbz_area)
1760 rlwinm. r5,r4,0,27,31
1761 rlwinm r5,r4,27,5,31
1770 function_epilog(dcbz_area)
1771 #endif /* CONFIG_440 */
1772 #endif /* CONFIG_NAND_SPL */
1774 /*------------------------------------------------------------------------------- */
1776 /* Description: Input 8 bits */
1777 /*------------------------------------------------------------------------------- */
1783 /*------------------------------------------------------------------------------- */
1784 /* Function: out8 */
1785 /* Description: Output 8 bits */
1786 /*------------------------------------------------------------------------------- */
1792 /*------------------------------------------------------------------------------- */
1793 /* Function: out32 */
1794 /* Description: Output 32 bits */
1795 /*------------------------------------------------------------------------------- */
1801 /*------------------------------------------------------------------------------- */
1802 /* Function: in32 */
1803 /* Description: Input 32 bits */
1804 /*------------------------------------------------------------------------------- */
1810 /**************************************************************************/
1811 /* PPC405EP specific stuff */
1812 /**************************************************************************/
1816 #ifdef CONFIG_BUBINGA
1818 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1819 * function) to support FPGA and NVRAM accesses below.
1822 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1823 ori r3,r3,GPIO0_OSRH@l
1824 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1825 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1828 ori r3,r3,GPIO0_OSRL@l
1829 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1830 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1833 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1834 ori r3,r3,GPIO0_ISR1H@l
1835 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1836 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1838 lis r3,GPIO0_ISR1L@h
1839 ori r3,r3,GPIO0_ISR1L@l
1840 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1841 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1844 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1845 ori r3,r3,GPIO0_TSRH@l
1846 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1847 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1850 ori r3,r3,GPIO0_TSRL@l
1851 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1852 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1855 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1856 ori r3,r3,GPIO0_TCR@l
1857 lis r4,CONFIG_SYS_GPIO0_TCR@h
1858 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1861 li r3,pb1ap /* program EBC bank 1 for RTC access */
1863 lis r3,CONFIG_SYS_EBC_PB1AP@h
1864 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1868 lis r3,CONFIG_SYS_EBC_PB1CR@h
1869 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1872 li r3,pb1ap /* program EBC bank 1 for RTC access */
1874 lis r3,CONFIG_SYS_EBC_PB1AP@h
1875 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1879 lis r3,CONFIG_SYS_EBC_PB1CR@h
1880 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1883 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1885 lis r3,CONFIG_SYS_EBC_PB4AP@h
1886 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1890 lis r3,CONFIG_SYS_EBC_PB4CR@h
1891 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1896 !-----------------------------------------------------------------------
1897 ! Check to see if chip is in bypass mode.
1898 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1899 ! CPU reset Otherwise, skip this step and keep going.
1900 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1901 ! will not be fast enough for the SDRAM (min 66MHz)
1902 !-----------------------------------------------------------------------
1904 mfdcr r5, CPC0_PLLMR1
1905 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1908 beq pll_done /* if SSCS =b'1' then PLL has */
1909 /* already been set */
1910 /* and CPU has been reset */
1911 /* so skip to next section */
1913 #ifdef CONFIG_BUBINGA
1915 !-----------------------------------------------------------------------
1916 ! Read NVRAM to get value to write in PLLMR.
1917 ! If value has not been correctly saved, write default value
1918 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1919 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1921 ! WARNING: This code assumes the first three words in the nvram_t
1922 ! structure in openbios.h. Changing the beginning of
1923 ! the structure will break this code.
1925 !-----------------------------------------------------------------------
1927 addis r3,0,NVRAM_BASE@h
1928 addi r3,r3,NVRAM_BASE@l
1931 addis r5,0,NVRVFY1@h
1932 addi r5,r5,NVRVFY1@l
1933 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1937 addis r5,0,NVRVFY2@h
1938 addi r5,r5,NVRVFY2@l
1939 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1941 addi r3,r3,8 /* Skip over conf_size */
1942 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1943 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1944 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1945 cmpi cr0,0,r5,1 /* See if PLL is locked */
1948 #endif /* CONFIG_BUBINGA */
1952 andi. r5, r4, CPC0_BOOT_SEP@l
1953 bne strap_1 /* serial eeprom present */
1954 addis r5,0,CPLD_REG0_ADDR@h
1955 ori r5,r5,CPLD_REG0_ADDR@l
1958 #endif /* CONFIG_TAIHU */
1960 #if defined(CONFIG_ZEUS)
1962 andi. r5, r4, CPC0_BOOT_SEP@l
1963 bne strap_1 /* serial eeprom present */
1970 mfdcr r3, CPC0_PLLMR0
1971 mfdcr r4, CPC0_PLLMR1
1975 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1976 ori r3,r3,PLLMR0_DEFAULT@l /* */
1977 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1978 ori r4,r4,PLLMR1_DEFAULT@l /* */
1983 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1984 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1985 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1986 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1989 mfdcr r3, CPC0_PLLMR0
1990 mfdcr r4, CPC0_PLLMR1
1991 #endif /* CONFIG_TAIHU */
1994 b pll_write /* Write the CPC0_PLLMR with new value */
1998 !-----------------------------------------------------------------------
1999 ! Clear Soft Reset Register
2000 ! This is needed to enable PCI if not booting from serial EPROM
2001 !-----------------------------------------------------------------------
2011 blr /* return to main code */
2014 !-----------------------------------------------------------------------------
2015 ! Function: pll_write
2016 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2018 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2020 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2021 ! 4. PLL Reset is cleared
2022 ! 5. Wait 100us for PLL to lock
2023 ! 6. A core reset is performed
2024 ! Input: r3 = Value to write to CPC0_PLLMR0
2025 ! Input: r4 = Value to write to CPC0_PLLMR1
2027 !-----------------------------------------------------------------------------
2033 ori r5,r5,0x0101 /* Stop the UART clocks */
2034 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2036 mfdcr r5, CPC0_PLLMR1
2037 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2038 mtdcr CPC0_PLLMR1,r5
2039 oris r5,r5,0x4000 /* Set PLL Reset */
2040 mtdcr CPC0_PLLMR1,r5
2042 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2043 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2044 oris r5,r5,0x4000 /* Set PLL Reset */
2045 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2046 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2047 mtdcr CPC0_PLLMR1,r5
2050 ! Wait min of 100us for PLL to lock.
2051 ! See CMOS 27E databook for more info.
2052 ! At 200MHz, that means waiting 20,000 instructions
2054 addi r3,0,20000 /* 2000 = 0x4e20 */
2059 oris r5,r5,0x8000 /* Enable PLL */
2060 mtdcr CPC0_PLLMR1,r5 /* Engage */
2063 * Reset CPU to guarantee timings are OK
2064 * Not sure if this is needed...
2067 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2068 /* execution will continue from the poweron */
2069 /* vector of 0xfffffffc */
2070 #endif /* CONFIG_405EP */
2072 #if defined(CONFIG_440)
2073 /*----------------------------------------------------------------------------+
2075 +----------------------------------------------------------------------------*/
2076 function_prolog(mttlb3)
2079 function_epilog(mttlb3)
2081 /*----------------------------------------------------------------------------+
2083 +----------------------------------------------------------------------------*/
2084 function_prolog(mftlb3)
2087 function_epilog(mftlb3)
2089 /*----------------------------------------------------------------------------+
2091 +----------------------------------------------------------------------------*/
2092 function_prolog(mttlb2)
2095 function_epilog(mttlb2)
2097 /*----------------------------------------------------------------------------+
2099 +----------------------------------------------------------------------------*/
2100 function_prolog(mftlb2)
2103 function_epilog(mftlb2)
2105 /*----------------------------------------------------------------------------+
2107 +----------------------------------------------------------------------------*/
2108 function_prolog(mttlb1)
2111 function_epilog(mttlb1)
2113 /*----------------------------------------------------------------------------+
2115 +----------------------------------------------------------------------------*/
2116 function_prolog(mftlb1)
2119 function_epilog(mftlb1)
2120 #endif /* CONFIG_440 */
2122 #if defined(CONFIG_NAND_SPL)
2124 * void nand_boot_relocate(dst, src, bytes)
2126 * r3 = Destination address to copy code to (in SDRAM)
2127 * r4 = Source address to copy code from
2128 * r5 = size to copy in bytes
2136 * Copy SPL from icache into SDRAM
2148 * Calculate "corrected" link register, so that we "continue"
2149 * in execution in destination range
2151 sub r3,r7,r6 /* r3 = src - dst */
2152 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2158 * First initialize SDRAM. It has to be available *before* calling
2161 lis r3,CONFIG_SYS_SDRAM_BASE@h
2162 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2166 * Now copy the 4k SPL code into SDRAM and continue execution
2169 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2170 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2171 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2172 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2173 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2174 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2175 bl nand_boot_relocate
2178 * We're running from SDRAM now!!!
2180 * It is necessary for 4xx systems to relocate from running at
2181 * the original location (0xfffffxxx) to somewhere else (SDRAM
2182 * preferably). This is because CS0 needs to be reconfigured for
2183 * NAND access. And we can't reconfigure this CS when currently
2184 * "running" from it.
2188 * Finally call nand_boot() to load main NAND U-Boot image from
2189 * NAND and jump to it.
2191 bl nand_boot /* will not return */
2192 #endif /* CONFIG_NAND_SPL */