2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*------------------------------------------------------------------------------+ */
26 /* This source code has been made available to you by IBM on an AS-IS */
27 /* basis. Anyone receiving this source is licensed under IBM */
28 /* copyrights to use it in any way he or she deems fit, including */
29 /* copying it, modifying it, compiling it, and redistributing it either */
30 /* with or without modifications. No license under IBM patents or */
31 /* patent applications is to be implied by the copyright license. */
33 /* Any user of this software should understand that IBM cannot provide */
34 /* technical support for this software and will not be responsible for */
35 /* any consequences resulting from the use of this software. */
37 /* Any person who transfers this source code or any derivative work */
38 /* must include the IBM copyright notice, this paragraph, and the */
39 /* preceding two paragraphs in the transferred software. */
41 /* COPYRIGHT I B M CORPORATION 1995 */
42 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
43 /*------------------------------------------------------------------------------- */
45 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
48 * The processor starts at 0xfffffffc and the code is executed
50 * in memory, but as long we don't jump around before relocating.
51 * board_init lies at a quite high address and when the cpu has
52 * jumped there, everything is ok.
53 * This works because the cpu gives the FLASH (CS0) the whole
54 * address space at startup, and board_init lies as a echo of
55 * the flash somewhere up there in the memorymap.
57 * board_init will change CS0 to be positioned at the correct
58 * address and (s)dram will be positioned at address 0
65 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
67 #include <ppc_asm.tmpl>
70 #include <asm/cache.h>
73 #ifndef CONFIG_IDENT_STRING
74 #define CONFIG_IDENT_STRING ""
77 #ifdef CFG_INIT_DCACHE_CS
78 # if (CFG_INIT_DCACHE_CS == 0)
82 # if (CFG_INIT_DCACHE_CS == 1)
86 # if (CFG_INIT_DCACHE_CS == 2)
90 # if (CFG_INIT_DCACHE_CS == 3)
94 # if (CFG_INIT_DCACHE_CS == 4)
98 # if (CFG_INIT_DCACHE_CS == 5)
102 # if (CFG_INIT_DCACHE_CS == 6)
106 # if (CFG_INIT_DCACHE_CS == 7)
110 #endif /* CFG_INIT_DCACHE_CS */
112 /* We don't want the MMU yet.
115 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
118 .extern ext_bus_cntlr_init
122 * Set up GOT: Global Offset Table
124 * Use r14 to access the GOT
127 GOT_ENTRY(_GOT2_TABLE_)
128 GOT_ENTRY(_FIXUP_TABLE_)
131 GOT_ENTRY(_start_of_vectors)
132 GOT_ENTRY(_end_of_vectors)
133 GOT_ENTRY(transfer_to_handler)
135 GOT_ENTRY(__init_end)
137 GOT_ENTRY(__bss_start)
141 * 440 Startup -- on reset only the top 4k of the effective
142 * address space is mapped in by an entry in the instruction
143 * and data shadow TLB. The .bootpg section is located in the
144 * top 4k & does only what's necessary to map in the the rest
145 * of the boot rom. Once the boot rom is mapped in we can
146 * proceed with normal startup.
148 * NOTE: CS0 only covers the top 2MB of the effective address
152 #if defined(CONFIG_440)
153 .section .bootpg,"ax"
156 /**************************************************************************/
158 /*----------------------------------------------------------------+
159 | Core bug fix. Clear the esr
160 +-----------------------------------------------------------------*/
163 /*----------------------------------------------------------------*/
164 /* Clear and set up some registers. */
165 /*----------------------------------------------------------------*/
166 iccci r0,r0 /* NOTE: operands not used for 440 */
167 dccci r0,r0 /* NOTE: operands not used for 440 */
174 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */
180 /*----------------------------------------------------------------*/
181 /* Initialize debug */
182 /*----------------------------------------------------------------*/
195 mtspr dbsr,r1 /* Clear all valid bits */
197 /*----------------------------------------------------------------*/
199 /*----------------------------------------------------------------*/
200 /* Disable store gathering & broadcast, guarantee inst/data
201 * cache block touch, force load/store alignment
202 * (see errata 1.12: 440_33)
204 lis r1,0x0030 /* store gathering & broadcast disable */
205 ori r1,r1,0x6000 /* cache touch */
208 #if defined (CONFIG_440SPE)
209 /*----------------------------------------------------------------+
210 | Initialize Core Configuration Reg1.
211 | a. ICDPEI: Record even parity. Normal operation.
212 | b. ICTPEI: Record even parity. Normal operation.
213 | c. DCTPEI: Record even parity. Normal operation.
214 | d. DCDPEI: Record even parity. Normal operation.
215 | e. DCUPEI: Record even parity. Normal operation.
216 | f. DCMPEI: Record even parity. Normal operation.
217 | g. FCOM: Normal operation
218 | h. MMUPEI: Record even parity. Normal operation.
219 | i. FFF: Flush only as much data as necessary.
220 | j. TCS: Timebase increments from CPU clock.
221 +-----------------------------------------------------------------*/
225 /*----------------------------------------------------------------+
226 | Reset the timebase.
227 | The previous write to CCR1 sets the timebase source.
228 +-----------------------------------------------------------------*/
233 /*----------------------------------------------------------------*/
234 /* Setup interrupt vectors */
235 /*----------------------------------------------------------------*/
236 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
238 mtspr ivor0,r1 /* Critical input */
240 mtspr ivor1,r1 /* Machine check */
242 mtspr ivor2,r1 /* Data storage */
244 mtspr ivor3,r1 /* Instruction storage */
246 mtspr ivor4,r1 /* External interrupt */
248 mtspr ivor5,r1 /* Alignment */
250 mtspr ivor6,r1 /* Program check */
252 mtspr ivor7,r1 /* Floating point unavailable */
254 mtspr ivor8,r1 /* System call */
256 mtspr ivor10,r1 /* Decrementer (PIT for 440) */
258 mtspr ivor13,r1 /* Data TLB error */
260 mtspr ivor14,r1 /* Instr TLB error */
262 mtspr ivor15,r1 /* Debug */
264 /*----------------------------------------------------------------*/
265 /* Configure cache regions */
266 /*----------------------------------------------------------------*/
284 /*----------------------------------------------------------------*/
285 /* Cache victim limits */
286 /*----------------------------------------------------------------*/
287 /* floors 0, ceiling max to use the entire cache -- nothing locked
294 /*----------------------------------------------------------------+
295 |Initialize MMUCR[STID] = 0.
296 +-----------------------------------------------------------------*/
303 /*----------------------------------------------------------------*/
304 /* Clear all TLB entries -- TID = 0, TS = 0 */
305 /*----------------------------------------------------------------*/
307 li r1,0x003f /* 64 TLB entries */
309 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
315 /*----------------------------------------------------------------*/
316 /* TLB entry setup -- step thru tlbtab */
317 /*----------------------------------------------------------------*/
318 bl tlbtab /* Get tlbtab pointer */
320 li r1,0x003f /* 64 TLB entries max */
327 beq 2f /* 0 marks end */
330 tlbwe r0,r4,0 /* TLB Word 0 */
331 tlbwe r1,r4,1 /* TLB Word 1 */
332 tlbwe r2,r4,2 /* TLB Word 2 */
333 addi r4,r4,1 /* Next TLB */
336 /*----------------------------------------------------------------*/
337 /* Continue from 'normal' start */
338 /*----------------------------------------------------------------*/
343 mtspr srr1,r0 /* Keep things disabled for now */
347 #endif /* CONFIG_440 */
350 * r3 - 1st arg to board_init(): IMMP pointer
351 * r4 - 2nd arg to board_init(): boot flag
354 .long 0x27051956 /* U-Boot Magic Number */
355 .globl version_string
357 .ascii U_BOOT_VERSION
358 .ascii " (", __DATE__, " - ", __TIME__, ")"
359 .ascii CONFIG_IDENT_STRING, "\0"
362 * Maybe this should be moved somewhere else because the current
363 * location (0x100) is where the CriticalInput Execption should be.
365 . = EXC_OFF_SYS_RESET
369 /*****************************************************************************/
370 #if defined(CONFIG_440)
372 /*----------------------------------------------------------------*/
373 /* Clear and set up some registers. */
374 /*----------------------------------------------------------------*/
377 mtspr dec,r0 /* prevent dec exceptions */
378 mtspr tbl,r0 /* prevent fit & wdt exceptions */
380 mtspr tsr,r1 /* clear all timer exception status */
381 mtspr tcr,r0 /* disable all */
382 mtspr esr,r0 /* clear exception syndrome register */
383 mtxer r0 /* clear integer exception register */
385 /*----------------------------------------------------------------*/
386 /* Debug setup -- some (not very good) ice's need an event*/
387 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
388 /* value you need in this case 0x8cff 0000 should do the trick */
389 /*----------------------------------------------------------------*/
390 #if defined(CFG_INIT_DBCR)
393 mtspr dbsr,r1 /* Clear all status bits */
394 lis r0,CFG_INIT_DBCR@h
395 ori r0,r0,CFG_INIT_DBCR@l
400 /*----------------------------------------------------------------*/
401 /* Setup the internal SRAM */
402 /*----------------------------------------------------------------*/
404 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
405 /* Clear Dcache to use as RAM */
406 addis r3,r0,CFG_INIT_RAM_ADDR@h
407 ori r3,r3,CFG_INIT_RAM_ADDR@l
408 addis r4,r0,CFG_INIT_RAM_END@h
409 ori r4,r4,CFG_INIT_RAM_END@l
410 rlwinm. r5,r4,0,27,31
421 #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
422 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
424 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
429 and r1,r1,r2 /* Disable parity check */
432 andis. r1,r1,r2 /* Disable pwr mgmt */
435 lis r1,0x8000 /* BAS = 8000_0000 */
436 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
437 ori r1,r1,0x0980 /* first 64k */
438 mtdcr isram0_sb0cr,r1
440 ori r1,r1,0x0980 /* second 64k */
441 mtdcr isram0_sb1cr,r1
443 ori r1,r1, 0x0980 /* third 64k */
444 mtdcr isram0_sb2cr,r1
446 ori r1,r1, 0x0980 /* fourth 64k */
447 mtdcr isram0_sb3cr,r1
448 #elif defined(CONFIG_440SPE)
449 lis r1,0x0000 /* BAS = 0000_0000 */
450 ori r1,r1,0x0984 /* first 64k */
451 mtdcr isram0_sb0cr,r1
453 ori r1,r1,0x0984 /* second 64k */
454 mtdcr isram0_sb1cr,r1
456 ori r1,r1, 0x0984 /* third 64k */
457 mtdcr isram0_sb2cr,r1
459 ori r1,r1, 0x0984 /* fourth 64k */
460 mtdcr isram0_sb3cr,r1
462 ori r1,r1,0x0380 /* 8k rw */
463 mtdcr isram0_sb0cr,r1
467 /*----------------------------------------------------------------*/
468 /* Setup the stack in internal SRAM */
469 /*----------------------------------------------------------------*/
470 lis r1,CFG_INIT_RAM_ADDR@h
471 ori r1,r1,CFG_INIT_SP_OFFSET@l
474 stwu r0,-4(r1) /* Terminate call chain */
476 stwu r1,-8(r1) /* Save back chain and move SP */
477 lis r0,RESET_VECTOR@h /* Address of reset vector */
478 ori r0,r0, RESET_VECTOR@l
479 stwu r1,-8(r1) /* Save back chain and move SP */
480 stw r0,+12(r1) /* Save return addr (underflow vect) */
484 bl cpu_init_f /* run low-level CPU init code (from Flash) */
487 #endif /* CONFIG_440 */
489 /*****************************************************************************/
491 /*----------------------------------------------------------------------- */
492 /* Set up some machine state registers. */
493 /*----------------------------------------------------------------------- */
494 addi r0,r0,0x0000 /* initialize r0 to zero */
495 mtspr esr,r0 /* clear Exception Syndrome Reg */
496 mttcr r0 /* timer control register */
497 mtexier r0 /* disable all interrupts */
498 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
499 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
500 mtdbsr r4 /* clear/reset the dbsr */
501 mtexisr r4 /* clear all pending interrupts */
503 mtexier r4 /* enable critical exceptions */
504 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
505 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
506 mtiocr r4 /* since bit not used) & DRC to latch */
507 /* data bus on rising edge of CAS */
508 /*----------------------------------------------------------------------- */
510 /*----------------------------------------------------------------------- */
512 /*----------------------------------------------------------------------- */
513 /* Invalidate i-cache and d-cache TAG arrays. */
514 /*----------------------------------------------------------------------- */
515 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
516 addi r4,0,1024 /* 1/4 of I-cache */
521 addic. r3,r3,-16 /* move back one cache line */
522 bne ..cloop /* loop back to do rest until r3 = 0 */
525 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
526 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
529 /* first copy IOP480 register base address into r3 */
530 addis r3,0,0x5000 /* IOP480 register base address hi */
531 /* ori r3,r3,0x0000 / IOP480 register base address lo */
534 /* use r4 as the working variable */
535 /* turn on CS3 (LOCCTL.7) */
536 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
537 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
538 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
541 #ifdef CONFIG_DASA_SIM
542 /* use r4 as the working variable */
543 /* turn on MA17 (LOCCTL.7) */
544 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
545 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
546 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
549 /* turn on MA16..13 (LCS0BRD.12 = 0) */
550 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
551 andi. r4,r4,0xefff /* make bit 12 = 0 */
552 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
554 /* make sure above stores all comlete before going on */
557 /* last thing, set local init status done bit (DEVINIT.31) */
558 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
559 oris r4,r4,0x8000 /* make bit 31 = 1 */
560 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
562 /* clear all pending interrupts and disable all interrupts */
563 li r4,-1 /* set p1 to 0xffffffff */
564 stw r4,0x1b0(r3) /* clear all pending interrupts */
565 stw r4,0x1b8(r3) /* clear all pending interrupts */
566 li r4,0 /* set r4 to 0 */
567 stw r4,0x1b4(r3) /* disable all interrupts */
568 stw r4,0x1bc(r3) /* disable all interrupts */
570 /* make sure above stores all comlete before going on */
573 /*----------------------------------------------------------------------- */
574 /* Enable two 128MB cachable regions. */
575 /*----------------------------------------------------------------------- */
578 mticcr r1 /* instruction cache */
582 mtdccr r1 /* data cache */
584 addis r1,r0,CFG_INIT_RAM_ADDR@h
585 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
586 li r0, 0 /* Make room for stack frame header and */
587 stwu r0, -4(r1) /* clear final stack frame so that */
588 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
590 GET_GOT /* initialize GOT access */
592 bl board_init_f /* run first part of init code (from Flash) */
594 #endif /* CONFIG_IOP480 */
596 /*****************************************************************************/
597 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
598 /*----------------------------------------------------------------------- */
599 /* Clear and set up some registers. */
600 /*----------------------------------------------------------------------- */
604 mtesr r4 /* clear Exception Syndrome Reg */
605 mttcr r4 /* clear Timer Control Reg */
606 mtxer r4 /* clear Fixed-Point Exception Reg */
607 mtevpr r4 /* clear Exception Vector Prefix Reg */
608 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
609 /* dbsr is cleared by setting bits to 1) */
610 mtdbsr r4 /* clear/reset the dbsr */
612 /*----------------------------------------------------------------------- */
613 /* Invalidate I and D caches. Enable I cache for defined memory regions */
614 /* to speed things up. Leave the D cache disabled for now. It will be */
615 /* enabled/left disabled later based on user selected menu options. */
616 /* Be aware that the I cache may be disabled later based on the menu */
617 /* options as well. See miscLib/main.c. */
618 /*----------------------------------------------------------------------- */
622 /*----------------------------------------------------------------------- */
623 /* Enable two 128MB cachable regions. */
624 /*----------------------------------------------------------------------- */
627 mticcr r4 /* instruction cache */
632 mtdccr r4 /* data cache */
634 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
635 /*----------------------------------------------------------------------- */
636 /* Tune the speed and size for flash CS0 */
637 /*----------------------------------------------------------------------- */
638 bl ext_bus_cntlr_init
641 #if defined(CONFIG_405EP)
642 /*----------------------------------------------------------------------- */
643 /* DMA Status, clear to come up clean */
644 /*----------------------------------------------------------------------- */
645 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
649 bl ppc405ep_init /* do ppc405ep specific init */
650 #endif /* CONFIG_405EP */
652 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
653 /********************************************************************
654 * Setup OCM - On Chip Memory
655 *******************************************************************/
659 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
660 mfdcr r4, ocmdscntl /* get data-side IRAM config */
661 and r3, r3, r0 /* disable data-side IRAM */
662 and r4, r4, r0 /* disable data-side IRAM */
663 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
664 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
667 addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
669 addis r4, 0, 0xC000 /* OCM data area enabled */
674 /*----------------------------------------------------------------------- */
675 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
676 /*----------------------------------------------------------------------- */
677 #ifdef CFG_INIT_DCACHE_CS
678 /*----------------------------------------------------------------------- */
679 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
680 /* used as temporary stack pointer for stage0 */
681 /*----------------------------------------------------------------------- */
694 /* turn on data chache for this region */
698 /* set stack pointer and clear stack to known value */
700 lis r1,CFG_INIT_RAM_ADDR@h
701 ori r1,r1,CFG_INIT_SP_OFFSET@l
703 li r4,2048 /* we store 2048 words to stack */
706 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
707 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
709 lis r4,0xdead /* we store 0xdeaddead in the stack */
716 li r0, 0 /* Make room for stack frame header and */
717 stwu r0, -4(r1) /* clear final stack frame so that */
718 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
720 * Set up a dummy frame to store reset vector as return address.
721 * this causes stack underflow to reset board.
723 stwu r1, -8(r1) /* Save back chain and move SP */
724 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
725 ori r0, r0, RESET_VECTOR@l
726 stwu r1, -8(r1) /* Save back chain and move SP */
727 stw r0, +12(r1) /* Save return addr (underflow vect) */
729 #elif defined(CFG_TEMP_STACK_OCM) && \
730 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
735 /* Set up Stack at top of OCM */
736 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
737 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
739 /* Set up a zeroized stack frame so that backtrace works right */
745 * Set up a dummy frame to store reset vector as return address.
746 * this causes stack underflow to reset board.
748 stwu r1, -8(r1) /* Save back chain and move SP */
749 lis r0, RESET_VECTOR@h /* Address of reset vector */
750 ori r0, r0, RESET_VECTOR@l
751 stwu r1, -8(r1) /* Save back chain and move SP */
752 stw r0, +12(r1) /* Save return addr (underflow vect) */
753 #endif /* CFG_INIT_DCACHE_CS */
755 /*----------------------------------------------------------------------- */
756 /* Initialize SDRAM Controller */
757 /*----------------------------------------------------------------------- */
761 * Setup temporary stack pointer only for boards
762 * that do not use SDRAM SPD I2C stuff since it
763 * is already initialized to use DCACHE or OCM
766 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
767 lis r1, CFG_INIT_RAM_ADDR@h
768 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
770 li r0, 0 /* Make room for stack frame header and */
771 stwu r0, -4(r1) /* clear final stack frame so that */
772 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
774 * Set up a dummy frame to store reset vector as return address.
775 * this causes stack underflow to reset board.
777 stwu r1, -8(r1) /* Save back chain and move SP */
778 lis r0, RESET_VECTOR@h /* Address of reset vector */
779 ori r0, r0, RESET_VECTOR@l
780 stwu r1, -8(r1) /* Save back chain and move SP */
781 stw r0, +12(r1) /* Save return addr (underflow vect) */
782 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
784 GET_GOT /* initialize GOT access */
786 bl cpu_init_f /* run low-level CPU init code (from Flash) */
789 bl board_init_f /* run first part of init code (from Flash) */
791 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
792 /*----------------------------------------------------------------------- */
795 /*****************************************************************************/
796 .globl _start_of_vectors
800 /*TODO Fixup _start above so we can do this*/
801 /* Critical input. */
802 CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
806 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
808 /* Data Storage exception. */
809 STD_EXCEPTION(0x300, DataStorage, UnknownException)
811 /* Instruction Storage exception. */
812 STD_EXCEPTION(0x400, InstStorage, UnknownException)
814 /* External Interrupt exception. */
815 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
817 /* Alignment exception. */
825 addi r3,r1,STACK_FRAME_OVERHEAD
827 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
828 lwz r6,GOT(transfer_to_handler)
832 .long AlignmentException - _start + EXC_OFF_SYS_RESET
833 .long int_return - _start + EXC_OFF_SYS_RESET
835 /* Program check exception */
839 addi r3,r1,STACK_FRAME_OVERHEAD
841 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
842 lwz r6,GOT(transfer_to_handler)
846 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
847 .long int_return - _start + EXC_OFF_SYS_RESET
849 /* No FPU on MPC8xx. This exception is not supposed to happen.
851 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
853 /* I guess we could implement decrementer, and may have
854 * to someday for timekeeping.
856 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
857 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
858 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
859 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
860 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
862 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
863 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
865 /* On the MPC8xx, this is a software emulation interrupt. It occurs
866 * for all unimplemented and illegal instructions.
868 STD_EXCEPTION(0x1000, PIT, PITException)
870 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
871 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
872 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
873 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
875 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
876 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
877 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
878 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
879 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
880 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
881 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
883 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
884 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
885 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
886 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
888 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
890 .globl _end_of_vectors
897 * This code finishes saving the registers to the exception frame
898 * and jumps to the appropriate handler for the exception.
899 * Register r21 is pointer into trap frame, r1 has new stack pointer.
901 .globl transfer_to_handler
913 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
915 addi r24,r1,STACK_FRAME_OVERHEAD
917 2: addi r2,r23,-TSS /* set r2 to current */
921 andi. r24,r23,0x3f00 /* get vector offset */
925 mtspr SPRG2,r22 /* r1 is now kernel sp */
927 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
931 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
933 lwz r24,0(r23) /* virtual address of handler */
934 lwz r23,4(r23) /* where to go when done */
939 rfi /* jump to handler, enable MMU */
942 mfmsr r28 /* Disable interrupts */
946 SYNC /* Some chip revs need this... */
961 lwz r2,_NIP(r1) /* Restore environment */
972 mfmsr r28 /* Disable interrupts */
976 SYNC /* Some chip revs need this... */
991 lwz r2,_NIP(r1) /* Restore environment */
993 mtspr 990,r2 /* SRR2 */
994 mtspr 991,r0 /* SRR3 */
1004 iccci r0,r0 /* for 405, iccci invalidates the */
1005 blr /* entire I cache */
1008 addi r6,0,0x0000 /* clear GPR 6 */
1009 /* Do loop for # of dcache congruence classes. */
1010 lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
1011 ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1012 /* NOTE: dccci invalidates both */
1013 mtctr r7 /* ways in the D cache */
1015 dccci 0,r6 /* invalidate line */
1016 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1021 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1023 mfmsr r12 /* save msr */
1025 mtmsr r9 /* disable EE and CE */
1026 addi r10,r0,0x0001 /* enable data cache for unused memory */
1027 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1028 or r10,r10,r9 /* bit 31 in dccr */
1031 /* do loop for # of congruence classes. */
1032 lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1033 ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1034 lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1035 ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1037 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1038 add r11,r10,r11 /* add to get to other side of cache line */
1039 ..flush_dcache_loop:
1040 lwz r3,0(r10) /* least recently used side */
1041 lwz r3,0(r11) /* the other side */
1042 dccci r0,r11 /* invalidate both sides */
1043 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1044 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1045 bdnz ..flush_dcache_loop
1046 sync /* allow memory access to complete */
1047 mtdccr r9 /* restore dccr */
1048 mtmsr r12 /* restore msr */
1051 .globl icache_enable
1054 bl invalidate_icache
1057 addis r3,r0, 0x8000 /* set bit 0 */
1061 .globl icache_disable
1063 addis r3,r0, 0x0000 /* clear bit 0 */
1068 .globl icache_status
1071 srwi r3, r3, 31 /* >>31 => select bit 0 */
1074 .globl dcache_enable
1077 bl invalidate_dcache
1080 addis r3,r0, 0x8000 /* set bit 0 */
1084 .globl dcache_disable
1089 addis r3,r0, 0x0000 /* clear bit 0 */
1093 .globl dcache_status
1096 srwi r3, r3, 31 /* >>31 => select bit 0 */
1104 #if !defined(CONFIG_440)
1116 /*------------------------------------------------------------------------------- */
1118 /* Description: Input 8 bits */
1119 /*------------------------------------------------------------------------------- */
1125 /*------------------------------------------------------------------------------- */
1126 /* Function: out8 */
1127 /* Description: Output 8 bits */
1128 /*------------------------------------------------------------------------------- */
1134 /*------------------------------------------------------------------------------- */
1135 /* Function: out16 */
1136 /* Description: Output 16 bits */
1137 /*------------------------------------------------------------------------------- */
1143 /*------------------------------------------------------------------------------- */
1144 /* Function: out16r */
1145 /* Description: Byte reverse and output 16 bits */
1146 /*------------------------------------------------------------------------------- */
1152 /*------------------------------------------------------------------------------- */
1153 /* Function: out32 */
1154 /* Description: Output 32 bits */
1155 /*------------------------------------------------------------------------------- */
1161 /*------------------------------------------------------------------------------- */
1162 /* Function: out32r */
1163 /* Description: Byte reverse and output 32 bits */
1164 /*------------------------------------------------------------------------------- */
1170 /*------------------------------------------------------------------------------- */
1171 /* Function: in16 */
1172 /* Description: Input 16 bits */
1173 /*------------------------------------------------------------------------------- */
1179 /*------------------------------------------------------------------------------- */
1180 /* Function: in16r */
1181 /* Description: Input 16 bits and byte reverse */
1182 /*------------------------------------------------------------------------------- */
1188 /*------------------------------------------------------------------------------- */
1189 /* Function: in32 */
1190 /* Description: Input 32 bits */
1191 /*------------------------------------------------------------------------------- */
1197 /*------------------------------------------------------------------------------- */
1198 /* Function: in32r */
1199 /* Description: Input 32 bits and byte reverse */
1200 /*------------------------------------------------------------------------------- */
1206 /*------------------------------------------------------------------------------- */
1207 /* Function: ppcDcbf */
1208 /* Description: Data Cache block flush */
1209 /* Input: r3 = effective address */
1211 /*------------------------------------------------------------------------------- */
1217 /*------------------------------------------------------------------------------- */
1218 /* Function: ppcDcbi */
1219 /* Description: Data Cache block Invalidate */
1220 /* Input: r3 = effective address */
1222 /*------------------------------------------------------------------------------- */
1228 /*------------------------------------------------------------------------------- */
1229 /* Function: ppcSync */
1230 /* Description: Processor Synchronize */
1233 /*------------------------------------------------------------------------------- */
1239 /*------------------------------------------------------------------------------*/
1242 * void relocate_code (addr_sp, gd, addr_moni)
1244 * This "function" does not return, instead it continues in RAM
1245 * after relocating the monitor code.
1249 * r5 = length in bytes
1250 * r6 = cachelinesize
1252 .globl relocate_code
1254 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
1256 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1257 * to speed up the boot process. Now this cache needs to be disabled.
1259 iccci 0,0 /* Invalidate inst cache */
1260 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1263 addi r1,r0,0x0000 /* TLB entry #0 */
1264 tlbre r0,r1,0x0002 /* Read contents */
1265 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1266 tlbwe r0,r1,0x0002 /* Save it out */
1270 mr r1, r3 /* Set new stack pointer */
1271 mr r9, r4 /* Save copy of Init Data pointer */
1272 mr r10, r5 /* Save copy of Destination Address */
1274 mr r3, r5 /* Destination Address */
1275 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1276 ori r4, r4, CFG_MONITOR_BASE@l
1277 lwz r5, GOT(__init_end)
1279 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1284 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1290 /* First our own GOT */
1292 /* the the one used by the C code */
1302 beq cr1,4f /* In place copy is not necessary */
1303 beq 7f /* Protect against 0 count */
1322 * Now flush the cache: note that we must start from a cache aligned
1323 * address. Otherwise we might miss one cache line.
1327 beq 7f /* Always flush prefetch queue in any case */
1335 sync /* Wait for all dcbst to complete on bus */
1341 7: sync /* Wait for all icbi to complete on bus */
1345 * We are done. Do not return, instead branch to second part of board
1346 * initialization, now running from RAM.
1349 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1351 blr /* NEVER RETURNS! */
1356 * Relocation Function, r14 point to got2+0x8000
1358 * Adjust got2 pointers, no need to check for 0, this code
1359 * already puts a few entries in the table.
1361 li r0,__got2_entries@sectoff@l
1362 la r3,GOT(_GOT2_TABLE_)
1363 lwz r11,GOT(_GOT2_TABLE_)
1373 * Now adjust the fixups and the pointers to the fixups
1374 * in case we need to move ourselves again.
1376 2: li r0,__fixup_entries@sectoff@l
1377 lwz r3,GOT(_FIXUP_TABLE_)
1391 * Now clear BSS segment
1393 lwz r3,GOT(__bss_start)
1407 mr r3, r9 /* Init Data pointer */
1408 mr r4, r10 /* Destination Address */
1412 * Copy exception vector code to low memory
1415 * r7: source address, r8: end address, r9: target address
1420 lwz r8, GOT(_end_of_vectors)
1422 li r9, 0x100 /* reset vector always at 0x100 */
1425 bgelr /* return if r7>=r8 - just in case */
1427 mflr r4 /* save link register */
1437 * relocate `hdlr' and `int_return' entries
1439 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1440 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1443 addi r7, r7, 0x100 /* next exception vector */
1447 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1450 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1453 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1454 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1457 addi r7, r7, 0x100 /* next exception vector */
1461 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1462 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1465 addi r7, r7, 0x100 /* next exception vector */
1469 #if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
1470 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1471 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1472 mtmsr r7 /* change MSR */
1475 b __440gx_msr_continue
1478 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1479 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1484 __440gx_msr_continue:
1487 mtlr r4 /* restore link register */
1491 * Function: relocate entries for one exception vector
1494 lwz r0, 0(r7) /* hdlr ... */
1495 add r0, r0, r3 /* ... += dest_addr */
1498 lwz r0, 4(r7) /* int_return ... */
1499 add r0, r0, r3 /* ... += dest_addr */
1505 /**************************************************************************/
1506 /* PPC405EP specific stuff */
1507 /**************************************************************************/
1511 #ifdef CONFIG_BUBINGA
1513 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1514 * function) to support FPGA and NVRAM accesses below.
1517 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1518 ori r3,r3,GPIO0_OSRH@l
1519 lis r4,CFG_GPIO0_OSRH@h
1520 ori r4,r4,CFG_GPIO0_OSRH@l
1523 ori r3,r3,GPIO0_OSRL@l
1524 lis r4,CFG_GPIO0_OSRL@h
1525 ori r4,r4,CFG_GPIO0_OSRL@l
1528 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1529 ori r3,r3,GPIO0_ISR1H@l
1530 lis r4,CFG_GPIO0_ISR1H@h
1531 ori r4,r4,CFG_GPIO0_ISR1H@l
1533 lis r3,GPIO0_ISR1L@h
1534 ori r3,r3,GPIO0_ISR1L@l
1535 lis r4,CFG_GPIO0_ISR1L@h
1536 ori r4,r4,CFG_GPIO0_ISR1L@l
1539 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1540 ori r3,r3,GPIO0_TSRH@l
1541 lis r4,CFG_GPIO0_TSRH@h
1542 ori r4,r4,CFG_GPIO0_TSRH@l
1545 ori r3,r3,GPIO0_TSRL@l
1546 lis r4,CFG_GPIO0_TSRL@h
1547 ori r4,r4,CFG_GPIO0_TSRL@l
1550 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1551 ori r3,r3,GPIO0_TCR@l
1552 lis r4,CFG_GPIO0_TCR@h
1553 ori r4,r4,CFG_GPIO0_TCR@l
1556 li r3,pb1ap /* program EBC bank 1 for RTC access */
1558 lis r3,CFG_EBC_PB1AP@h
1559 ori r3,r3,CFG_EBC_PB1AP@l
1563 lis r3,CFG_EBC_PB1CR@h
1564 ori r3,r3,CFG_EBC_PB1CR@l
1567 li r3,pb1ap /* program EBC bank 1 for RTC access */
1569 lis r3,CFG_EBC_PB1AP@h
1570 ori r3,r3,CFG_EBC_PB1AP@l
1574 lis r3,CFG_EBC_PB1CR@h
1575 ori r3,r3,CFG_EBC_PB1CR@l
1578 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1580 lis r3,CFG_EBC_PB4AP@h
1581 ori r3,r3,CFG_EBC_PB4AP@l
1585 lis r3,CFG_EBC_PB4CR@h
1586 ori r3,r3,CFG_EBC_PB4CR@l
1590 addi r3,0,CPC0_PCI_HOST_CFG_EN
1591 #ifdef CONFIG_BUBINGA
1593 !-----------------------------------------------------------------------
1594 ! Check FPGA for PCI internal/external arbitration
1595 ! If board is set to internal arbitration, update cpc0_pci
1596 !-----------------------------------------------------------------------
1598 addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1599 ori r5,r5,FPGA_REG1@l
1600 lbz r5,0x0(r5) /* read to get PCI arb selection */
1601 andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1602 beq ..pci_cfg_set /* if not set, then bypass reg write*/
1604 ori r3,r3,CPC0_PCI_ARBIT_EN
1606 mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1609 !-----------------------------------------------------------------------
1610 ! Check to see if chip is in bypass mode.
1611 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1612 ! CPU reset Otherwise, skip this step and keep going.
1613 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1614 ! will not be fast enough for the SDRAM (min 66MHz)
1615 !-----------------------------------------------------------------------
1617 mfdcr r5, CPC0_PLLMR1
1618 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1621 beq pll_done /* if SSCS =b'1' then PLL has */
1622 /* already been set */
1623 /* and CPU has been reset */
1624 /* so skip to next section */
1626 #ifdef CONFIG_BUBINGA
1628 !-----------------------------------------------------------------------
1629 ! Read NVRAM to get value to write in PLLMR.
1630 ! If value has not been correctly saved, write default value
1631 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1632 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1634 ! WARNING: This code assumes the first three words in the nvram_t
1635 ! structure in openbios.h. Changing the beginning of
1636 ! the structure will break this code.
1638 !-----------------------------------------------------------------------
1640 addis r3,0,NVRAM_BASE@h
1641 addi r3,r3,NVRAM_BASE@l
1644 addis r5,0,NVRVFY1@h
1645 addi r5,r5,NVRVFY1@l
1646 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1650 addis r5,0,NVRVFY2@h
1651 addi r5,r5,NVRVFY2@l
1652 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1654 addi r3,r3,8 /* Skip over conf_size */
1655 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1656 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1657 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1658 cmpi cr0,0,r5,1 /* See if PLL is locked */
1661 #endif /* CONFIG_BUBINGA */
1663 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1664 ori r3,r3,PLLMR0_DEFAULT@l /* */
1665 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1666 ori r4,r4,PLLMR1_DEFAULT@l /* */
1668 b pll_write /* Write the CPC0_PLLMR with new value */
1672 !-----------------------------------------------------------------------
1673 ! Clear Soft Reset Register
1674 ! This is needed to enable PCI if not booting from serial EPROM
1675 !-----------------------------------------------------------------------
1685 blr /* return to main code */
1688 !-----------------------------------------------------------------------------
1689 ! Function: pll_write
1690 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1692 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1694 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1695 ! 4. PLL Reset is cleared
1696 ! 5. Wait 100us for PLL to lock
1697 ! 6. A core reset is performed
1698 ! Input: r3 = Value to write to CPC0_PLLMR0
1699 ! Input: r4 = Value to write to CPC0_PLLMR1
1701 !-----------------------------------------------------------------------------
1706 ori r5,r5,0x0101 /* Stop the UART clocks */
1707 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1709 mfdcr r5, CPC0_PLLMR1
1710 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1711 mtdcr CPC0_PLLMR1,r5
1712 oris r5,r5,0x4000 /* Set PLL Reset */
1713 mtdcr CPC0_PLLMR1,r5
1715 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1716 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1717 oris r5,r5,0x4000 /* Set PLL Reset */
1718 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1719 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1720 mtdcr CPC0_PLLMR1,r5
1723 ! Wait min of 100us for PLL to lock.
1724 ! See CMOS 27E databook for more info.
1725 ! At 200MHz, that means waiting 20,000 instructions
1727 addi r3,0,20000 /* 2000 = 0x4e20 */
1732 oris r5,r5,0x8000 /* Enable PLL */
1733 mtdcr CPC0_PLLMR1,r5 /* Engage */
1736 * Reset CPU to guarantee timings are OK
1737 * Not sure if this is needed...
1740 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
1741 /* execution will continue from the poweron */
1742 /* vector of 0xfffffffc */
1743 #endif /* CONFIG_405EP */